WO2014082292A1 - 自对准金属氧化物薄膜晶体管器件及制造方法 - Google Patents

自对准金属氧化物薄膜晶体管器件及制造方法 Download PDF

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WO2014082292A1
WO2014082292A1 PCT/CN2012/085643 CN2012085643W WO2014082292A1 WO 2014082292 A1 WO2014082292 A1 WO 2014082292A1 CN 2012085643 W CN2012085643 W CN 2012085643W WO 2014082292 A1 WO2014082292 A1 WO 2014082292A1
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source
drain
metal oxide
gate
semiconductor layer
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PCT/CN2012/085643
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English (en)
French (fr)
Inventor
魏鹏
余晓军
刘自鸿
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深圳市柔宇科技有限公司
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to US14/648,628 priority Critical patent/US9564536B2/en
Priority to CN201280001858.9A priority patent/CN104040683B/zh
Priority to PCT/CN2012/085643 priority patent/WO2014082292A1/zh
Publication of WO2014082292A1 publication Critical patent/WO2014082292A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the invention belongs to the technical field of electronic devices, and in particular relates to a self-aligned metal oxide thin film transistor device and a method for fabricating the same.
  • TFT Metal oxide thin film transistor
  • Cgs gate-source parasitic capacitance
  • Cgd gate-drain parasitic capacitance
  • the prior art has a self-aligned device which is a device designed by a specific process to automatically align the source, the drain and the gate during the process manufacturing process, without manual or Alignment of the source, drain and gate can be achieved by mechanically optically aligning two different masks.
  • This self-aligned device is widely used in traditional single crystal silicon chips ( In the manufacturing process of MOSFETs, however, the self-aligned process of transistors in conventional silicon chips cannot be directly applied to metal oxide TFTs.
  • the prior art proposes a self-aligned process, using a top gate as a mask, automatically aligning to form a source, a drain, and passing Ar
  • the surface of the metal oxide indium gallium zinc oxide (IGZO) is treated by plasma or NH3 plasma containing more hydrogen to reduce the contact resistance of the source and drain, but Ar
  • the plasma only partially improves the surface resistance of the source and drain regions in contact with the metal.
  • the source and drain regions are still very resistant, and the plasma requires an additional process to increase the cost, while hydrogen can diffuse into the channel, causing the source.
  • the drain region extends to the channel, causing the overlap region of the gate and the source and the drain to increase, and the parasitic capacitance becomes large, thereby reducing the metal oxide.
  • etch barrier layer needs to be formed over the semiconductor layer to form separately by double exposure Etching the barrier layer and the source and drain, and the two back exposure self-alignments increase the use of the lithography mask and greatly increase the difficulty of the process. At the same time, the etch barrier also adversely affects the semiconductor channel, which in turn affects the TFT. Electrical characteristics.
  • Another example is the Chinese patent application CN201110147134, which discloses a TFT.
  • the manufacturing process uses a mask having a slit having a width smaller than the resolution of the exposure machine, and by changing the exposure amount, the preparation of the source/drain electrodes and the semiconductor channel is completed by a set of masks, but the channel size is strictly controlled by the exposure machine.
  • the specification is limited, and the exposure amount needs more precise control to distinguish the source and drain electrodes from the semiconductor channel, so it is subject to a large limitation, is difficult to apply, and is not conducive to the reduction of the manufacturing cost.
  • An object of the present invention is to provide a method of fabricating a self-aligned metal oxide thin film transistor device, which is intended to solve the conventional method A problem that creates parasitic capacitance and is complicated in process.
  • the present invention is achieved by the method of fabricating a self-aligned metal oxide thin film transistor device comprising the steps of:
  • a method of fabricating a self-aligned metal oxide thin film transistor device comprising the steps of:
  • An insulating layer, a transparent electrode layer and a photoresist are sequentially disposed on the gate;
  • the gate as a mask, exposing from the back of the substrate, removing a portion of the transparent electrode layer aligned with the gate to form a source and a drain aligned with the gate;
  • Etching the metal oxide semiconductor layer and the source and the drain exposing the outer ends of the source and the drain to the outside of the etched metal oxide semiconductor layer, and isolating the source and drain of different thin film transistor devices pole;
  • a passivation layer is deposited over the substrate and the source and drain are taken out of the passivation layer.
  • Another object of the present invention is to provide a self-aligned metal oxide thin film transistor device comprising:
  • a gate electrode and an insulating layer are sequentially stacked on the substrate;
  • a source and a drain are disposed side by side on the insulating layer and are transparent electrodes;
  • a metal oxide semiconductor layer disposed over the source and the drain and forming a channel between the source and the drain, both sides of the channel and an inner side of the source and the drain Aligning
  • a passivation layer encapsulating one side of the substrate with a gate
  • the source and drain are led out of the passivation layer by a conductive material.
  • a further object of the present invention is to provide a A method of fabricating a self-aligned metal oxide thin film transistor pixel circuit, comprising the steps of:
  • An insulating layer, a transparent electrode layer and a photoresist are sequentially disposed on the gate, the gate lead and the storage capacitor electrode;
  • Etching the metal oxide semiconductor layer and the source and the drain exposing the outer ends of the source and the drain to the outside of the etched metal oxide semiconductor layer, and isolating the source of the different thin film transistor devices And drain;
  • a passivation layer is deposited over the substrate and the source, drain and gate leads are taken out of the passivation layer.
  • a self-aligned metal oxide thin film transistor pixel circuit comprising:
  • a gate electrode, a gate lead and a storage capacitor electrode are disposed side by side on the substrate;
  • An insulating layer disposed on the gate and the storage capacitor electrode
  • a source and a drain are transparent electrodes disposed side by side on a region of the insulating layer corresponding to the gate;
  • a metal oxide semiconductor layer disposed over the source and the drain and forming a channel between the source and the drain, both sides of the channel and an inner side of the source and the drain Aligning
  • a passivation layer encapsulating one side of the substrate with a gate
  • the source, drain and gate leads are led out of the passivation layer by a conductive material.
  • the method uses the bottom gate as a mask for back exposure, achieving high-precision self-alignment of the source and drain electrodes with the channel and the gate, and the overlapping area of the source and drain electrodes and the gate can be precisely controlled at 2 ⁇ m.
  • it is much higher than the precision of the traditional mask alignment, effectively reducing the parasitic capacitance, improving the circuit speed of the device, and making the channel size control more precise, which is beneficial to minimize the channel size and improve the device performance.
  • mask alignment in the production process is no longer a critical alignment requirement, which reduces manufacturing difficulties.
  • the device is a bottom gate and bottom contact structure, it is not necessary to perform an etching process on the semiconductor layer, so there is no need to make an etch barrier layer, and only one step of back exposure is performed, thereby simplifying the process and reducing the light.
  • the use of the mask improves the production efficiency and avoids the adverse effect of the etch barrier on the semiconductor channel; and the use of the bottom contact structure makes it easier to transport carriers, improving The electrical characteristics of the device.
  • the present invention does not need to use the high-precision and expensive mask, and the channel size is not strictly limited by the lithography apparatus, and the manufacturing process It is easy to implement and solves other process problems of traditional mask alignment, and is suitable for a wide range of applications.
  • FIG. 1 is a schematic structural view of a conventional metal oxide thin film transistor device
  • FIG. 2 is a flow chart of a method of fabricating a self-aligned metal oxide thin film transistor device according to a first embodiment of the present invention
  • Figure 3-1 to Figure 3-10 It is a schematic structural diagram corresponding to each step in the manufacturing method of the self-aligned metal oxide thin film transistor device provided by the first embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a self-aligned metal oxide thin film transistor device according to a first embodiment of the present invention
  • FIG. 5 is a flow chart of a method for fabricating a pixel circuit of a self-aligned metal oxide thin film transistor according to a second embodiment of the present invention
  • Figure 6-1 to Figure 6-10 It is a schematic structural diagram corresponding to each step in the manufacturing method of the pixel circuit of the self-aligned metal oxide thin film transistor provided by the second embodiment of the present invention.
  • FIG. 2 is a flow chart showing a method of fabricating a self-aligned metal oxide thin film transistor device according to a first embodiment of the present invention.
  • 3-1 to 3-10 show schematic views corresponding to the manufacturing method, and for convenience of explanation, only parts related to the present embodiment are shown.
  • the method includes the following steps:
  • step S101 a substrate 11 is selected, and a gate 12 is prepared on the substrate 11; as shown in FIG. 3-1 .
  • the substrate 11 The transparent material is selected, and the 'transparent' in this embodiment is a material which is transparent to light waves used in the photolithography process, and then the gate 12 is formed using the first photolithographic mask.
  • the gate 12 is formed using the first photolithographic mask.
  • a buffer layer is placed on top of it.
  • step S102 an insulating layer 13, a transparent electrode layer 14, and a photoresist are sequentially disposed over the gate electrode 12. ; Figure 3-2, 3-3, 3-4.
  • an insulating layer 13 is first deposited on the substrate 11 and the gate electrode 12, as shown in FIG. 3-2.
  • the insulating layer 13 may be a SiO 2 film, a SiN X film or a SiO 2 and SiN X layer.
  • a transparent film structure such as a film.
  • a transparent electrode layer 14 is deposited over the insulating layer 13, as shown in Fig. 3-3, which is specifically selected from transparent conductive materials such as ITO, IZO or GZO.
  • a photoresist 15 is applied over the transparent electrode layer 14 for subsequent lithography, as shown in FIG. 3-4.
  • step S103 the gate 12 is used as a mask, exposed from the back of the substrate 11, and removed from the gate 12
  • the partially transparent electrode layer 14 is aligned to form a source 141 and a drain 142 aligned with the gate electrode 12; as shown in FIGS. 3-4 and 3-5.
  • the metal material as the gate electrode 12 is opaque, and the other structures are transparent materials, so the gate electrode 12
  • the transparent electrode layer 14 can be photolithographically used as a mask to prepare a source 141 and a drain 142. Specifically, this step uses the gate 12 as a mask from the substrate 11
  • the back exposure and development, the exposed transparent electrode layer 14 is cured, and the unexposed portion opposite to the gate 12 is stripped together with the photoresist 15 at the gate 12
  • the upper region is the reserved channel portion 16, and the source 141 and drain 142 are well self-aligned with the gate 12.
  • step S104 a metal oxide semiconductor layer 17 is deposited over the source 141 and the drain 142; 3-6.
  • the deposited metal oxide semiconductor layer 17 covers the source 141 and the drain 142.
  • a semiconductor channel 171 is formed, mainly serving as a channel for carrier transport between the source and drain electrodes, and the specific material thereof may be IGZO or the like.
  • step S105 the metal oxide semiconductor layer 17 and the source and drain electrodes 141 and 142 are etched and the source is turned on. The outer ends of the 141 and the drain 142 are exposed outside the etched metal oxide semiconductor layer 17, and the source and drain of the different thin film transistor devices are isolated; as shown in Fig. 3-7.
  • the source 141 and the drain 142 may be etched by using a second lithography mask-tone mask 20. And a metal oxide semiconductor layer 17 .
  • the gray scale mask 20 provides variable transmittance at different positions of the plane of the mask.
  • a suitable gray mask is selected to make the corresponding transmittance region and the source to be etched.
  • the drain 142 and the metal oxide semiconductor layer 17 are properly aligned, exposed from the front side of the substrate 11, etching away most of the metal oxide semiconductor layer 17 and a relatively small number of sources 141
  • the drain electrode 142, the remaining metal oxide semiconductor layer 17 and the source and drain electrodes have a stepped structure, and the outer ends of the source electrode 141 and the drain electrode 142 are exposed to the remaining metal oxide semiconductor layer. Outside.
  • the device is fabricated in a single process for a plurality of TFT devices, and after the above etching, the source and drain of the different thin film transistor devices are also isolated.
  • This step simultaneously realizes the metal oxide semiconductor layer 17 and the source 141 and the drain 142 using a gray scale mask.
  • the etching saves one photolithography step and reduces the use of a photolithography mask, which saves material and simplifies the process, compared with the method of separately etching the metal oxide semiconductor layer and the source and drain electrodes. Conducive to improving production efficiency.
  • step S106 a passivation layer 18 is deposited over the substrate 11, and the source 141 and the drain 142 are deposited. Lead out to the passivation layer 18. See Figures 3-8, 3-9, 3-10.
  • the passivation layer 18 can be etched using a third photolithographic mask to form a source 141 and a drain. 142 is exposed to the via 181 outside the metal oxide semiconductor layer 17, and then a conductive material 19 is deposited on the passivation layer 18, preferably a transparent conductive material such as a transparent metal oxide, a conductive material 19 The passivation layer 18 is covered and implanted into the via 181 to be in contact with the source 141 and the drain 142. Then, the conductive material 19 is etched by using a fourth photolithography mask to form a conductive lead to source 141. And drain 142 leads.
  • the device can be fabricated. It can be understood that the above description only describes the manufacturing process of the main structure of the metal oxide thin film transistor device. Of course, the device also includes other conventional functional structures, which can be fabricated by a conventional method, and the present invention does not. Let me repeat.
  • the opaque bottom gate is used as a mask, and the source drain and the semiconductor channel are automatically aligned by the back exposure to form a self-aligned bottom gate and bottom contact metal oxide TFT.
  • This method has the following effects:
  • the device is a bottom gate and bottom contact structure, it is not necessary to perform an etching process on the semiconductor layer, so there is no need to make an etch barrier layer, so that only one step of back exposure is performed, thereby simplifying the process and reducing the process.
  • the use of a lithography mask improves production efficiency and avoids the adverse effect of the etch barrier on the semiconductor channel; in addition, the bottom contact structure makes it easier for carriers to be between the source-semiconductor channel-drain Transmission, improved The electrical characteristics of the device.
  • the one-step photolithography process can be reduced and the use of the photolithography mask can be reduced, the cost can be reduced, and the production efficiency can be improved.
  • the present invention does not need to use the high-precision and expensive mask, the channel size is not strictly limited by the lithography apparatus, and the manufacturing process is easy. Implementation, while solving the other process problems of traditional mask alignment.
  • the embodiment of the present invention further provides a self-aligned metal oxide thin film transistor device which can be fabricated by the above manufacturing process.
  • the device is a bottom gate, bottom contact structure TFT device, which mainly includes a substrate 11 on the substrate 11 A gate electrode 12 and an insulating layer 13 are stacked in this order, and a transparent source electrode 141 and a drain electrode 142 are disposed side by side on the surface of the insulating layer 13, at the source electrode 141 and the drain electrode 142.
  • a metal oxide semiconductor layer 17 and a metal oxide semiconductor layer 17 forms a semiconductor channel 171 for carrier transport between the source 141 and the drain 142, and a semiconductor channel Both sides of 171 are aligned with the inner sides of source 141 and drain 142.
  • a passivation layer 18 is provided on the substrate 11 to seal all the structures on the substrate 11. Among them, the source 141 And the drain 142 is led out to the passivation layer 18 through the conductive material 19, and is electrically connected to an external circuit.
  • the metal oxide semiconductor layer 17 may cover part of the source 141 and the drain 142 to make the source 141 and the drain
  • the outer end of the 142 is exposed outside the metal oxide semiconductor layer 17, and is further preferably symmetrical with respect to the metal oxide semiconductor layer 17.
  • the passivation layer 18 can be opened to the source 141 And a via 181 of the exposed portion of the drain 142, the via 181 is filled with a transparent conductive material 19, and the source 141 and the drain 142 are led out of the passivation layer 18.
  • the source 141 and the drain 142 of the device and the semiconductor channel 171 are formed by the back exposure process described above.
  • the width of the overlap region can be reduced to less than 2 ⁇ m, which is much smaller than the overlap area of the conventional device, thereby effectively reducing the parasitic capacitance and improving the device performance.
  • the self-aligned metal oxide thin film transistor device may further include other functional structures, which are not described in this embodiment, and the metal oxide thin film transistor device fabricated by the above method is within the protection scope of the present invention. .
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 5 is a flow chart showing a method of fabricating a self-aligned metal oxide thin film transistor pixel circuit according to a second embodiment of the present invention.
  • 6-1 to 6-10 show schematic views corresponding to the manufacturing method, and for convenience of explanation, only the parts related to the present embodiment are shown.
  • the method includes the following steps:
  • step S201 a substrate 21 is selected, and a gate 221 and a gate lead 222 are prepared on the substrate 21. And storage capacitor electrode 223; as shown in Figure 6-1.
  • the substrate 21 Selectively made of a transparent material, the 'transparent' in this embodiment is a material that is transparent to light waves used in the photolithography process, and then the first photolithographic mask is used to form the gate electrode 221, the gate lead 222, and the storage capacitor electrode. 223.
  • a buffer layer may be disposed on the substrate 21 first.
  • step S202 an insulating layer is sequentially disposed over the gate electrode 221, the gate lead 222, and the storage capacitor electrode 223. 23, transparent electrode layer 24 and photoresist 25; as shown in Figures 6-2, 6-3, 6-4.
  • the insulating layer 23 is first deposited, as shown in Fig. 6-2, and the insulating layer 23 may be a transparent film structure such as a SiO 2 film, a SiN X film, or a multilayer film in which SiO 2 and SiN X are laminated.
  • a transparent electrode layer 24 is deposited over the insulating layer 23, as shown in Fig. 6-3, which may specifically be a transparent conductive material such as ITO, IZO or GZO.
  • a photoresist 25 is applied over the transparent electrode layer 24 for subsequent lithography, as shown in FIG. 6-4.
  • step S203 the gate electrode 221, the gate lead 222 and the storage capacitor electrode 223 are used as a mask from the substrate.
  • the back exposure of 21 removes a portion of the transparent electrode layer 24 aligned with the gate electrode 221, the gate lead 222, and the storage capacitor electrode 223 to form a source 241 and a drain aligned with the gate electrode 221 242; as shown in Figures 6-4 and 6-5.
  • the non-transparent gate electrode 221, the gate lead 222 and the storage capacitor electrode 223 are used as a mask from the substrate 21
  • step S204 at the source 241 and the drain 242 and other remaining transparent electrode layers 24 A metal oxide semiconductor layer 27 is deposited thereon; as shown in Fig. 6-6.
  • step S205 the metal oxide semiconductor layer 27 and the source 241 and the drain 242 are etched to make the source 241 And the outer end of the drain 242 is exposed outside the etched metal oxide semiconductor layer 27, and isolates the source and drain of different thin film transistor devices; as shown in Fig. 6-7.
  • the source 241 and the drain 242 may be etched by using a second lithography mask-tone mask 30. And a metal oxide semiconductor layer 27 .
  • the corresponding transmittance regions of the gray mask 20 are properly aligned with the source 241, the drain 242 and the metal oxide semiconductor layer 27 to be etched, from the substrate 21
  • the front side exposes the transparent electrode layer 24 and the metal oxide semiconductor layer 27 on the gate lead 222 and the storage capacitor electrode 223, and the source 241 and the drain on the gate 221 are drained.
  • the 242 and the metal oxide semiconductor layer 27 are stepwise etched so that the outer ends of the etched source 241 and drain 242 are exposed outside the remaining metal oxide semiconductor layer 27.
  • This embodiment simultaneously realizes the metal oxide semiconductor layer 27 using a gray scale mask.
  • the etching of the source and drain electrodes saves one photolithography step and reduces the use of a photolithography mask, which saves material and simplifies, compared with the method of respectively etching the metal oxide semiconductor layer and the source and drain electrodes.
  • the process is conducive to improving production efficiency.
  • step S206 a passivation layer 28 is deposited over the substrate 21, and the source 241 and the drain 242 are deposited. And the gate lead 222 is led out of the passivation layer 28. See Figures 6-8, 6-9, 6-10.
  • the passivation layer 28 may be etched using a third lithography mask to form a gate lead 222. And a source 241, a drain 242 exposed to the via 281 outside the metal oxide semiconductor layer 27, and then a conductive material is deposited on the passivation layer 28.
  • it is a transparent conductive material such as a transparent metal oxide
  • the conductive material 29 covers the passivation layer 28 and is implanted into the via 281, with the source 241, the drain 242 and the gate lead 222. Contact.
  • the conductive material 29 is etched using a fourth lithography mask to form a conductive lead to lead the source 241, the drain 242, and the gate lead 222.
  • the pixel circuit is formed. It can be understood that the manufacturing process of the main structure of the pixel circuit is described above. Of course, the device also includes other conventional functional structures, which can be fabricated by a conventional method, and the description of the present invention will not be repeated. .
  • the opaque bottom gate, the gate lead and the storage capacitor electrode are used as a mask, and the source drain and the gate are automatically aligned by the back exposure to form a self-aligned bottom gate and bottom contact structure.
  • Metal oxide TFT Pixel circuit This method has the same effect as the above embodiment, and will not be described in detail in this embodiment.
  • Embodiments of the present invention further provide a metal oxide TFT pixel circuit which can be fabricated by the above method.
  • the device is a metal oxide TFT pixel circuit with a bottom gate and a bottom contact structure, which mainly includes a substrate. 21, a gate electrode 221, a gate lead 222, and a storage capacitor electrode 223 are arranged side by side on the substrate 21, and an insulating layer is disposed on the gate electrode 221 and the storage capacitor electrode 223.
  • a transparent source 241 and a drain 242 are arranged side by side in a region corresponding to the gate 221 on the surface of the insulating layer 23, and a metal oxide semiconductor layer is above the source 241 and the drain 242.
  • the metal oxide semiconductor layer 27 forms a channel for carrier transport between the source 241 and the drain 242, that is, the semiconductor channel 271, the two sides and the source of the semiconductor channel 271 241 is aligned with the inner side of the drain 242. Further, a passivation layer 28 is provided on the substrate 21 to seal all the structures above the substrate 21. Wherein, source 241, drain 242 And the gate lead 222 is led out to the passivation layer 28 through the conductive material 29, and is electrically connected to an external circuit.
  • the metal oxide semiconductor layer 27 may cover part of the source 241 and the drain 242 to make the source 241 and the drain
  • the outer ends of 242 are exposed outside the metal oxide semiconductor layer 27, and further preferably are symmetrical to each other outside the metal oxide semiconductor layer 27.
  • the passivation layer 28 can be opened to the gate lead 222.
  • the via 281 of the exposed portion of the source 241 and the drain 242 is filled with a transparent conductive material 29, and the source 241 and the drain 242 are led out to the passivation layer. Outside.
  • the source 241 and the drain 242 of the device and the semiconductor channel 271 are formed by the back exposure process described above.
  • the width of the overlap region can be reduced to less than 2 ⁇ m, which is much smaller than the overlap area of the conventional device, thereby effectively reducing the parasitic capacitance and improving the device performance.
  • the self-aligned metal oxide thin film transistor pixel circuit may further include other functional structures, which are not described in this embodiment, and the metal oxide thin film transistor pixel circuits fabricated by the above method are all protected by the present invention. Within the scope.

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Abstract

提供了一种自对准金属氧化物TFT器件的制造方法，包括：选取基板（11），在基板（11）上制备栅极（12）；在栅极（12）上依次设置绝缘层（13）、透明电极层（14）及光刻胶（15）；以栅极（12）为掩膜，自基板（11）背部曝光，形成与栅极（12）对准的源漏极（141、142）；在透明电极层（14）上沉积金属氧化物半导体层（17）；刻蚀半导体层（17）及源漏极（141、142），使源漏极（141、142）的外端露于金属氧化物半导体层之外；沉积钝化层（18），并将源漏极（141、142）引出。采用透明导体作为电极层，并以底栅为掩膜进行背部曝光刻蚀源漏电极，实现源漏极与栅极自对准，有效减弱了寄生电容，提高了器件性能。该器件为底栅、底接触结构，无需制作刻蚀阻挡层，简化了工艺，减少了光刻掩膜的使用，提高了效率，并改善了器件的电学特性。

Description

自对准金属氧化物薄膜晶体管器件及制造方法 技术领域
本发明属于电子器件技术领域，特别涉及一种自对准金属氧化物薄膜晶体管器件及其制造方法。
背景技术
金属氧化物薄膜晶体管 (TFT) 是一种可广泛用于各种电子系统的基本电路组成器件，其具有多种优势，如高电子迁移率、低温制造工艺、较高的稳定性、透明度高等等。如图 1 所示，在传统的 TFT 制造工艺中， TFT 器件的栅极 (Gate)101 与源极 (Source)102 、漏极 (Drain)103 的对准是采用两层不同的掩膜板通过手动或者机械的光学对准方式实现的。 由于对准设备的精度等因素的限制，这种方式会导致源极 102 、漏极 103 与栅极 101 之间存在一定的重叠，因而产生较大的栅源寄生电容 (Cgs) 及栅漏寄生电容（ Cgd ）。 较大的寄生电容通常会降低器件的截止频率 ( 截止频率反比于寄生电容 ) ，从而降低电路的运行速度；并且，较大的寄生电容也导致显示电极电压偏离设计要求，从而需要复杂的栅极驱动电路来补偿偏差，增加了电路设计的复杂性；此外，无法精确控制的寄生电容也增加了电路设计的复杂性和不确定性，并使沟道 (Channel) 的最小尺寸无法精确，进而限制了沟道尺寸的最小化，从而难以提高器件的性能。另外，传统器件中使用多层掩膜板也会增加工艺复杂度并增加成本，不利于提高生产效率。
为了解决上述问题，现有技术出现一种自对准器件，它是一种通过特定的工艺设计、可以在工艺制造过程中自动将源极、漏极与栅极相对准的器件，无需手动或者通过机械光学对准两层不同掩膜板即可实现源极、漏极与栅极的对准。这种自对准器件广泛应用于传统的单晶硅芯片（ MOSFET ）的制造过程中，但是，传统硅芯片中的晶体管的自对准工艺却无法直接应用于金属氧化物 TFT 上。
为解决该问题，现有技术提出一种自对准工艺，利用顶栅极作为掩膜，自动对准形成源、漏极，并通过 Ar 等离子体或者含氢较多的 NH3 等离子体处理金属氧化物氧化铟镓锌（ IGZO ）的表面，以降低源、漏极的接触电阻，但是 Ar 等离子体只是部分改善了源、漏区与金属接触的表面电阻，源、漏区电阻仍然很大，而且等离子体需要一道额外工艺处理，增加了成本，而氢则能扩散到沟道，导致源、漏区延伸到沟道，导致栅极和源、漏极的重叠区域增大，寄生电容变大，进而减低金属氧化物 TFT 器件的性能。
在其他现有的自对准工艺中， 如中国专利申请 CN201080017247 ， 需要在半导体层之上形成刻蚀阻挡层，通过两次曝光分别形成 刻蚀阻挡层和源漏极，两次背面曝光自对准，增加了光刻掩膜的使用并大幅度的增加了工艺实现的难度。同时，刻蚀阻挡层也会对半导体沟道产生不良影响，进而影响 TFT 的电学特性。
又如中国专利申请 CN201110147134 ，公开了一种 TFT 制造工艺，使用具有宽度小于曝光机分辨率缝隙的掩膜板，通过改变曝光量，实现用一套掩膜板分别完成对源漏电极和半导体沟道的制备，但沟道尺寸严格受到曝光机规格的制约，并且曝光量需要较精确的控制以区别源漏电极和半导体沟道，因此会受到较大的限制，较难以应用，亦不利于制备成本的降低。
 技术问题
本发明的目的 在于提供一种 自对准金属氧化物薄膜晶体管器件的制造方法，旨在解决传统方法容易 产生寄生电容且工艺复杂的问题。
技术解决方案
本发明是这样实现的， 自对准金属氧化物薄膜晶体管器件的制造方法，包括下述步骤：
自对准金属氧化物薄膜晶体管器件的制造方法，包括下述步骤：
选取一基板，在所述基板之上制备栅极；
在所述栅极之上依次设置绝缘层、透明电极层及光刻胶；
以所述栅极为掩膜，自所述基板的背部曝光，去除与所述栅极对位的部分透明电极层，以形成与所述栅极对准的源极和漏极；
在所述源极和漏极之上沉积金属氧化物半导体层；
刻蚀所述金属氧化物半导体层及源极和漏极，使源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极；
向所述基板之上沉积钝化层，并将所述源极和漏极引出至所述钝化层之外。
本发明的另一目的 在于提供 一种自对准金属氧化物薄膜晶体管器件，包括：
基板；
栅极和绝缘层，依次叠层设置于所述基板之上；
源极和漏极，并排设置于所述绝缘层之上，且为透明电极；
金属氧化物半导体层，设置于所述源极和漏极之上，并在所述源极和漏极之间形成沟道，所述沟道的两边与所述源极和漏极的内侧边对准；
钝化层，包封于所述基板设有栅极的一面；
所述源极和漏极通过导电材料引出至所述钝化层之外。
本发明的再一目的 在于提供一种 自对准金属氧化物薄膜晶体管像素电路的制造方法，包括下述步骤：
选取一基板，在所述基板之上制备栅极、栅极引线和存储电容电极；
在所述栅极、栅极引线和存储电容电极之上依次设置绝缘层、透明电极层及光刻胶；
以所述栅极、栅极引线和存储电容电极为掩膜，自所述基板的背部曝光，去除与所述栅极、栅极引线和存储电容电极对位的部分透明电极层，形成与所述栅极对准的源极和漏极；
在所述源极和漏极以及其他保留的透明电极层之上沉积金属氧化物半导体层；
刻蚀所述金属氧化物半导体层及源极和漏极，使所述源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极；
向所述基板之上沉积钝化层，并将所述源极、漏极和栅极引线引出至所述钝化层之外。 本发明的又一目的 在于提供 一种 自对准金属氧化物薄膜晶体管像素电路，包括：
基板；
栅极、栅极引线和存储电容电极，并排设置于所述基板之上；
绝缘层，设置于所述栅极和存储电容电极之上；
源极和漏极，为透明电极，并排设置于所述绝缘层上与所述栅极对应的区域；
金属氧化物半导体层，设置于所述源极和漏极之上，并在所述源极和漏极之间形成沟道，所述沟道的两边与所述源极和漏极的内侧边对准；
钝化层，包封于所述基板设有栅极的一面；
所述源极、漏极和栅极引线通过导电材料引出至所述钝化层之外。
 有益效果
本发明具有下述有益效果：
一方面，该方法以底栅极为掩膜进行背部曝光，实现源漏电极与沟道、栅极的高精度自对准，源漏电极与栅极的重叠区域可精确控制在 2 μ m 以内，远高于传统掩膜对位的精度，有效的减弱了寄生电容，提高了器件的电路速度，并且使沟道尺寸的控制更加精确，有利于实现沟道尺寸的最小化，提高器件性能；并且，生产流程中的掩膜板对准不再是关键的对准要求，进而降低了制造难度。
另一方面，由于该器件为底栅、底接触结构，不需在半导体层之上再进行刻蚀工艺，因此无需制作刻蚀阻挡层，只需一步背部曝光，从而简化了工艺，减少了光刻掩膜的使用，提高了生产效率，并且避免了刻蚀阻挡层对半导体沟道的不良影响；并且，采用底接触结构更易于载流子的传输，改善了 器件的电学特性。
另外，与采用 宽度小于曝光机分辨率缝隙的掩膜板进行刻蚀的方法相比，本发明也无需使用该高精度且昂贵的掩膜板，沟道尺寸不受光刻设备的严格限制，且该制造工艺易于实现，同时解决了传统的掩膜板对准的其他工艺问题，适合广泛应用。
 附图说明
图 1 是现有金属氧化物薄膜晶体管器件的结构示意图；
图 2 是本发明第一实施例提供的自对准金属氧化物薄膜晶体管器件的制造方法流程图；
图 3-1 至图 3-10 是本发明第一实施例提供的自对准金属氧化物薄膜晶体管器件的制造方法中各步骤对应的结构示意图；
图 4 是本发明第一实施例提供的自对准金属氧化物薄膜晶体管器件的结构示意图；
图 5 是本发明第二实施例提供的自对准金属氧化物薄膜晶体管像素电路的制造方法流程图；
图 6-1 至图 6-10 是本发明第二实施例提供的自对准金属氧化物薄膜晶体管像素电路的制造方法中各步骤对应的结构示意图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
以下结合具体实施例对本发明的具体实现进行详细描述：
图 2 示出了本发明第一实施例提供的自对准金属氧化物薄膜晶体管器件的制造方法流程图，图 3-1~3-10 示出了与该制造方法相对应的结构示意图，为了便于说明，仅示出了与本实施例相关的部分。
如图 2 ，该方法包括下述步骤：
在步骤 S101 中，选取一基板 11 ，在基板 11 之上制备栅极 12 ；如图 3-1 。
在此步骤中，基板 11 选择透明材料制作，本实施例中的'透明'是指针对光刻工艺中使用的光波透明的材料，然后使用第一个光刻掩膜制作栅极 12 。可选的，还可以在基板 11 之上设置一缓冲层。
在步骤 S102 中，在栅极 12 之上依次设置绝缘层 13 、透明电极层 14 及光刻胶 15 ；如图 3-2 、 3-3 、 3-4 。
在此步骤中，首先在基板 11 及栅极 12 之上沉积绝缘层 13 ，如图 3-2 ，该绝缘层 13 可以是 SiO2 膜、 SiNX 膜或 SiO2 与 SiNX 叠层分布的多层膜等透明的膜结构。沉积绝缘层 13 之后，在绝缘层 13 之上沉积透明电极层 14 ，如图 3-3 ，其具体可选 ITO 、 IZO 或 GZO 等透明导电材料。之后，在透明电极层 14 之上涂覆光刻胶 15 ，待后续光刻使用，如图 3-4 。
在步骤 S103 中，以栅极 12 为掩膜，自基板 11 的背部曝光，去除与栅极 12 对位的部分透明电极层 14 ，以形成与栅极 12 对准的源极 141 和漏极 142 ；如图 3-4 、 3-5 。
在本实施例中，作为栅极 12 的金属材料是非透明的，而其他结构均为透明材质，因此栅极 12 可以作为掩膜对透明电极层 14 进行光刻以制备源极 141 、漏极 142 。具体的，此步骤以栅极 12 为掩膜，从基板 11 的背部曝光、显影，被曝光的透明电极层 14 被固化保留，与栅极 12 相对位的未被曝光的部分连同光刻胶 15 一起被剥离，在栅极 12 之上的区域为预留的沟道部分 16 ，，而源极 141 和漏极 142 与栅极 12 实现了良好的自对准。
在步骤 S104 中，在源极 141 和漏极 142 之上沉积金属氧化物半导体层 17 ；如图 3-6 。
此步骤中，沉积的金属氧化物半导体层 17 覆盖在源极 141 和漏极 142 上及上述步骤预留的沟道中，形成半导体沟道 171 ，主要作为源漏电极之间载流子传输的通道 , ，其具体材料可选择 IGZO 等。
在步骤 S105 中，刻蚀金属氧化物半导体层 17 及源极 141 和漏极 142 ，并使源极 141 和漏极 142 的外端露于刻蚀后的金属氧化物半导体层 17 之外，并且隔离不同薄膜晶体管器件的源极和漏极；如图 3-7 。
作为本实施例优选的实现方式，可采用第二个光刻掩膜-灰度掩模板 20 刻蚀源极 141 、漏极 142 和金属氧化物半导体层 17 。灰度掩模板 20 在掩膜板平面的不同位置提供可变的透过率，在本实施例中，选择合适的灰度掩模板，使相应透过率区域与待刻蚀的源极 141 、漏极 142 和金属氧化物半导体层 17 进行合理对位，自基板 11 正面曝光，刻蚀掉大部分金属氧化物半导体层 17 和相对少部分源极 141 、漏极 142 ，保留的金属氧化物半导体层 17 和源漏极为阶梯结构，源极 141 和漏极 142 的外端露于保留的金属氧化物半导体层 17 之外。并且，该器件的制作为多个 TFT 器件在一次制程中制造，通过上述刻蚀后，也使得属于不同薄膜晶体管器件的源极和漏极得以隔离。
此步骤使用一个灰度掩模板同时实现了金属氧化物半导体层 17 和源极 141 、漏极 142 的刻蚀，与分别刻蚀金属氧化物半导体层和源漏极的方法相比，节省了一次光刻步骤，也减少了一个光刻掩膜的使用，既节约物料，又简化了工艺，有利于提高生产效率。
在步骤 S106 中，向基板 11 之上沉积钝化层 18 ，并将源极 141 和漏极 142 引出至钝化层 18 之外。如图 3-8 、 3-9 、 3-10 。
作为本实施例的一种实现方式，可以使用第三个光刻掩膜刻蚀钝化层 18 ，形成通向源极 141 和漏极 142 露于金属氧化物半导体层 17 之外部分的过孔 181 ，然后向钝化层 18 沉积导电材料 19 ，优选为透明导电材料，如透明金属氧化物，导电材料 19 覆盖钝化层 18 并注入过孔 181 中，与源极 141 和漏极 142 接触。然后，采用第四个光刻掩膜刻蚀导电材料 19 ，形成导电引线将源极 141 和漏极 142 引出。
经过上述步骤后，自对准金属氧化物 TFT 器件得以制成，可以理解，以上仅对金属氧化物薄膜晶体管器件的主体结构的制造工艺进行了说明，当然，该器件还包括其他常规的功能结构，其可采用常规的方法制作，本发明不再赘述。
本发明实施例以不透明的底栅极为掩膜，通过背部曝光自动对准源漏极和半导体沟道，制成了自对准的底栅极、底接触结构的金属氧化物 TFT 器件。该方法具有下述效果：
一方面，通过以底栅极为掩膜进行背部曝光，可实现源漏电极与栅极的高精度自对准，源漏电极与栅极的重叠区域可精确控制在 2 μ m 以内，远高于传统掩膜对位的精度，有效的减弱了寄生电容，提高了器件的电路速度，并且使沟道尺寸的控制更加精确，有利于实现沟道尺寸的最小化，提高器件性能；并且，生产流程中的掩膜板对准不再是关键的对准要求，进而降低了制造难度。
另一方面，由于该器件为底栅、底接触结构，不需在半导体层之上再进行刻蚀工艺，因此无需制作刻蚀阻挡层，因此只需一步背部曝光，从而简化了工艺，减少了光刻掩膜的使用，提高了生产效率，并且避免了刻蚀阻挡层对半导体沟道的不良影响；另外，采用底接触结构更易于载流子在源极-半导体沟道-漏极间的传输，改善了 器件的电学特性。
再一方面，当使用灰度掩模板刻蚀源漏电极和半导体沟道时，可减少一步光刻工艺并减少光刻掩膜的使用，降低了成本且提高了生产效率。
另外，与采用 宽度小于曝光机分辨率缝隙的掩膜板进行刻蚀的方法相比，本发明无需使用该高精度且昂贵的掩膜板，沟道尺寸不受光刻设备的严格限制，且该制造工艺易于实现，同时解决了传统的掩膜板对准的其他工艺问题。
基于上述制造方法，本发明实施例进一步提供一种自对准金属氧化物薄膜晶体管器件，其可通过上述制造工艺制成。
参考附图 4 ，该器件是一种底栅极、底接触结构的 TFT 器件，主要包括一基板 11 ，在基板 11 之上依次叠层设置栅极 12 和绝缘层 13 ，在绝缘层 13 的表面并排设置有透明的源极 141 和漏极 142 ，在源极 141 和漏极 142 之上则为金属氧化物半导体层 17 ，金属氧化物半导体层 17 在源极 141 和漏极 142 之间形成了可供载流子传输的半导体沟道 171 ，半导体沟道 171 的两边与源极 141 和漏极 142 的内侧边对准。另外，在基板 11 上设有钝化层 18 ，将基板 11 之上的所有结构密封在内。其中，源极 141 和漏极 142 通过导电材料 19 引出至钝化层 18 之外，与外部电路实现电性连接。
进一步的，金属氧化物半导体层 17 可以覆盖部分源极 141 和漏极 142 ，使源极 141 和漏极 142 的外端露于金属氧化物半导体层 17 之外，并进一步优选为相互对称的露于金属氧化物半导体层 17 之外。而钝化层 18 则可以开设有通向源极 141 和漏极 142 外露部分的过孔 181 ，过孔 181 中填充有透明的导电材料 19 ，将源极 141 和漏极 142 引出至钝化层 18 之外。
进一步的，通过上述的背部曝光工艺，使得该器件的源极 141 和漏极 142 与半导体沟道 171 的重叠区域的宽度可缩小到 2 μ m 以内，远小于传统器件的重叠区域，进而有效的减小了寄生电容，提高了器件性能。
可以理解，该自对准金属氧化物薄膜晶体管器件还可包括其他功能结构，本实施例不再赘述，并且，凡通过上述方法制成的金属氧化物薄膜晶体管器件均在本发明的保护范围内。
实施例二：
图 5 示出了本发明第二实施例提供的 自对准金属氧化物薄膜晶体管像素电路的制造方法流程图，图 6-1~6-10 示出了与该制造方法相对应的结构示意图，为了便于说明，仅示出了与本实施例相关的部分。
如图 5 ，该方法包括下述步骤：
在步骤 S201 中， 选取一基板 21 ，在基板 21 之上制备栅极 221 、栅极引线 222 和存储电容电极 223 ；如图 6-1 。
在此步骤中，基板 21 选择透明材料制作，本实施例中的'透明'是指针对光刻工艺中使用的光波透明的材料，然后使用第一个光刻掩膜制作栅极 221 、栅极引线 222 和存储电容电极 223 。可选的，还可以先在基板 21 之上设置一缓冲层。
在步骤 S202 中， 在栅极 221 、栅极引线 222 和存储电容电极 223 之上依次设置绝缘层 23 、透明电极层 24 及光刻胶 25 ；如图 6-2 、 6-3 、 6-4 。
在此步骤中，首先沉积绝缘层 23 ，如图 6-2 ，该绝缘层 23 可以是 SiO2 膜、 SiNX 膜或 SiO2 与 SiNX 叠层分布的多层膜等透明的膜结构。沉积绝缘层 23 之后，在绝缘层 23 之上沉积透明电极层 24 ，如图 6-3 ，其具体可选 ITO 、 IZO 或 GZO 等透明导电材料。之后，在透明电极层 24 之上涂覆光刻胶 25 ，待后续光刻使用，如图 6-4 。
在步骤 S203 中， 以栅极 221 、栅极引线 222 和存储电容电极 223 为掩膜，自基板 21 的背部曝光，去除与栅极 221 、栅极引线 222 和存储电容电极 223 对位的部分透明电极层 24 ，形成与栅极 221 对准的源极 241 和漏极 242 ；如图 6-4 、 6-5 。
在本实施例中，以非透明的栅极 221 、栅极引线 222 和存储电容电极 223 为掩膜，从基板 21 的背部曝光、显影，被曝光的透明电极层 24 被固化保留，与栅极 221 、栅极引线 222 和存储电容电极 223 相对位的未被曝光的部分连同光刻胶 25 一起被剥离，在栅极 221 、栅极引线 222 和存储电容电极 223 之上的区域形成了沟道 26 ，其中，与栅极 221 对准的沟道 26 两侧的透明电极层 24 形成源、漏电极。
在步骤 S204 中 ，在源极 241 和漏极 242 以及其他保留的透明电极层 24 之上沉积金属氧化物半导体层 27 ；如图 6-6 。
在步骤 S205 中， 刻蚀金属氧化物半导体层 27 及源极 241 和漏极 242 ，使源极 241 和漏极 242 的外端露于刻蚀后的金属氧化物半导体层 27 之外，并且隔离不同薄膜晶体管器件的源极和漏极；如图 6-7 。
作为本实施例优选的实现方式，可采用第二个光刻掩膜-灰度掩模板 30 刻蚀源极 241 、漏极 242 和金属氧化物半导体层 27 。将灰度掩模板 20 相应透过率区域与待刻蚀的源极 241 、漏极 242 和金属氧化物半导体层 27 进行合理对位，自基板 21 正面曝光， 刻蚀掉栅极引线 222 和存储电容电极 223 之上的透明电极层 24 和金属氧化物半导体层 27 ，并对栅极 221 之上的源极 241 、漏极 242 和金属氧化物半导体层 27 进行阶梯式刻蚀，使刻蚀后的源极 241 和漏极 242 的外端露于保留的金属氧化物半导体层 27 之外。
本实施例使用一个灰度掩模板同时实现了金属氧化物半导体层 27 和源漏极的刻蚀，与分别刻蚀金属氧化物半导体层和源漏极的方法相比，节省了一次光刻步骤，也减少了一个光刻掩膜的使用，既节约物料，又简化了工艺，有利于提高生产效率。
在步骤 S206 中， 向基板 21 之上沉积钝化层 28 ，并将源极 241 、漏极 242 和栅极引线 222 引出至钝化层 28 之外。如图 6-8 、 6-9 、 6-10 。
作为本实施例的一种实现方式，可以使用第三个光刻掩膜刻蚀钝化层 28 ，形成通向 栅极引线 222 和源极 241 、漏极 242 露于金属氧化物半导体层 27 之外部分的过孔 281 ，然后向钝化层 28 沉积导电材料 29 ，优选为透明导电材料，如透明金属氧化物，导电材料 29 覆盖钝化层 28 并注入过孔 281 中，与源极 241 、 漏极 242 和栅极引线 222 接触。然后，采用第四个光刻掩膜刻蚀导电材料 29 ，形成导电引线将源极 241 、漏极 242 和栅极引线 222 引出。
经过上述步骤后，自对准金属氧化物 TFT 像素电路得以制成，可以理解，以上仅对该像素电路的主体结构的制造工艺进行了说明，当然，该器件还包括其他常规的功能结构，其可采用常规的方法制作，本发明不再赘述。
本发明实施例以不透明的底栅极、栅极引线和存储电容电极为掩膜，通过背部曝光自动对准源漏极和栅极，制成了自对准的底栅极、底接触结构的金属氧化物 TFT 像素电路。该方法具有同上述实施例相同的效果，本实施例不再赘述。
本发明实施例进一步提供一种金属氧化物 TFT 像素电路，该器件可以通过上述方法制成。
进一步参考图 6-10 ，该器件是一种底栅极、底接触结构的金属氧化物 TFT 像素电路，主要包括一基板 21 ，在基板 21 之上并排设有栅极 221 、栅极引线 222 和存储电容电极 223 ，在栅极 221 和存储电容电极 223 之上设置绝缘层 23 ，在绝缘层 23 的表面与栅极 221 对应的区域并排设置有透明的源极 241 和漏极 242 ，在源极 241 和漏极 242 之上则为金属氧化物半导体层 27 ，金属氧化物半导体层 27 在源极 241 和漏极 242 之间形成了可供载流子传输的沟道，即半导体沟道 271 ，半导体沟道 271 的两边与源极 241 和漏极 242 的内侧边对准。另外，在基板 21 上设有钝化层 28 ，将基板 21 之上的所有结构密封在内。其中，源极 241 、漏极 242 和栅极引线 222 通过导电材料 29 引出至钝化层 28 之外，与外部电路实现电性连接。
进一步的，金属氧化物半导体层 27 可以覆盖部分源极 241 和漏极 242 ，使源极 241 和漏极 242 的外端露于金属氧化物半导体层 27 之外，并进一步优选为相互对称的露于金属氧化物半导体层 27 之外。而钝化层 28 则可以开设有通向栅极引线 222 、源极 241 和漏极 242 外露部分的过孔 281 ，过孔 281 中填充有透明的导电材料 29 ，将源极 241 和漏极 242 引出至钝化层 28 之外。
进一步的，通过上述的背部曝光工艺，使得该器件的源极 241 和漏极 242 与半导体沟道 271 的重叠区域的宽度可缩小到 2 μ m 以内，远小于传统器件的重叠区域，进而有效的减小了寄生电容，提高了器件性能。
可以理解，该自对准金属氧化物薄膜晶体管像素电路还可包括其他功能结构，本实施例不再赘述，并且，凡通过上述方法制成的金属氧化物薄膜晶体管像素电路均在本发明的保护范围内。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (16)

  1. 自对准金属氧化物薄膜晶体管器件的制造方法，其特征在于，包括下述步骤：
    选取一基板，在所述基板之上制备栅极；
    在所述栅极之上依次设置绝缘层、透明电极层及光刻胶；
    以所述栅极为掩膜，自所述基板的背部曝光，去除与所述栅极对位的部分透明电极层，以形成与所述栅极对准的源极和漏极；
    在所述源极和漏极之上沉积金属氧化物半导体层；
    刻蚀所述金属氧化物半导体层及源极和漏极，使源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极；
    向所述基板之上沉积钝化层，并将所述源极和漏极引出至所述钝化层之外。
  2. 如权利要求 1 所述的制造方法，其特征在于，刻蚀所述金属氧化物半导体层及源极和漏极，使源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离属于不同薄膜晶体管器件的源极和漏极的步骤具体为：
    采用一灰度掩模板自所述基板的正面进行一次光刻，使光刻后的金属氧化物半导体层覆盖部分源极和漏极，并使源极和漏极的外端露于金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极。
  3. 如权利要求 1 或 2 所述的制造方法，其特征在于，将所述源极和漏极引出至所述钝化层之外的步骤具体为：
    刻蚀所述钝化层，形成通向所述源极和漏极露于金属氧化物半导体层之外部分的过孔；
    向所述过孔中沉积导电材料，形成导电引线，将所述源极和漏极引出。
  4. 如权利要求 3 所述的制造方法，其特征在于，所述导电材料为透明导电材料。
  5. 自对准金属氧化物薄膜晶体管像素电路的制造方法，其特征在于，包括下述步骤：
    选取一基板，在所述基板之上制备栅极、栅极引线和存储电容电极；
    在所述栅极、栅极引线和存储电容电极之上依次设置绝缘层、透明电极层及光刻胶；
    以所述栅极、栅极引线和存储电容电极为掩膜，自所述基板的背部曝光，去除与所述栅极、栅极引线和存储电容电极对位的部分透明电极层，形成与所述栅极对准的源极和漏极；
    在所述源极和漏极以及其他保留的透明电极层之上沉积金属氧化物半导体层；
    刻蚀所述金属氧化物半导体层及源极和漏极，使所述源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极；
    向所述基板之上沉积钝化层，并将所述源极、漏极和栅极引线引出至所述钝化层之外。
  6. 如权利要求 5 所述的制造方法，其特征在于，刻蚀所述金属氧化物半导体层及源极和漏极，使所述源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极的步骤具体为：
    采用一灰度掩模板自所述基板的正面进行一次光刻，将与所述栅极引线和存储电容电极对应区域的部分透明导电层和金属氧化物半导体层去除，使源极和漏极的外端露于刻蚀后的金属氧化物半导体层之外，并且隔离不同薄膜晶体管器件的源极和漏极。
  7. 如权利要求 5 或 6 所述的制造方法，其特征在于，将所述源极、漏极和栅极引线引出至所述钝化层之外的步骤具体为：
    刻蚀所述钝化层，形成通向所述栅极引线以及通向源极和漏极露于金属氧化物半导体层之外部分的过孔；
    向所述过孔中沉积导电材料，形成导电引线，将所述源极、漏极和栅极引线引出。
  8. 如权利要求 7 所述的制造方法，其特征在于，所述导电材料为透明导电材料。
  9. 自对准金属氧化物薄膜晶体管器件，其特征在于，包括：
    基板；
    栅极和绝缘层，依次叠层设置于所述基板之上；
    源极和漏极，并排设置于所述绝缘层之上，且为透明电极；
    金属氧化物半导体层，设置于所述源极和漏极之上，并在所述源极和漏极之间形成沟道，所述沟道的两边与所述源极和漏极的内侧边对准；
    钝化层，包封于所述基板设有栅极的一面；
    所述源极和漏极通过导电材料引出至所述钝化层之外。
  10. 如权利要求 9 所述的自对准金属氧化物薄膜晶体管器件，其特征在于，所述源极和漏极与所述沟道的重叠区域的宽度均小于 2 μ m 。
  11. 如权利要求 9 或 10 所述的自对准金属氧化物薄膜晶体管器件，其特征在于，所述源极和漏极的外端露于所述金属氧化物半导体层之外；
    所述钝化层具有通向所述源极和漏极露于所述金属氧化物半导体层之外部分的过孔，所述过孔中填充有将所述源极和漏极引出的导电材料。
  12. 如权利要求 11 所述的自对准金属氧化物薄膜晶体管器件，其特征在于，所述导电材料为透明导电材料。
  13. 自对准金属氧化物薄膜晶体管像素电路，其特征在于，包括：
    基板；
    栅极、栅极引线和存储电容电极，并排设置于所述基板之上；
    绝缘层，设置于所述栅极和存储电容电极之上；
    源极和漏极，为透明电极，并排设置于所述绝缘层上与所述栅极对应的区域；
    金属氧化物半导体层，设置于所述源极和漏极之上，并在所述源极和漏极之间形成沟道，所述沟道的两边与所述源极和漏极的内侧边对准；
    钝化层，包封于所述基板设有栅极的一面；
    所述源极、漏极和栅极引线通过导电材料引出至所述钝化层之外。
  14. 如权利要求 13 所述的自对准金属氧化物薄膜晶体管像素电路，其特征在于，所述源极和漏极与所述沟道的重叠区域的宽度均小于 2 μ m 。
  15. 如权利要求 13 或 14 所述的自对准金属氧化物薄膜晶体管像素电路，其特征在于，所述源极和漏极的外端露于所述金属氧化物半导体层之外；
    所述钝化层具有通向所述栅极引线和通向所述源极和漏极露于所述金属氧化物半导体层之外部分的过孔，所述过孔中填充有将所述源极、漏极和栅极引线引出的导电材料。
  16. 如权利要求 15 所述的自对准金属氧化物薄膜晶体管像素电路，其特征在于，所述导电材料为透明导电材料。
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