JP2018133528A - スイッチング素子とその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 210000000746 body region Anatomy 0.000 claims abstract description 101
- 239000004065 semiconductor Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000010410 layer Substances 0.000 claims description 165
- 238000005530 etching Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
【解決手段】 スイッチング素子であって、トレンチの間に幅広部と幅狭部とが交互に配置されており、幅広部上にコンタクトホールを有する。半導体基板が、幅広部から幅狭部まで伸びるとともに幅広部内でコンタクトホール内の電極に接している上部n型領域と、幅広部内でコンタクトホール内の電極に接しているp型のボディコンタクト領域と、幅狭部内でゲート絶縁層に接しているp型のボディ領域と、幅狭部内でゲート絶縁層に接している下部n型領域を有する。
【選択図】図3
Description
12 :半導体基板
20a :幅広部
20b :幅狭部
22 :トレンチ
24 :ゲート絶縁層
26 :ゲート電極
28 :層間絶縁層
28a :コンタクトホール
30 :ソース領域
31 :ボディコンタクト領域
32 :ボディ領域
33 :ドリフト領域
34 :ドレイン領域
36 :底部p型領域
38 :接続p型領域
70 :上部電極
72 :下部電極
Claims (6)
- スイッチング素子であって、
半導体基板と、
前記半導体基板の上面に設けられた第1トレンチと、
前記半導体基板の前記上面に設けられており、前記第1トレンチから間隔を開けて配置されている第2トレンチと、
前記第1トレンチの内面を覆う第1ゲート絶縁層と、
前記第2トレンチの内面を覆う第2ゲート絶縁層と、
前記第1トレンチ内に配置されており、前記第1ゲート絶縁層によって前記半導体基板から絶縁されている第1ゲート電極と、
前記第2トレンチ内に配置されており、前記第2ゲート絶縁層によって前記半導体基板から絶縁されている第2ゲート電極と、
前記第1ゲート電極の上面と前記第2ゲート電極の上面と前記半導体基板の前記上面を覆う層間絶縁層と、
前記層間絶縁層上に配置されている第1電極と、
第2電極、
を有しており、
前記半導体基板の前記上面において、前記第1トレンチと前記第2トレンチの間に、幅広部と、前記幅広部よりも前記第1トレンチと前記第2トレンチの間の間隔が狭い幅狭部とが交互に配置されており、
前記層間絶縁層が、前記幅広部上にコンタクトホールを有し、
前記第1電極が、前記コンタクトホール内で前記半導体基板に接しており、
前記半導体基板が、
前記幅広部から前記幅狭部まで伸びており、前記幅狭部内で前記第1ゲート絶縁層と前記第2ゲート絶縁層に接しており、前記幅広部内で前記コンタクトホール内の前記第1電極に接している上部n型領域と、
前記幅広部内で前記コンタクトホール内の前記第1電極に接しているp型のボディコンタクト領域と、
前記幅狭部内の前記上部n型領域の下側で前記第1ゲート絶縁層と前記第2ゲート絶縁層に接しており、前記ボディコンタクト領域に接続されており、前記ボディコンタクト領域よりもp型不純物濃度が低いp型のボディ領域と、
前記幅狭部内の前記ボディ領域の下側で前記第1ゲート絶縁層と前記第2ゲート絶縁層に接しており、前記第2電極に接している下部n型領域、
を有する、
ことを特徴とするスイッチング素子。 - 前記ボディ領域と前記下部n型領域が、前記幅広部から前記幅狭部まで伸びており、
前記半導体基板が、
前記第1トレンチの底面で前記第1ゲート絶縁層に接している第1底部p型領域と、
前記第2トレンチの底面で前記第2ゲート絶縁層に接している第2底部p型領域と、
前記幅広部内で前記第1トレンチの側面に沿って伸びており、前記ボディ領域と前記第1底部p型領域の間を接続している第1接続p型領域と、
前記幅広部内で前記第2トレンチの側面に沿って伸びており、前記ボディ領域と前記第2底部p型領域の間を接続している第2接続p型領域、
をさらに有する請求項1のスイッチング素子。 - 前記半導体基板がSiC基板であり、
前記第1ゲート絶縁層に接する範囲及び前記第2ゲート絶縁層に接する範囲において、前記上部n型領域と前記下部n型領域の間の前記ボディ領域の厚みが1μm以下であることを特徴とする請求項1または2のスイッチング素子。 - スイッチング素子の製造方法であって、
半導体基板の上面に、第1トレンチと、前記第1トレンチから間隔を開けて配置されている第2トレンチを形成する工程と、
前記第1トレンチと前記第2トレンチの長手方向に沿ってエッチング領域と非エッチング領域とが交互に現れるように前記エッチング領域を設定し、前記エッチング領域内の前記第1トレンチと前記第2トレンチの側面をエッチングすることによって、前記エッチング領域内の前記第1トレンチと前記第2トレンチの幅を拡大する工程であって、前記エッチング領域内の前記第1トレンチと前記第2トレンチの間に、前記非エッチング領域内の前記第1トレンチと前記第2トレンチの間に位置する幅広部よりも前記第1トレンチと前記第2トレンチの間の間隔が狭い幅狭部を形成する工程、
を有しており、
製造される前記スイッチング素子が、
前記第1トレンチの内面を覆う第1ゲート絶縁層と、
前記第2トレンチの内面を覆う第2ゲート絶縁層と、
前記第1トレンチ内に配置されており、前記第1ゲート絶縁層によって前記半導体基板から絶縁されている第1ゲート電極と、
前記第2トレンチ内に配置されており、前記第2ゲート絶縁層によって前記半導体基板から絶縁されている第2ゲート電極と、
前記第1ゲート電極の上面と前記第2ゲート電極の上面と前記半導体基板の上面を覆い、前記幅広部上にコンタクトホールを有する層間絶縁層と、
前記層間絶縁層上に配置されており、前記コンタクトホール内で前記半導体基板に接する第1電極と、
第2電極、
を有しており、
製造される前記スイッチング素子の前記半導体基板が、
前記幅広部から前記幅狭部まで伸びており、前記幅狭部内で前記第1ゲート絶縁層と前記第2ゲート絶縁層に接しており、前記幅広部内で前記コンタクトホール内の前記第1電極に接している上部n型領域と、
前記幅広部内で前記コンタクトホール内の前記第1電極に接しているp型のボディコンタクト領域と、
前記幅狭部内の前記上部n型領域の下側で前記第1ゲート絶縁層と前記第2ゲート絶縁層に接しており、前記ボディコンタクト領域に接続されており、前記ボディコンタクト領域よりもp型不純物濃度が低いp型のボディ領域と、
前記幅狭部内の前記ボディ領域の下側で前記第1ゲート絶縁層と前記第2ゲート絶縁層に接しており、前記第2電極に接している下部n型領域、
を有する、
ことを特徴とする製造方法。 - 前記エッチング領域内の前記第1トレンチと前記第2トレンチの幅を拡大する前記工程よりも前に、前記第1トレンチと前記第2トレンチの側面にp型不純物を注入することによって、前記第1トレンチの側面に沿って伸びている第1接続p型領域と前記第2トレンチの側面に沿って伸びている第2接続p型領域を形成する工程と、
前記第1トレンチと前記第2トレンチの底面にp型不純物を注入することによって、前記第1トレンチの底面に露出する第1底部p型領域と前記第2トレンチの底面に露出する第2底部p型領域を形成する工程、
をさらに有しており、
前記エッチング領域内の前記第1トレンチと前記第2トレンチの幅を拡大する前記工程では、前記エッチング領域内の前記第1接続p型領域と前記第2接続p型領域をエッチングにより除去し、
製造される前記スイッチング素子において、
前記ボディ領域と前記下部n型領域が、前記幅広部から前記幅狭部まで伸びており、
前記第1接続p型領域が、前記幅広部内で前記ボディ領域と前記第1底部p型領域の間を接続しており、
前記第2接続p型領域が、前記幅広部内で前記ボディ領域と前記第2底部p型領域の間を接続している、
ことを特徴とする請求項4の製造方法。 - 前記半導体基板がSiC基板であり、
製造される前記スイッチング素子において、
前記第1ゲート絶縁層に接する範囲及び前記第2ゲート絶縁層に接する範囲において、前記上部n型領域と前記下部n型領域の間の前記ボディ領域の厚みが1μm以下であることを特徴とする請求項4または5の製造方法。
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JP6687504B2 (ja) * | 2016-12-19 | 2020-04-22 | トヨタ自動車株式会社 | スイッチング素子の製造方法 |
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