JP2018010988A - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000002093 peripheral effect Effects 0.000 claims abstract description 171
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000012535 impurity Substances 0.000 claims description 42
- 230000015556 catabolic process Effects 0.000 claims description 20
- 230000005684 electric field Effects 0.000 abstract description 41
- 238000000034 method Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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Abstract
Description
12 :半導体基板
14 :上部電極
15 :コンタクト面
16 :下部電極
18 :絶縁膜
20 :素子領域
22 :外周耐圧領域
30 :カソード領域
32 :ドリフト領域
32a:メインドリフト領域
32b:外周ドリフト領域
34 :メインp型領域
34a:環状領域
34b:ストライプ領域
36 :ガードリング
40 :高濃度領域
42 :低濃度領域
Claims (3)
- 半導体装置であって、
半導体基板と、
前記半導体基板の表面に接している表面電極と、
前記半導体基板の裏面に接している裏面電極、
を有しており、
前記半導体基板が、前記半導体基板の厚み方向に沿って平面視したときに前記表面電極と前記半導体基板との接触面と重複する素子領域と、前記素子領域の周囲の外周耐圧領域を有しており、
前記素子領域が、前記表面電極と前記裏面電極の間に通電することが可能な半導体素子を有しており、
前記外周耐圧領域が、
前記表面に露出しており、前記素子領域を多重に囲むp型の複数のガードリングと、
前記複数のガードリングを互いから分離しているn型の外周ドリフト領域、
を有しており、
前記複数のガードリングが、複数の内周側ガードリングと、前記内周側ガードリングよりも外周側に配置されているとともに前記内周側ガードリングよりも幅が狭い複数の外周側ガードリングを有しており、
前記複数の内周側ガードリング同士の間の間隔が、前記複数の外周側ガードリング同士の間の間隔よりも狭く、
前記内周側ガードリングのそれぞれが、自身のp型不純物濃度のピーク値の10%よりも高いp型不純物濃度を有する第1高濃度領域と、そのピーク値の10%以下のp型不純物濃度を有するとともに前記第1高濃度領域と前記外周ドリフト領域の間に配置されている第1低濃度領域を有しており、
前記外周側ガードリングのそれぞれが、自身のp型不純物濃度のピーク値の10%よりも高いp型不純物濃度を有する第2高濃度領域と、そのピーク値の10%以下のp型不純物濃度を有するとともに前記第2高濃度領域と前記外周ドリフト領域の間に配置されている第2低濃度領域を有しており、
前記第1高濃度領域に対して外周側で隣接する部分の前記第1低濃度領域の前記表面における幅が、前記第2高濃度領域に対して外周側で隣接する部分の前記第2低濃度領域の前記表面における幅よりも広い、
半導体装置。 - 前記素子領域が、
前記表面電極に接しており、互いに間隔を開けてストライプ状に伸びるp型の複数のコンタクトp型領域と、
前記複数のコンタクトp型領域の間の位置で前記表面電極にショットキー接触しており、前記外周ドリフト領域に接しているn型のメインドリフト領域と、
前記裏面電極にオーミック接触しており、前記メインドリフト領域に接しているn型のカソード領域、
を有しており、
前記コンタクトp型領域のそれぞれが、自身のp型不純物濃度のピーク値の10%よりも高いp型不純物濃度を有する第3高濃度領域と、そのピーク値の10%以下のp型不純物濃度を有するとともに前記第3高濃度領域と前記メインドリフト領域の間に配置されている第3低濃度領域を有しており、
前記第3低濃度領域の前記表面における幅が、前記第2高濃度領域に対して外周側で隣接する部分の前記第2低濃度領域の前記表面における幅よりも狭い、
請求項1の半導体装置。 - 請求項1または2の半導体装置の製造方法であって、
半導体ウエハの表面に、内周側開口部と外周側開口部を有するマスクを形成する工程と、
前記内周側開口部内の前記半導体ウエハの前記表面にp型不純物を注入することによって前記内周側ガードリングを形成するとともに、前記外周側開口部内の前記半導体ウエハの前記表面にp型不純物を注入することによって前記外周側ガードリングを形成する工程、
を有しており、
前記内周側開口部の側面の傾斜角度が、前記外周側開口部の側面の傾斜角度よりも大きい製造方法。
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