JP2017538288A5 - - Google Patents

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JP2017538288A5
JP2017538288A5 JP2017526096A JP2017526096A JP2017538288A5 JP 2017538288 A5 JP2017538288 A5 JP 2017538288A5 JP 2017526096 A JP2017526096 A JP 2017526096A JP 2017526096 A JP2017526096 A JP 2017526096A JP 2017538288 A5 JP2017538288 A5 JP 2017538288A5
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single crystal
crystal semiconductor
handle substrate
layer
multilayer structure
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JP2017538288A (ja
JP6726180B2 (ja
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JP2017526096A 2014-11-18 2015-11-16 高抵抗率半導体・オン・インシュレータウエハおよび製造方法 Active JP6726180B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201462081352P 2014-11-18 2014-11-18
US62/081,352 2014-11-18
PCT/US2015/060854 WO2016081356A1 (en) 2014-11-18 2015-11-16 High resistivity semiconductor-on-insulator wafer and a method of manufacturing

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JP2020068195A Division JP7191886B2 (ja) 2014-11-18 2020-04-06 高抵抗率半導体・オン・インシュレータウエハおよび製造方法

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JP2017538288A JP2017538288A (ja) 2017-12-21
JP2017538288A5 true JP2017538288A5 (enExample) 2018-12-06
JP6726180B2 JP6726180B2 (ja) 2020-07-22

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JP2017526096A Active JP6726180B2 (ja) 2014-11-18 2015-11-16 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
JP2020068195A Active JP7191886B2 (ja) 2014-11-18 2020-04-06 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
JP2021208175A Active JP7206366B2 (ja) 2014-11-18 2021-12-22 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
JP2023000068A Active JP7451777B2 (ja) 2014-11-18 2023-01-04 高抵抗率半導体・オン・インシュレータウエハおよび製造方法

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JP2020068195A Active JP7191886B2 (ja) 2014-11-18 2020-04-06 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
JP2021208175A Active JP7206366B2 (ja) 2014-11-18 2021-12-22 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
JP2023000068A Active JP7451777B2 (ja) 2014-11-18 2023-01-04 高抵抗率半導体・オン・インシュレータウエハおよび製造方法

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US (3) US10483152B2 (enExample)
EP (3) EP3221885B1 (enExample)
JP (4) JP6726180B2 (enExample)
WO (1) WO2016081356A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6447439B2 (ja) * 2015-09-28 2019-01-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
WO2017142849A1 (en) * 2016-02-19 2017-08-24 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a buried high resistivity layer
US10825681B2 (en) * 2016-08-13 2020-11-03 Applied Materials, Inc. 3D CTF integration using hybrid charge trap layer of sin and self aligned SiGe nanodot
JP6831911B2 (ja) * 2016-10-26 2021-02-17 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 向上した電荷捕獲効率を有する高抵抗率シリコンオンインシュレータ基板
JP6801105B2 (ja) * 2016-12-05 2020-12-16 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 高抵抗シリコンオンインシュレータ構造及びその製造方法
US10943813B2 (en) 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
CN110943066A (zh) * 2018-09-21 2020-03-31 联华电子股份有限公司 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
FR3091618B1 (fr) * 2019-01-09 2021-09-24 Soitec Silicon On Insulator Procédé de fabrication d’un substrat receveur pour une structure de type semi-conducteur sur isolant pour applications radiofrequences et procédé de fabrication d’une telle structure
FR3098985B1 (fr) * 2019-07-15 2022-04-08 Soitec Silicon On Insulator Procédé de collage hydrophile de substrats
US11296190B2 (en) * 2020-01-15 2022-04-05 Globalfoundries U.S. Inc. Field effect transistors with back gate contact and buried high resistivity layer
US11715886B2 (en) * 2020-05-08 2023-08-01 Mobix Labs, Inc. Low-cost, IPD and laminate based antenna array module
EP4287239A1 (en) * 2022-06-02 2023-12-06 Imec VZW A low loss semiconductor substrate
CN116487242A (zh) * 2022-12-15 2023-07-25 苏州华太电子技术股份有限公司 抑制射频器件欧姆损耗的方法及射频器件

Family Cites Families (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4501060A (en) 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
US4755865A (en) 1986-01-21 1988-07-05 Motorola Inc. Means for stabilizing polycrystalline semiconductor layers
JPH0648686B2 (ja) 1988-03-30 1994-06-22 新日本製鐵株式会社 ゲッタリング能力の優れたシリコンウェーハおよびその製造方法
JPH06105691B2 (ja) 1988-09-29 1994-12-21 株式会社富士電機総合研究所 炭素添加非晶質シリコン薄膜の製造方法
JP2617798B2 (ja) 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
JP3217089B2 (ja) * 1991-08-23 2001-10-09 富士通株式会社 Ｓｏｉウェハおよびその製造方法
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US6043138A (en) 1996-09-16 2000-03-28 Advanced Micro Devices, Inc. Multi-step polysilicon deposition process for boron penetration inhibition
US5783469A (en) 1996-12-10 1998-07-21 Advanced Micro Devices, Inc. Method for making nitrogenated gate structure for improved transistor performance
FR2765393B1 (fr) * 1997-06-25 2001-11-30 France Telecom Procede de gravure d'une couche de si1-xgex polycristallin ou d'un empilement d'une couche de si1-xgex polycristallin et d'une couche de si polycristallin, et son application a la microelectronique
US6068928A (en) 1998-02-25 2000-05-30 Siemens Aktiengesellschaft Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method
US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
JP4313874B2 (ja) 1999-02-02 2009-08-12 キヤノン株式会社 基板の製造方法
US6204205B1 (en) 1999-07-06 2001-03-20 Taiwan Semiconductor Manufacturing Company Using H2anneal to improve the electrical characteristics of gate oxide
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US20020090758A1 (en) 2000-09-19 2002-07-11 Silicon Genesis Corporation Method and resulting device for manufacturing for double gated transistors
JP4463957B2 (ja) 2000-09-20 2010-05-19 信越半導体株式会社 シリコンウエーハの製造方法およびシリコンウエーハ
US20050026432A1 (en) 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US6562127B1 (en) 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7057234B2 (en) 2002-12-06 2006-06-06 Cornell Research Foundation, Inc. Scalable nano-transistor and memory using back-side trapping
CN100483666C (zh) 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 施主晶片以及重复利用晶片的方法和剥离有用层的方法
US6995427B2 (en) 2003-01-29 2006-02-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same
JP4853990B2 (ja) 2003-01-29 2012-01-11 ソイテック 絶縁体上に歪み結晶層を製造する方法、前記方法による半導体構造及び製造された半導体構造
US7005160B2 (en) 2003-04-24 2006-02-28 Asm America, Inc. Methods for depositing polycrystalline films with engineered grain structures
EP1649495A2 (en) * 2003-07-30 2006-04-26 ASM America, Inc. Epitaxial growth of relaxed silicon germanium layers
EP1662549B1 (en) 2003-09-01 2015-07-29 SUMCO Corporation Method for manufacturing bonded wafer
CN1856873A (zh) 2003-09-26 2006-11-01 卢万天主教大学 制造具有降低的欧姆损耗的多层半导体结构的方法
US6992025B2 (en) * 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
US7018882B2 (en) * 2004-03-23 2006-03-28 Sharp Laboratories Of America, Inc. Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon
US7279400B2 (en) * 2004-08-05 2007-10-09 Sharp Laboratories Of America, Inc. Method of fabricating single-layer and multi-layer single crystalline silicon and silicon devices on plastic using sacrificial glass
US7312487B2 (en) 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
DE102004041378B4 (de) 2004-08-26 2010-07-08 Siltronic Ag Halbleiterscheibe mit Schichtstruktur mit geringem Warp und Bow sowie Verfahren zu ihrer Herstellung
GB0424290D0 (en) * 2004-11-02 2004-12-01 Koninkl Philips Electronics Nv Method of growing a strained layer
US7476594B2 (en) 2005-03-30 2009-01-13 Cree, Inc. Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
FR2890489B1 (fr) 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
JP2007214199A (ja) 2006-02-07 2007-08-23 Canon Inc 半導体基板及びその製造方法
FR2897982B1 (fr) 2006-02-27 2008-07-11 Tracit Technologies Sa Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat
US7936043B2 (en) * 2006-03-17 2011-05-03 Sychip Inc. Integrated passive device substrates
FR2902233B1 (fr) 2006-06-09 2008-10-17 Soitec Silicon On Insulator Procede de limitation de diffusion en mode lacunaire dans une heterostructure
FR2911430B1 (fr) 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"
CN101681807B (zh) 2007-06-01 2012-03-14 株式会社半导体能源研究所 半导体器件的制造方法
JP4445524B2 (ja) 2007-06-26 2010-04-07 株式会社東芝 半導体記憶装置の製造方法
JP2009016692A (ja) 2007-07-06 2009-01-22 Toshiba Corp 半導体記憶装置の製造方法と半導体記憶装置
US20090278233A1 (en) 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US7915716B2 (en) 2007-09-27 2011-03-29 Stats Chippac Ltd. Integrated circuit package system with leadframe array
US7879699B2 (en) 2007-09-28 2011-02-01 Infineon Technologies Ag Wafer and a method for manufacturing a wafer
US8128749B2 (en) 2007-10-04 2012-03-06 International Business Machines Corporation Fabrication of SOI with gettering layer
US7868419B1 (en) * 2007-10-18 2011-01-11 Rf Micro Devices, Inc. Linearity improvements of semiconductor substrate based radio frequency devices
JP2009135453A (ja) 2007-10-30 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
US20090236689A1 (en) 2008-03-24 2009-09-24 Freescale Semiconductor, Inc. Integrated passive device and method with low cost substrate
FR2933234B1 (fr) 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
FR2933233B1 (fr) 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
JP2010258083A (ja) 2009-04-22 2010-11-11 Panasonic Corp Ｓｏｉウェーハ、その製造方法および半導体装置の製造方法
WO2011052787A1 (ja) 2009-11-02 2011-05-05 富士電機システムズ株式会社 半導体装置および半導体装置の製造方法
JP5644096B2 (ja) 2009-11-30 2014-12-24 ソニー株式会社 接合基板の製造方法及び固体撮像装置の製造方法
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
US20110174362A1 (en) 2010-01-18 2011-07-21 Applied Materials, Inc. Manufacture of thin film solar cells with high conversion efficiency
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
WO2011118643A1 (ja) 2010-03-26 2011-09-29 テルモ株式会社 留置針組立体
US8859393B2 (en) 2010-06-30 2014-10-14 Sunedison Semiconductor Limited Methods for in-situ passivation of silicon-on-insulator wafers
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
JP5117588B2 (ja) 2010-09-07 2013-01-16 株式会社東芝 窒化物半導体結晶層の製造方法
JP5627649B2 (ja) 2010-09-07 2014-11-19 株式会社東芝 窒化物半導体結晶層の製造方法
CN102465336B (zh) * 2010-11-05 2014-07-09 上海华虹宏力半导体制造有限公司 一种高锗浓度的锗硅外延方法
FR2967812B1 (fr) 2010-11-19 2016-06-10 S O I Tec Silicon On Insulator Tech Dispositif electronique pour applications radiofrequence ou de puissance et procede de fabrication d'un tel dispositif
US9287353B2 (en) 2010-11-30 2016-03-15 Kyocera Corporation Composite substrate and method of manufacturing the same
KR101913322B1 (ko) 2010-12-24 2018-10-30 퀄컴 인코포레이티드 반도체 소자들을 위한 트랩 리치 층
US8536021B2 (en) * 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
US8481405B2 (en) 2010-12-24 2013-07-09 Io Semiconductor, Inc. Trap rich layer with through-silicon-vias in semiconductor devices
US8796116B2 (en) 2011-01-31 2014-08-05 Sunedison Semiconductor Limited Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
US20120235283A1 (en) * 2011-03-16 2012-09-20 Memc Electronic Materials, Inc. Silicon on insulator structures having high resistivity regions in the handle wafer
FR2973159B1 (fr) 2011-03-22 2013-04-19 Soitec Silicon On Insulator Procede de fabrication d'un substrat de base
FR2973158B1 (fr) 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
FR2980916B1 (fr) 2011-10-03 2014-03-28 Soitec Silicon On Insulator Procede de fabrication d'une structure de type silicium sur isolant
US9496255B2 (en) 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US8741739B2 (en) 2012-01-03 2014-06-03 International Business Machines Corporation High resistivity silicon-on-insulator substrate and method of forming
US20130193445A1 (en) 2012-01-26 2013-08-01 International Business Machines Corporation Soi structures including a buried boron nitride dielectric
US8921209B2 (en) 2012-09-12 2014-12-30 International Business Machines Corporation Defect free strained silicon on insulator (SSOI) substrates
US9202711B2 (en) 2013-03-14 2015-12-01 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness
JP2016519049A (ja) 2013-05-24 2016-06-30 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 低酸素シリコンインゴットの製造方法
US8951896B2 (en) 2013-06-28 2015-02-10 International Business Machines Corporation High linearity SOI wafer for low-distortion circuit applications
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
KR102294812B1 (ko) 2014-01-23 2021-08-31 글로벌웨이퍼스 씨오., 엘티디. 고 비저항 soi 웨이퍼 및 그 제조 방법
US10068795B2 (en) 2014-02-07 2018-09-04 Globalwafers Co., Ltd. Methods for preparing layered semiconductor structures
JP6118757B2 (ja) 2014-04-24 2017-04-19 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6179530B2 (ja) 2015-01-23 2017-08-16 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

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