WO2015074480A1 - 边缘光滑的半导体衬底的制备方法 - Google Patents

边缘光滑的半导体衬底的制备方法 Download PDF

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WO2015074480A1
WO2015074480A1 PCT/CN2014/089981 CN2014089981W WO2015074480A1 WO 2015074480 A1 WO2015074480 A1 WO 2015074480A1 CN 2014089981 W CN2014089981 W CN 2014089981W WO 2015074480 A1 WO2015074480 A1 WO 2015074480A1
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substrate
insulating layer
polishing
semiconductor substrate
edge
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PCT/CN2014/089981
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English (en)
French (fr)
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叶斐
陈国兴
陈猛
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上海新傲科技股份有限公司
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Publication of WO2015074480A1 publication Critical patent/WO2015074480A1/zh
Priority to US15/162,146 priority Critical patent/US20160379865A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Definitions

  • the invention relates to a method for preparing a silicon-on-insulator substrate, in particular to a method for preparing a semiconductor substrate with a smooth edge.
  • the existing method of bonding the SOI wafer is to bond the two oxidized silicon wafers as a supporting substrate and a device substrate, respectively, and then reinforced at a temperature higher than 1000 ° C for more than 2 hours, and then the key
  • the combined substrate is chamfered by grinding or the like, and finally the device substrate is thinned to the thickness required for the SOI device by grinding, polishing, etc., to obtain a final bonded SOI wafer.
  • the oxide layer for example, the silicon dioxide layer
  • the oxide layer material debris generated during the grinding is likely to remain on the edge of the substrate, and the residual oxide layer material is detrived. Cannot be removed by normal cleaning process.
  • FIG. 1 is a transmission electron micrograph of a prior art bonded SOI wafer.
  • the oxide layer material is silicon dioxide.
  • silicon dioxide remains in the edge regions. Residual silica may cause the user to increase particle size and wafer fragmentation during processing and production, resulting in a decrease in product yield.
  • the technical problem to be solved by the present invention is to provide a method for preparing a semiconductor substrate having a smooth edge, which can significantly reduce the residue of the insulating layer material debris at the edge of the substrate.
  • the present invention provides a method for fabricating a semiconductor substrate having a smooth edge, comprising the steps of: providing a first substrate and a second substrate; and a first substrate and/or a second substrate. Forming an insulating layer on the surface; bonding the first substrate and the second substrate with the insulating layer as an intermediate layer; chamfering the bonded first substrate and the insulating layer; after chamfering The first substrate and the insulating layer are edge-polished.
  • a step of modifying the pair of first substrate and the second substrate is performed to reduce the first substrate and the second substrate Thickness deviation.
  • a step of annealing the substrate after bonding is performed.
  • the method used for the chamfering treatment is selected from one or more of mechanical grinding and corrosion.
  • the step of thinning the pair of first substrates is selected, and the thinning method is selected from one or more of mechanical grinding, etching, and chemical mechanical polishing.
  • a step of polishing a pair of first substrate surfaces is included.
  • the surface of the first substrate is further fabricated with a device layer.
  • the invention has the advantages that the edge polishing process is performed on the first substrate and the insulating layer after the chamfering step, which significantly reduces the residual of the insulating layer material debris in the edge region of the substrate caused by the chamfering step, and improves the product yield. .
  • Figure 1 is a transmission electron micrograph of a prior art bonded SOI wafer
  • Figure 2 is a schematic view showing the steps of the method of the embodiment of the present invention.
  • 3A to 3G are process flow diagrams of the method according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an edge polishing apparatus according to an embodiment of the present invention.
  • Figure 5 is a transmission electron micrograph of a bonded SOI wafer prepared in accordance with the method of the present invention.
  • Step S21 providing a first substrate and a second substrate
  • Step S22 in the first substrate and/or the second
  • the surface of the substrate is formed with an insulating layer
  • step S23 the first substrate and the second substrate are bonded together with the insulating layer as an intermediate layer
  • step S24 The bonded substrate and the insulating layer are chamfered
  • step S26 the first substrate is thinned
  • step S27 the chamfered first substrate and the insulating layer are edge-polished
  • step S28 Polishing is performed on the surface of the first substrate.
  • a first substrate 310 and a second substrate 320 are provided.
  • An epitaxial device layer 330 may be further formed on the surface of the first substrate 310.
  • the first substrate 310 and the second substrate 320 may be lightly doped or heavily doped Si substrate, and may be p-type or n-type doped substrate, and the dopant may be B, P.
  • the second substrate 320 is used as a supporting substrate for the finally formed semiconductor substrate, and the selection material range is wider, and is not limited to being a semiconductor substrate.
  • the epitaxy may be a homoepitaxial or a heteroepitaxial, and in order to obtain a higher crystal quality, homoepitaxial growth is preferred.
  • a device layer 330 of single crystal silicon is epitaxially grown on the surface of the first substrate of single crystal silicon.
  • the device layer 330 of the single crystal silicon material if it is required to form a thermally oxidized silicon oxide insulating layer on the surface thereof, further consideration is given to the thinning effect of the silicon dioxide process on the device layer 330, at this time, the device Layer 330 The thickness should be slightly larger than the target thickness of the top semiconductor layer on the surface of the insulating layer.
  • a step of modifying the pair of first substrate 310 and the second substrate 320 is performed to reduce The first substrate 310 and the second substrate 320 are deviated in thickness.
  • the modified method is selected from one or a combination of grinding or polishing.
  • an insulating layer 340 is formed on the surface of the first substrate 310 and/or the second substrate 320.
  • FIG. 3B shows a case where the insulating layer 340 is formed on the surface of the second substrate 320.
  • the insulating layer 340 may be formed on the surface of the first substrate 310, or the second substrate 320 may be formed.
  • An insulating layer 340 is formed with both surfaces of the first substrate 310.
  • the material of the insulating layer 340 is preferably silicon dioxide, silicon nitride or silicon oxynitride, and the formation process may be a method of chemical vapor deposition or thermal oxidation. Particularly for a single crystal silicon substrate, it is preferred to form a silicon dioxide insulating layer by a method of thermal oxidation.
  • the first substrate 310 and the second substrate 320 are bonded together with the insulating layer 340 as an intermediate layer.
  • the bonding may be a common hydrophilic bonding or a hydrophobic bonding, or may be a plasma-assisted hydrophilic bonding, preferably a hydrophilic bonding and a plasma-assisted hydrophilic bonding.
  • the first substrate 310 and the second substrate 320 are bonded together with the insulating layer 340 and the device layer 330 as intermediate layers.
  • the bonded substrate is annealed.
  • the temperature of the annealing step only needs to be reinforced to meet the strength requirements of the subsequent grinding process.
  • the bonded first substrate 310 and insulating layer 340 are chamfered to form a chamfer 350.
  • the chamfers 350 are exaggeratedly shown in the drawings.
  • a chamfer 350 is formed at the first substrate 310 and the insulating layer 340 by mechanical grinding or etching.
  • the debris 351 is schematically shown in the drawing. The presence of debris 351 may result in increased particle size and wafer fragmentation during processing of the chip.
  • the first substrate 310 is thinned with reference to step S26.
  • the step of thinning the first substrate 310 may be a method of first grinding and then polishing. The grinding is performed by first rough grinding the first substrate 310 and then performing fine grinding on the first substrate 310. The rough grinding rapidly thins the first substrate 310, which reduces the damage caused by the polishing to the first substrate 310.
  • the first substrate 310 is directly thinned to the device layer 330, and the top semiconductor layer is entirely composed of the device layer 330. If the surface of the first substrate 310 is epitaxial The thickness of the device layer 330 is greater than the target thickness. This step can further reduce the device layer 330 to the target thickness.
  • the advantage is that a small amount of impurities diffused from the first substrate 310 into the device layer 330 can be removed, and the device layer can be improved.
  • the thinning is stopped at a certain distance from the device layer 330. Subsequent thinning to device layer 330 by other thinning processes.
  • edge polishing is performed on the chamfered first substrate 310 and the insulating layer 340.
  • the edge polishing process removes all or part of the debris 351 formed by grinding or etching.
  • the edge-polished area is shown in the dashed line area in Fig. 3E, and only the polishing area on one side is schematically shown in the drawing. In fact, the polishing area should be around the bonded substrate one week.
  • the device used for the edge polishing is an edge polishing device.
  • FIG. 4 is a schematic view showing the structure of an edge polishing apparatus for edge polishing according to the present invention.
  • the edge polishing apparatus is configured to include a stage 410, a polishing head 420, and a polishing pad 430.
  • the stage 410 carries and fixes a sample 440 to be polished, and the polishing pad 430 is coupled to the polishing head 420 for polishing the sample 440 to be polished.
  • the polishing sample 440 is to be polished
  • the stage 410 carries a low speed rotation of the sample 440 to be polished, and the polishing head 420 rotates at a high speed and slowly descends until the polishing pad 430 contacts the sample 440 to be polished.
  • the stage 410 fixes the sample to be polished 440 by vacuum adsorption.
  • the sample to be polished may be fixed by mechanical fixing or the like to prevent the sample 440 to be polished from moving during edge polishing.
  • the surface of the first substrate 310 is polished to make the surface of the first substrate 310 flat and smooth.
  • the polishing may be double-sided polishing or single-sided polishing, or may be double-sided + single-sided polishing, and here is preferably double-sided + single-sided polishing.
  • Figure 5 is a transmission electron micrograph of a bonded SOI wafer prepared in accordance with the method of the present invention.
  • the dotted line area in Fig. 5 is smoother than the dotted line area in Fig. 1, and the edge of the semiconductor substrate prepared by the method of the present invention is smooth, which reduces the residue of the insulating layer material debris at the edge of the substrate, and significantly improves the product yield.

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Abstract

一种边缘光滑的半导体衬底的制备方法，包括如下步骤：提供一第一衬底及第二衬底；在第一衬底和/或第二衬底的表面形成绝缘层；以绝缘层为中间层，将第一衬底与第二衬底键合在一起；对键合后的第一衬底及绝缘层实施倒角处理；对倒角处理后的第一衬底及绝缘层实施边缘抛光。优点在于，对实施倒角步骤后的第一衬底及绝缘层进行边缘抛光处理，显著降低倒角步骤带来的绝缘层材料碎屑在边缘区域的残留，提高产品良率。

Description

边缘光滑的半导体衬底的制备方法 技术领域
本发明涉及绝缘体上硅衬底的制备方法，尤其涉及一种边缘光滑的半导体衬底的制备方法。
背景技术
现有的键合SOI晶片的做法是：将两片氧化后的硅片分别作为支撑衬底和器件衬底键合在一起，随后在高于1000℃的温度下加固2小时以上，然后对键合后的衬底采用研磨等方式制造倒角，最后采用研磨、抛光等方式将器件衬底减薄到SOI器件所需要的厚度，即得到最终的键合SOI晶片。在制造倒角时，所述氧化层，例如，二氧化硅层，也被研磨制造出倒角，则研磨时产生的氧化层材料碎屑容易残留在衬底边缘，残留的氧化层材料碎屑无法通过正常清洗工艺去除。附图1所示是现有技术中键合SOI晶片的透射电镜图，氧化层材料为二氧化硅，从附图1中虚线区域可以看出，在边缘区域残留有二氧化硅。残留的二氧化硅可能会导致用户在加工生产过程中发生颗粒增加、晶圆碎片的情况，造成产品良率下降。
发明内容
本发明所要解决的技术问题是，提供一种边缘光滑的半导体衬底的制备方法，该方法能够显著降低绝缘层材料碎屑在衬底边缘的残留。
为了解决上述问题，本发明提供了一种边缘光滑的半导体衬底的制备方法，包括如下步骤：提供一第一衬底及第二衬底，；在第一衬底和/或第二衬底的表面形成绝缘层；以绝缘层为中间层，将第一衬底与第二衬底键合在一起；对键合后的第一衬底及绝缘层实施倒角处理；对倒角处理后的第一衬底及绝缘层实施边缘抛光。
进一步，在第一衬底和/或第二衬底的表面形成绝缘层之前，包括一对第一衬底及第二衬底进行修正的步骤，以减小第一衬底及第二衬底厚度偏差。
进一步，键合步骤后，包括一对键合后衬底实施退火的步骤。
进一步，所述倒角处理采用的方法选自于机械研磨、腐蚀中的一种或多种。
进一步，倒角步骤后，包括一对第一衬底减薄的步骤，所述减薄方法选自于机械研磨、腐蚀、化学机械研磨中的一种或多种。
进一步，边缘抛光步骤后，包括一对第一衬底表面抛光的步骤。
进一步，所述第一衬底的表面进一步制作有器件层。
本发明的优点在于，对实施倒角步骤后的第一衬底及绝缘层进行边缘抛光处理，显著降低倒角步骤带来的绝缘层材料碎屑在衬底边缘区域的残留，提高产品良率。
附图说明
附图1所示是现有技术中键合SOI晶片的透射电镜图；
附图2所示是本发明具体实施方式所述方法的实施步骤示意图；
附图3A～附图3G所示是本发明具体实施方式所述方法的工艺流程图；
附图4所示是本发明具体实施方式所述边缘抛光装置的结构示意图；
附图5所示是根据本发明方法制备的键合SOI晶片的透射电镜图。
具体实施方式
下面结合附图对本发明提供的边缘光滑的半导体衬底的制备方法的具体实施方式做详细说明。
图2所示是本发明具体实施方式所述方法的实施步骤示意图，包括如下步骤：步骤S21，提供一第一衬底及第二衬底；步骤S22，在第一衬底和/或第二衬底的表面形成绝缘层；步骤S23，以绝缘层为中间层，将第一衬底与第二衬底键合在一起；步骤S24，对键合后的衬底实施退火；步骤S25，对键合后的第一衬底及绝缘层实施倒角处理；步骤S26，对第一衬底减薄；步骤S27，对倒角处理后的第一衬底及绝缘层实施边缘抛光；步骤S28，对第一衬底表面实施抛光。
附图3A所示，参考步骤S21，提供一第一衬底310及第二衬底320。在所述第一衬底310的表面还可以进一步制作有外延的器件层330。所述第一衬底310及第二衬底320可以是轻掺杂也可以是重掺杂Si衬底，可以是p型也可以是n型掺杂衬底，掺杂剂可以是B、P、As也可以是别的杂质元素。尤其是第二衬底320作为最终形成的半导体衬底的支撑衬底使用，其选择材料范围更为广泛，甚至于不限于是半导体衬底。
所述外延可以是同质外延也可以是异质外延，为了获得更高的晶体质量，优选为同质外延。例如在单晶硅的第一衬底表面外延单晶硅的器件层330。进一步，对于单晶硅材料的器件层330而言，如果需要在其表面形成热氧化的二氧化硅绝缘层，还要进一步考虑二氧化硅工艺对器件层330的减薄效应，此时，器件层330 的厚度应当略大于绝缘层表面的顶层半导体层的目标厚度。
进一步，作为可选步骤，在第二衬底320和/或第一衬底310的表面形成绝缘层之前，包括一对第一衬底310及第二衬底320进行修正的步骤，以减小第一衬底310及第二衬底320厚度偏差。所述修正的方法选自于研磨或抛光中的一种或两者结合。
附图3B所示，参考步骤S22，在第一衬底310和/或第二衬底320表面形成绝缘层340。附图3B所示是在第二衬底320表面形成绝缘层340的情况，在其他的实施方式中，也可以是在第一衬底310的表面形成绝缘层340，或者在第二衬底320和第一衬底310的表面均形成绝缘层340。绝缘层340的材料优选为二氧化硅、氮化硅或者氮氧化硅，形成工艺可以采用化学气相淀积或者热氧化的方法。尤其对于单晶硅衬底，优选为采用热氧化的方法形成二氧化硅绝缘层。
附图3C所示，参考步骤S23，以绝缘层340为中间层，将第一衬底310与第二衬底320键合在一起。键合可以是普通的亲水键合也可以是疏水键合，也可以是等离子辅助亲水键合，优选为亲水键合和等离子辅助亲水键合。当所述第一衬底310表面具有器件层330时，以绝缘层340及器件层330为中间层，将将第一衬底310与第二衬底320键合在一起。
参考步骤S24，对键合后的衬底实施退火。该退火步骤的温度只需要对键合界面进行加固使其满足后续研磨等工艺的强度要求即可。
附图3D所示，参考步骤S25，对键合后的第一衬底310及绝缘层340实施倒角处理，形成倒角350。为了清楚解释本发明内容，附图中将倒角350夸大地表示出来。采用机械研磨或腐蚀的方式在第一衬底310及绝缘层340处形成倒角350。在形成倒角350时，研磨或腐蚀形成的碎屑有一部分会粘贴在磨削后的表面，附图中示意性地表示出碎屑351。碎屑351的存在可能会导致在加工芯片的过程中产品产生颗粒增加、晶圆碎片的情况。
附图3E所示，参考步骤S26，对第一衬底310减薄。对第一衬底310减薄的步骤可以采用先研磨再抛光的方法。所述研磨的方法为首先对第一衬底310进行粗磨，然后再对第一衬底310进行精磨。所述粗磨快速减薄第一衬底310，所述精磨减小研磨对第一衬底310造成的损伤。优选地，直接减薄第一衬底310至器件层330，则顶层半导体层完全由器件层330构成。如果在第一衬底310表面外延形 成的器件层330的厚度大于目标厚度，此步骤还可以进一步减薄器件层330至目标厚度，其优点在于可以去除少数从第一衬底310扩散至器件层330中的杂质，并提高器件层330表面的平整度。在本发明其他实施方式中，在距离器件层330一定位置处停止减薄。后续通过其他减薄工艺减薄至器件层330。
附图3F所示，参考步骤S27，对倒角处理后的第一衬底310及绝缘层340实施边缘抛光。边缘抛光工艺全部或部分去除研磨或腐蚀形成的碎屑351。所述边缘抛光区域参见附图3E中的虚线区域，附图中仅示意性地表示出一侧的抛光区域，事实上，抛光区域应该是围绕键合后的衬底一周。所述边缘抛光使用的装置为边缘抛光装置。
附图4所示为本发明用于边缘抛光的边缘抛光装置结构示意图。参见图4所示，所述边缘抛光装置结构为：包括载台410、抛光头420、抛光垫430。所述载台410承载并固定待抛光样品440，所述抛光垫430与所述抛光头420连接，用以抛光待抛光样品440。当对待抛光样品440进行抛光时，所述载台410承载待抛光样品440低速旋转，所述抛光头420高速旋转并缓慢下降直到抛光垫430接触待抛光样品440。在本具体实施方式中，所述载台410采用真空吸附的方式固定所述待抛光样品440。在其他具体实施方式中，可以采用机械固定等方式固定所述待抛光样品，以防止在进行边缘抛光时待抛光样品440移动。
附图3G所示，参考步骤S28，对第一衬底310表面实施抛光，以使得第一衬底310表面平坦光滑。所述抛光可以是双面抛光也可以是单面抛光，也可以是双面+单面抛光，这里优选为为双面+单面抛光。
附图5所示是根据本发明方法制备的键合SOI晶片的透射电镜图。附图5中虚线区域与附图1中虚线区域相比，本发明方法制备的半导体衬底边缘光滑，减少了绝缘层材料碎屑在衬底边缘的残留，显著提高产品良率。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

  1. 一种边缘光滑的半导体衬底的制备方法，其特征在于，包括如下步骤：
    提供一第一衬底及第二衬底；
    在第一衬底和/或第二衬底的表面形成绝缘层；
    以绝缘层为中间层，将第一衬底与第二衬底键合在一起；
    对键合后的第一衬底及绝缘层实施倒角处理；
    对倒角处理后的第一衬底及绝缘层实施边缘抛光。
  2. 根据权利要求1所述的边缘光滑的半导体衬底的制备方法，其特征在于，
    在第一衬底和/或第二衬底的表面形成绝缘层之前，包括一对第一衬底及第二衬底进行修正的步骤，以减小第一衬底及第二衬底厚度偏差。
  3. 根据权利要求1所述的边缘光滑的半导体衬底的制备方法，其特征在于，
    键合步骤后，进一步包括一对键合后衬底实施退火的步骤。
  4. 根据权利要求1所述的边缘光滑的半导体衬底的制备方法，其特征在于，
    所述倒角处理采用的方法选自于机械研磨、腐蚀中的一种或多种。
  5. 根据权利要求1所述的边缘光滑的半导体衬底的制备方法，其特征在于，
    倒角步骤后，进一步包括一对第一衬底减薄的步骤，所述减薄方法选自于机械研磨、腐蚀、化学机械研磨中的一种或多种。
  6. 根据权利要求1所述的边缘光滑的半导体衬底的制备方法，其特征在于，
    边缘抛光步骤后，进一步包括一对第一衬底表面抛光的步骤。
  7. 根据权利要求1所述的边缘光滑的半导体衬底的制备方法，其特征在于，
    所述第一衬底的表面进一步制作有器件层。
PCT/CN2014/089981 2013-11-22 2014-10-31 边缘光滑的半导体衬底的制备方法 WO2015074480A1 (zh)

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