WO2015074478A1 - 低翘曲度的半导体衬底的制备方法 - Google Patents

低翘曲度的半导体衬底的制备方法 Download PDF

Info

Publication number
WO2015074478A1
WO2015074478A1 PCT/CN2014/089977 CN2014089977W WO2015074478A1 WO 2015074478 A1 WO2015074478 A1 WO 2015074478A1 CN 2014089977 W CN2014089977 W CN 2014089977W WO 2015074478 A1 WO2015074478 A1 WO 2015074478A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
insulating layer
semiconductor substrate
warpage
Prior art date
Application number
PCT/CN2014/089977
Other languages
English (en)
French (fr)
Inventor
叶斐
陈猛
陈国兴
Original Assignee
上海新傲科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海新傲科技股份有限公司 filed Critical 上海新傲科技股份有限公司
Publication of WO2015074478A1 publication Critical patent/WO2015074478A1/zh
Priority to US15/161,555 priority Critical patent/US20170018454A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes

Definitions

  • the invention relates to a method for preparing a silicon-on-insulator substrate, in particular to a method for preparing a semiconductor substrate with low warpage.
  • the oxide layer on the surface of the device layer needs to be etched away.
  • the simultaneous removal of the backside insulating layer of the support substrate during the etching of the oxide layer results in a large warpage of the silicon wafer.
  • the first surface of the support substrate 100 has a device layer 110 and an oxide layer 120 over the device layer 110.
  • the second surface of the support substrate 100 opposite the first surface has an insulating layer 130 when corrosion is applied.
  • the oxide layer 120 is removed, the insulating layer 130 is simultaneously corroded and removed due to sputtering or flow of the etching solution, resulting in a large warpage of the semiconductor substrate.
  • FIG. 1B is a transmission electron micrograph of a prior art bonded SOI wafer. As can be seen from FIG. 1B, after the oxide layer 120 is removed, the tilt angle of the semiconductor substrate is large, indicating the warpage of the semiconductor substrate. Larger. Large warpage may cause component failure, chipping, etc. of the semiconductor substrate during processing, resulting in loss of yield. Therefore, users need a semiconductor substrate with low warpage.
  • the technical problem to be solved by the present invention is to provide a method for preparing a semiconductor substrate having low warpage. This method can reduce the warpage of the wafer.
  • the present invention provides a method for fabricating a low warpage semiconductor substrate, comprising the steps of: providing a first substrate and a second substrate, the first substrate having an opposite first surface And a second surface, the first surface is provided with a first insulating layer, the second surface is provided with a second insulating layer, the second substrate comprises a supporting layer, an oxide layer on the surface of the supporting layer, and an oxide layer a device layer of the surface; bonding the first substrate and the second substrate with the device layer and the first insulating layer as an intermediate layer; forming a protective layer on the surface of the second insulating layer, the second The insulating layer and the protective layer function to adjust the warpage of the semiconductor substrate.
  • the protective layer is a blue film
  • the materials of the first insulating layer and the second insulating layer are each independently selected from any one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the step of performing annealing on a pair of bonded substrates is further included.
  • an etching step is further included to remove the oxide layer.
  • the method of thinning is selected from one or two of mechanical grinding and chemical mechanical polishing.
  • the step of chamfering the pair of second substrate and the first insulating layer is further included.
  • An advantage of the present invention is that a protective layer is adhered to the surface of the second insulating layer of the substrate, and the protective layer can prevent the second insulating layer from being corroded, thereby effectively reducing the warpage of the wafer.
  • 1A is a schematic view showing a process of preparing an SOI wafer for etching and removing an oxide layer in the prior art
  • 1B is a transmission electron micrograph of a prior art bonded SOI wafer
  • Figure 2 is a schematic view showing the steps of the method of the embodiment of the present invention.
  • 3A to 3E are schematic views showing an implementation process of a specific embodiment of the present invention.
  • Figure 4 is a transmission electron micrograph of a semiconductor substrate prepared by the method of the present invention.
  • Figure 5 shows a comparison of the warpage of a semiconductor substrate prepared by the method of the present invention and a semiconductor substrate prepared by a conventional method in the prior art.
  • Step S21 providing a first substrate and a second substrate, the first substrate having a first surface and a first surface a second surface, the first surface is provided with a first insulating layer, the second surface is provided with a second insulating layer, the second substrate comprises a supporting layer, an oxide layer on the surface of the supporting layer, and an oxide layer surface a device layer; in step S22, the first substrate and the second substrate are bonded together with the device layer and the first insulating layer as an intermediate layer; in step S23, the bonded substrate is annealed; step S24, The second substrate is thinned to remove the support layer; in step S25, a protective layer is formed on the second insulating layer, and the second insulating layer and the protective layer function to adjust the semiconductor substrate The degree of warpage; in step S26, an etching step is performed on the substrate to remove the oxide layer.
  • a first substrate 310 having a first surface and a second surface, and a second substrate 320 having a first surface and a second surface a must The edge layer 330 is provided with a second insulating layer 380 on the second surface, and the second substrate 320 includes a support layer 340, an oxide layer 350 on the surface of the support layer 340, and a device layer 360 on the surface of the oxide layer 350.
  • the first substrate 310 and the second substrate 320 may be lightly doped or heavily doped Si substrate, and may be p-type or n-type doped substrate, and the dopant may be B, P. As can also be another impurity element.
  • the second substrate 320 is used as a supporting substrate for the finally formed semiconductor substrate, and the selection material range is wider, and is not limited to being a semiconductor substrate.
  • the materials of the first insulating layer 330 and the second insulating layer 380 are each independently selected from any one of silicon dioxide, silicon nitride or silicon oxynitride, and the forming process may be chemical vapor deposition or thermal oxidation. method. Particularly for a single crystal silicon substrate, it is preferred to form a silicon dioxide insulating layer by a method of thermal oxidation.
  • the device layer 360 can be formed using an epitaxial method.
  • the epitaxy may be a homoepitaxial or a heteroepitaxial, and in order to obtain a higher crystal quality, homoepitaxial growth is preferred.
  • a device layer 330 of single crystal silicon is epitaxially grown on the surface of the first substrate of single crystal silicon.
  • the oxide layer 350 is formed by ion implantation and exists as a buried oxide layer in the second substrate 320.
  • the step of forming an insulating layer on the surface of the device layer 360 may be further included.
  • the insulating layer on the surface of the device layer 360 and the first insulating layer 330 are used as an intermediate layer. The first substrate and the second substrate are bonded together.
  • the first substrate 310 and the second substrate 320 are bonded together with the device layer 360 and the first insulating layer 330 as intermediate layers.
  • the bonding may be a common hydrophilic bonding or a hydrophobic bonding, or may be a plasma-assisted hydrophilic bonding, preferably a hydrophilic bonding and a plasma-assisted hydrophilic bonding.
  • the bonded substrate is annealed.
  • the annealing forms a covalent bond at the bonding interface, and the bonding force is enhanced.
  • the annealing temperature is greater than 900 ° C
  • the annealing time is greater than 2 hours
  • the annealing atmosphere is a mixed gas of wet oxygen, dry oxygen, nitrogen or oxygen and argon.
  • the second substrate 320 is thinned to remove the support layer 340.
  • the step of thinning the first substrate 310 may be a method of first grinding and then polishing. The grinding is performed by first rough grinding the first substrate 310 and then performing fine grinding on the first substrate 310. The rough grinding rapidly thins the first substrate 310, which reduces the damage caused by the polishing to the first substrate 310.
  • the polishing may be performed by chemical mechanical polishing on one or both sides, preferably on one side Polishing to prevent removal of the second insulating layer 380.
  • the bonded substrate may be chamfered before the step S24 is performed.
  • a protective layer 370 is formed on the second insulating layer 380 to prevent the second insulating layer 380 from being corroded.
  • the protective layer 370 is not corroded by the etching liquid, and the etching liquid is not corroded to the insulating layer 330, so that a semiconductor substrate having a low warpage can be obtained.
  • the protective layer 370 may be attached, but not limited to, by the following method:
  • the film is tightly attached to the second insulating layer 380 of the substrate by using a slider during the tearing process.
  • step S26 an etching step is performed on the substrate to remove the oxide layer 350.
  • the oxide layer 350 is removed by etching to expose the device layer 360.
  • the etching solution used for the etching is preferably HF.
  • Figure 4 is a transmission electron micrograph of a semiconductor substrate prepared in accordance with the method of the present invention. As can be seen from FIG. 4, after the oxide layer 350 is removed, the tilt angle of the semiconductor substrate becomes smaller as compared with the prior art, indicating that the warpage of the semiconductor substrate becomes small.
  • Figure 5 is a comparison of the warpage of a semiconductor substrate prepared by the method of the present invention and a semiconductor substrate prepared by a conventional method in the prior art.
  • the layer 380 has a protective layer 370 on its surface such that the second insulating layer 380 is not corroded by the etching liquid, and therefore, the warpage of the semiconductor substrate prepared by the method of the present invention is higher than that of the semiconductor substrate prepared by the conventional method in the prior art. Low warpage.

Abstract

提供一种低翘曲度的半导体衬底的制备方法，其特征在于，包括如下步骤：提供第一衬底（310）及第二衬底（320），第一衬底具有相对的第一表面和第二表面，第一表面上设置有第一绝缘层（330），第二表面上设置有第二绝缘层（380），第二衬底包括支撑层（340）、支撑层表面的氧化层（350）以及氧化层表面的器件层（360）；以器件层及第一绝缘层为中间层，将第一衬底与第二衬底键合在一起；在第二绝缘层表面粘贴形成一保护层（370），第二绝缘层和保护层的作用在于调整所述半导体衬底的翘曲度。在衬底的第二绝缘层表面粘贴保护层能够防止第二绝缘层被腐蚀，从而能有效地降低晶片的翘曲度。

Description

低翘曲度的半导体衬底的制备方法 技术领域
本发明涉及绝缘体上硅衬底的制备方法，尤其涉及一种低翘曲度的半导体衬底的制备方法。
背景技术
在SOI晶片制作过程中，器件层表面的氧化层需要被腐蚀掉。在腐蚀氧化层的过程中会将支撑衬底背面绝缘层同时去除导致硅片翘曲度较大。如图1A所示，支撑衬底100的第一表面具有器件层110及位于器件层110上方的氧化层120，支撑衬底100与第一表面相对的第二表面具有绝缘层130，当采用腐蚀的方法去除氧化层120时，由于腐蚀液溅射或流动，则会使得绝缘层130会同时被腐蚀去除，导致半导体衬底翘曲度较大。附图1B所示是现有技术中键合SOI晶片的透射电镜图，从附图1B中可以看出，去除氧化层120后，半导体衬底倾斜角度较大，则说明半导体衬底翘曲度较大。翘曲度较大可能会导致半导体衬底在加工过程中元件失效、产生碎片等情况发生，造成良率损失。因此，用户需要一种低翘曲度的半导体衬底。
发明内容
本发明所要解决的技术问题是，提供一种低翘曲度的半导体衬底的制备方法。该方法能够降低晶片的翘曲度。
为了解决上述问题，本发明提供了一种低翘曲度的半导体衬底的制备方法，包括如下步骤：提供第一衬底及第二衬底，所述第一衬底具有相对的第一表面和第二表面，所述第一表面上设置有第一绝缘层，所述第二表面上设置有第二绝缘层，所述第二衬底包括支撑层、支撑层表面的氧化层以及氧化层表面的器件层；以器件层及第一绝缘层为中间层，将第一衬底与第二衬底键合在一起；在所述第二绝缘层表面粘贴形成一保护层，所述第二绝缘层和保护层的作用在于调整所述半导体衬底的翘曲度。
进一步，所述保护层为蓝膜，所述第一绝缘层和第二绝缘层的材料各自独立地选自于氧化硅、氮化硅、以及氮氧化硅的任意一种。
所述键合步骤后，进一步包括一对键合后的衬底实施退火的步骤。
所述键合步骤后，进一步包括一对第二衬底进行减薄的步骤，以去除所述 支撑层。
所述减薄步骤之后，进一步包括一腐蚀步骤，以去除所述氧化层。
所述减薄采用的方法选自于机械研磨、化学机械抛光中的一种或两种。
所述键合步骤后，进一步包括一对第二衬底及第一绝缘层实施倒角的步骤。
本发明的优点在于，在衬底的第二绝缘层表面粘贴一保护层，所述保护层能够防止第二绝缘层被腐蚀，从而能有效地降低晶片的翘曲度。
附图说明
附图1A所示是现有技术中制备SOI晶片腐蚀去除氧化层的工艺示意图；
附图1B所示是现有技术中键合SOI晶片的透射电镜图；
附图2所示是本发明具体实施方式所述方法的实施步骤示意图；
附图3A至附图3E所示是本发明具体实施方式的实施工艺示意图；
附图4所示是本发明方法制备的半导体衬底的透射电镜图；
附图5所示为本发明方法制备的半导体衬底与现有技术中的常规方法制备的半导体衬底的翘曲度的对比。
具体实施方式
下面结合附图对本发明提供的低翘曲度的半导体衬底的制备方法的具体实施方式做详细说明。
图2所示是本发明具体实施方式所述方法的实施步骤示意图，包括如下步骤：步骤S21，提供第一衬底及第二衬底，所述第一衬底具有相对的第一表面和第二表面，所述第一表面上设置有第一绝缘层，所述第二表面上设置有第二绝缘层，所述第二衬底包括支撑层、支撑层表面的氧化层以及氧化层表面的器件层；步骤S22，以器件层及第一绝缘层为中间层，将第一衬底与第二衬底键合在一起；步骤S23，对键合后的衬底实施退火；步骤S24，对第二衬底进行减薄，以去除所述支撑层；步骤S25，在所述第二绝缘层上粘贴形成一保护层，所述第二绝缘层和保护层的作用在于调整所述半导体衬底的翘曲度；步骤S26，对衬底实施腐蚀步骤，以去除所述氧化层。
附图3A所示，参考步骤S21，提供第一衬底310及第二衬底320，所述第一衬底310具有相对的第一表面和第二表面，所述第一表面上设置有第一绝 缘层330，所述第二表面上设置有第二绝缘层380，所述第二衬底320包括支撑层340、支撑层340表面的氧化层350以及氧化层350表面的器件层360。
所述第一衬底310及第二衬底320可以是轻掺杂也可以是重掺杂Si衬底，可以是p型也可以是n型掺杂衬底，掺杂剂可以是B、P、As也可以是别的杂质元素。尤其是第二衬底320作为最终形成的半导体衬底的支撑衬底使用，其选择材料范围更为广泛，甚至于不限于是半导体衬底。
所述第一绝缘层330及第二绝缘层380的材料各自独立地选自于二氧化硅、氮化硅或者氮氧化硅中的任意一种，形成工艺可以采用化学气相淀积或者热氧化的方法。尤其对于单晶硅衬底，优选为采用热氧化的方法形成二氧化硅绝缘层。
所述器件层360可以采用外延的方法形成。所述外延可以是同质外延也可以是异质外延，为了获得更高的晶体质量，优选为同质外延。例如在单晶硅的第一衬底表面外延单晶硅的器件层330。所述氧化层350采用离子注入的方法形成，在第二衬底320中作为埋层氧化层存在。
进一步，作为可选步骤，在此步骤之后，还可以包括在器件层360表面形成绝缘层的步骤，在键合步骤中，以器件层360表面的绝缘层及第一绝缘层330为中间层，将第一衬底与第二衬底键合在一起。
附图3B所示，参考步骤S22，以器件层360及第一绝缘层330为中间层，将第一衬底310与第二衬底320键合在一起。键合可以是普通的亲水键合也可以是疏水键合，也可以是等离子辅助亲水键合，优选为亲水键合和等离子辅助亲水键合。
参考步骤S23，对键合后的衬底实施退火。退火使得键合界面处形成共价键，增强键合力，退火温度大于900℃，退火时间大于2小时，退火气氛为湿氧、干氧、氮气或者氧氩混合气体。
附图3C所示，参考步骤S24，对第二衬底320进行减薄，以去除所述支撑层340。对第一衬底310减薄的步骤可以采用先研磨再抛光的方法。所述研磨的方法为首先对第一衬底310进行粗磨，然后再对第一衬底310进行精磨。所述粗磨快速减薄第一衬底310，所述精磨减小研磨对第一衬底310造成的损伤。所述抛光可以采用化学机械抛光的方法进行单面或双面抛光，优选为单面 抛光，以防止将第二绝缘层380去除。
进一步，如果需要倒角，则可以在步骤S24实施之前，对键合后的衬底实施倒角处理。
附图3D所示，步骤S25，在所述第二绝缘层380上粘贴形成一保护层370，以防止所述第二绝缘层380被腐蚀。在后续腐蚀步骤中，所述保护层370不会被腐蚀液腐蚀，则腐蚀液也不会腐蚀到绝缘层330，从而可以得到低翘曲度的半导体衬底。
在本发明中，可以但不限于采用如下方法粘贴保护层370：
(1)在减薄后的衬底放在贴膜工作台上；
(2)将待贴膜的一面向上，即第二绝缘层380向上，取出与衬底大小相同的蓝膜；
(3)在撕膜的过程中使用滑杆将膜紧紧贴在衬底的第二绝缘层380上。
附图3E所示，步骤S26，对衬底实施腐蚀步骤，以去除所述氧化层350。此步骤中，采用腐蚀的方法去除氧化层350以暴露出器件层360。当采用腐蚀液对衬底进行腐蚀去除氧化层350时，虽然腐蚀液会溅射或流动到衬底的底部，但由于衬底底部粘贴有保护层370，第二绝缘层380没有被腐蚀液腐蚀，从而本发明能够提供一种低翘曲度的半导体衬底。若所述氧化层350为二氧化硅，则所述腐蚀采用的腐蚀液优选为HF。
附图4所示为根据本发明方法制备的半导体衬底的透射电镜图。从附图4中可以看出，去除氧化层350之后，与现有技术相比，半导体衬底倾斜角度变小，则说明半导体衬底翘曲度变小。附图5所示为本发明方法制备的半导体衬底与现有技术中的常规方法制备的半导体衬底的翘曲度的对比，从附图5中可以看出，由于本发明在第二绝缘层380表面上有保护层370，使得第二绝缘层380没有被腐蚀液腐蚀，因此，采用本发明方法制备的半导体衬底的翘曲度比现有技术中的常规方法制备的半导体衬底的翘曲度低。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

  1. 一种低翘曲度的半导体衬底的制备方法，其特征在于，包括如下步骤：
    提供第一衬底及第二衬底，所述第一衬底具有相对的第一表面和第二表面，
    所述第一表面上设置有第一绝缘层，所述第二表面上设置有第二绝缘层，
    所述第二衬底包括支撑层、支撑层表面的氧化层以及氧化层表面的器件层；
    以器件层及第一绝缘层为中间层，将第一衬底与第二衬底键合在一起；
    在所述第二绝缘层表面粘贴形成一保护层，所述第二绝缘层和保护层的作用在于调整所述半导体衬底的翘曲度。
  2. 根据权利要求1所述的低翘曲度的半导体衬底，其特征在于，所述保护层为蓝膜，所述第一绝缘层和第二绝缘层的材料各自独立地选自于氧化硅、氮化硅、以及氮氧化硅的任意一种。
  3. 根据权利要求1所述的低翘曲度的半导体衬底的制备方法，其特征在于，
    所述键合步骤后，进一步包括一对键合后的衬底实施退火的步骤。
  4. 根据权利要求1所述的低翘曲度的半导体衬底的制备方法，其特征在于，
    所述键合步骤后，进一步包括一对第二衬底进行减薄的步骤，以去除所述支撑层。
  5. 根据权利要求4所述的低翘曲度的半导体衬底的制备方法，其特征在于，
    所述减薄步骤之后，进一步包括一腐蚀步骤，以去除所述氧化层。
  6. 根据权利要求4所述的低翘曲度的半导体衬底的制备方法，其特征在于，
    所述减薄采用的方法选自于机械研磨、化学机械抛光中的一种或两种。
  7. 根据权利要求1所述的低翘曲度的半导体衬底的制备方法，其特征在于，
    所述键合步骤后，进一步包括一对第二衬底及第一绝缘层实施倒角的步骤。
PCT/CN2014/089977 2013-11-22 2014-10-31 低翘曲度的半导体衬底的制备方法 WO2015074478A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/161,555 US20170018454A1 (en) 2013-11-22 2016-05-23 Method for preparing low-warpage semiconductor substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310590120.7A CN103560106B (zh) 2013-11-22 2013-11-22 低翘曲度的半导体衬底的制备方法
CN201310590120.7 2013-11-22

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/161,555 Continuation US20170018454A1 (en) 2013-11-22 2016-05-23 Method for preparing low-warpage semiconductor substrate

Publications (1)

Publication Number Publication Date
WO2015074478A1 true WO2015074478A1 (zh) 2015-05-28

Family

ID=50014320

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/089977 WO2015074478A1 (zh) 2013-11-22 2014-10-31 低翘曲度的半导体衬底的制备方法

Country Status (3)

Country Link
US (1) US20170018454A1 (zh)
CN (1) CN103560106B (zh)
WO (1) WO2015074478A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103560136A (zh) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 低翘曲度的半导体衬底及其制备方法
CN103560106B (zh) * 2013-11-22 2017-01-18 上海新傲科技股份有限公司 低翘曲度的半导体衬底的制备方法
CN109686692A (zh) * 2017-10-18 2019-04-26 昆山中辰矽晶有限公司 手动贴膜边缘去氧化层的制程方法
CN111515792A (zh) * 2020-04-28 2020-08-11 福建晶安光电有限公司 一种适合石墨烯生长的衬底材料及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140210A (en) * 1997-09-26 2000-10-31 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer and SOI wafer fabricated thereby
CN1744298A (zh) * 2005-07-29 2006-03-08 上海新傲科技有限公司 一种绝缘体上硅的制作方法
CN101064242A (zh) * 2002-10-25 2007-10-31 株式会社瑞萨科技 半导体电路器件的制造方法
CN101101891A (zh) * 2006-07-07 2008-01-09 上海新傲科技有限公司 绝缘体上硅及其制备工艺
CN103560106A (zh) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 低翘曲度的半导体衬底的制备方法
CN103560136A (zh) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 低翘曲度的半导体衬底及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04163907A (ja) * 1990-10-29 1992-06-09 Fujitsu Ltd 半導体基板
JPH11345954A (ja) * 1998-05-29 1999-12-14 Shin Etsu Handotai Co Ltd 半導体基板及びその製造方法
CN102903607A (zh) * 2011-06-30 2013-01-30 上海新傲科技股份有限公司 采用选择性腐蚀制备带有绝缘埋层的衬底的制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140210A (en) * 1997-09-26 2000-10-31 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer and SOI wafer fabricated thereby
CN101064242A (zh) * 2002-10-25 2007-10-31 株式会社瑞萨科技 半导体电路器件的制造方法
CN1744298A (zh) * 2005-07-29 2006-03-08 上海新傲科技有限公司 一种绝缘体上硅的制作方法
CN101101891A (zh) * 2006-07-07 2008-01-09 上海新傲科技有限公司 绝缘体上硅及其制备工艺
CN103560106A (zh) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 低翘曲度的半导体衬底的制备方法
CN103560136A (zh) * 2013-11-22 2014-02-05 上海新傲科技股份有限公司 低翘曲度的半导体衬底及其制备方法

Also Published As

Publication number Publication date
CN103560106A (zh) 2014-02-05
CN103560106B (zh) 2017-01-18
US20170018454A1 (en) 2017-01-19

Similar Documents

Publication Publication Date Title
TWI721223B (zh) 具有較佳電荷捕獲效率之高電阻率絕緣體上矽基板
JP6650463B2 (ja) 電荷トラップ層を備えた高抵抗率の半導体・オン・インシュレーターウェハーの製造方法
JP7206366B2 (ja) 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
TWI758133B (zh) 製備多層結構的方法
US20240022229A1 (en) Composite substrate
JPH03132055A (ja) 半導体基板の製造方法
US11587824B2 (en) Method for manufacturing semiconductor structure
WO2015074478A1 (zh) 低翘曲度的半导体衬底的制备方法
WO2014037793A1 (en) Pseudo substrate with improved efficiency of usage of single crystal material
WO2015074479A1 (zh) 低翘曲度的半导体衬底及其制备方法
US10559471B2 (en) Method of manufacturing bonded wafer
JP5009124B2 (ja) 半導体基板の製造方法
US8853054B2 (en) Method of manufacturing silicon-on-insulator wafers
CN109075028B (zh) 贴合式soi晶圆的制造方法
WO2015074480A1 (zh) 边缘光滑的半导体衬底的制备方法
TWI775825B (zh) 特別是用於前側型成像器之絕緣體上半導體型結構，及製造此結構之方法
JP2017139266A (ja) 複合基板、半導体装置、およびこれらの製造方法
JP2007250676A (ja) 異種材料の積層基板の製造方法
CN110391173B (zh) 绝缘体上覆硅基板的制造方法及半导体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14863220

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14863220

Country of ref document: EP

Kind code of ref document: A1