CN107112204B - 贴合式soi晶圆的制造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000005498 polishing Methods 0.000 claims abstract description 154
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 95
- 229920005591 polysilicon Polymers 0.000 claims abstract description 71
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 230000003746 surface roughness Effects 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 238000000227 grinding Methods 0.000 claims description 9
- 238000003486 chemical etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 abstract 2
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- 230000000052 comparative effect Effects 0.000 description 18
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- 238000007254 oxidation reaction Methods 0.000 description 3
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
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Abstract
一种贴合式SOI晶圆的制造方法,将皆以单晶硅所构成的贴合晶圆及基底晶圆透过绝缘膜贴合而制造贴合式SOI晶圆,包含下列步骤,将多晶硅层堆积于基底晶圆的贴合面侧,研磨多晶硅层的表面,于贴合晶圆的贴合面形成绝缘膜,透过绝缘膜将基底晶圆的多晶硅层的研磨面与贴合晶圆贴合,以及将经贴合的贴合晶圆薄膜化而形成SOI层,其中于堆积多晶硅层的步骤中,作为基底晶圆使用具有化学蚀刻面的晶圆,于化学蚀刻面进行一次研磨后,于经一次研磨的面堆积多晶硅层,于研磨多晶硅层表面的步骤中,于多晶硅层表面进行二次研磨,或进行二次研磨及精研磨。
Description
技术领域
本发明涉及一种贴合式SOI晶圆的制造方法。
背景技术
由于携带终端机、网络通讯等的发达,对于透过无线的信息交流、信息量或通讯速度的要求,无上限的持续扩大着。近年,作为RF开关等高频装置,将至今的蓝宝石基底上硅(Silicon on sapphire,SOS)或GaAs的基板等所制作的单一组件,置换为于Si基板上集成化的装置,而小型化、集成化的技术被广泛采用。特别是使用SOI晶圆而制作高频装置的方法,大幅扩展了市场。
以高频装置的性能而言,为了防止通讯的串扰,二次谐波、三次谐波的控制成为主要的要求项目。为此,基板必须要是绝缘体。虽然在SOI晶圆中,将埋入氧化膜(BOX层)的厚度加大有作为一个方法而被考虑,但是氧化膜的导热率较差,无法除去高频装置运作时的发热成为问题。于是,考案有使用高电阻Si基板作为SOI晶圆的支承基板的方法。由此,能够抑制BOX层之下的电流传导,而能够抑制高频装置的谐波。但是,若于SOI层施加电压,BOX层正下方的Si基板表面将产生空乏层而形成反转层,由于产生于此部分的电流传导,而无法抑制谐波。为了解决此问题,采用有使BOX层的正下方内置有捕捉载体的层(例如参照专利文献1至3)。
作为捕捉载体的层,以多晶硅层为最普遍。多晶硅层在结晶边界捕捉载体,抑制电流传导。
作为将多晶硅层内置的方法,通过于支承基板用晶圆(基底晶圆)堆栈多晶硅层,并将其与带有氧化膜的晶圆(贴合晶圆)贴合,而能够制作内置有多晶硅层的SOI晶圆。但是,此时为了实现晶圆贴合,多晶硅层的表面必须为平滑,而考案有使用研磨除去表面粗糙而进行贴合的方法。
但是,在制造用于装置制作等的一般的经镜面研磨的单晶硅晶圆(以下称为PW)时,系例如以柴可斯基法育成单晶铸块,将此铸块切片而加工为薄圆板状后,经过倒角、抛光、蚀刻、研磨等各种步骤而加工为镜面状的晶圆(镜面晶圆)。
硅晶圆的研磨步骤中,通常经过自粗研磨至精研磨的多个阶段而进行研磨。例如,于抛光步骤或是蚀刻步骤之后,为了除去晶圆表面的扭曲,使其平坦化,以数μm左右的研磨量进行一次研磨。接着,为了去除一次研磨所产生的伤痕等、改善表面粗糙,以1μm左右的研磨量进行二次研磨。进一步,为了使其成为无雾的表面,以未满1μm的研磨量进行精研磨。晶圆的表面经过如此的粗研磨(一次研磨及二次研磨)及精研磨而镜面化(例如参照专利文献4的段落【0004】)。
随着研磨次数增加,将逐次使研磨磨粒的粒度较细、降低研磨布的硬度等使研磨条件缓和的同时,设定条件以使各阶段受研磨的镜面部的平坦度或表面粗糙等变为较低的值而进行研磨(例如参照专利文献5的段落【0027】)。
特别是在直径300mm的硅晶圆中为了满足平坦度的严格规范而进行以双面研磨进行的一次研磨,之后为了改善表面的伤痕或表面粗糙而进行以单面研磨进行的表面二次研磨及精研磨(例如参照专利文献6的段落【0002】)。
〔现有技术文献〕
专利文献1:日本特表2007-507093号公报
专利文献2:日本特表2013-513234号公报
专利文献3:日本特表2014-509087号公报
专利文献4:日本特开2007-067179号公报
专利文献5:日本特开2014-093457号公报
专利文献6:日本特开2013-166200号公报
发明内容
如同前述,作为高频装置用的基板,开始采取使SOI晶圆的BOX层正下方内置捕捉载体的层的方法,作为此捕捉载体的层,以多晶硅层为最普遍。为了实现基底晶圆与贴和晶圆的贴合,基底晶圆上的多晶硅层表面必须为平滑,而考案有利用研磨以除去基底晶圆上的多晶硅层的表面粗糙而进行贴合。
于基底晶圆堆栈多晶硅时,基底晶圆的表面粗糙,并不一定必要为制作装置所必要的表面粗糙(与用于制作装置的PW相同的表面粗糙)。即使在化学蚀刻面(以下称为CW面)程度的表面粗糙的基板上,亦能够堆栈多晶硅层。
但是,于CW面上所堆栈的多晶硅层的表面,将反映出CW面的表面粗糙或起伏,为了得到能够贴合的平滑面,变得必须采取将堆栈多晶硅层后的研磨中的研磨量极端扩大等对策,成为问题。
但是另一方面,即使于PW面上堆栈多晶硅层,多晶硅层的表面粗糙,亦会较原本的PW面的表面粗糙更大幅恶化,为了得到能够贴合的平滑面,必须进行堆栈多晶硅层后的研磨。
这是变得与为了得到PW面的研磨为相同的步骤,重复在将多晶硅堆栈于基底晶圆之前与之后两方面进行研磨的步骤,而具有变得使研磨步骤的效率(生产性)显著降低的结果的问题。
本发明鉴于上述各问题点,目的在于提供一种贴合式SOI晶圆的制造方法,包含有为了在研磨后得到能够抑制贴合后的孔隙产生的多晶硅面所必须的最低限的研磨步骤。
为了达成前述目的,本发明提供一种贴合式SOI晶圆的制造方法,用以制造贴合式SOI晶圆,该贴合式SOI晶圆将皆以单晶硅所构成的贴合晶圆及基底晶圆透过绝缘膜而予以贴合,该制造方法包含下列步骤:将多晶硅层堆积于该基底晶圆的贴合面侧;研磨该多晶硅层的表面;于该贴合晶圆的贴合面形成该绝缘膜;透过该绝缘膜将该基底晶圆的该多晶硅层的研磨面与该贴合晶圆贴合;以及将经贴合的该贴合晶圆薄膜化而形成SOI层,其中,于堆积该多晶硅层的步骤中,作为该基底晶圆,使用具有化学蚀刻面的晶圆,于该化学蚀刻面进行一次研磨后,于该经一次研磨的面堆积该多晶硅层,于研磨该多晶硅层的表面的步骤中,于该多晶硅层的表面进行二次研磨,或进行二次研磨及精研磨。
如此,于堆栈多晶硅的步骤中,于化学蚀刻面进行一次研磨后,不进行二次研磨、精研磨,于经一次研磨的面堆栈多晶硅,在研磨多晶硅层的表面的步骤中,于多晶硅层的表面不进行一次研磨而进行二次研磨或二次研磨及精研磨,以使贴合式SOI晶圆的制造中的研磨步骤,成为为了在研磨后得到能够抑制贴合后的孔隙产生的多晶硅面所必须的最低限的研磨步骤。
此时,作为该基底晶圆,以使用电阻率100Ω·cm以上之物为佳。
若使用如此的基底晶圆,便能够制作适合作为高频装置用的基板的SOI晶圆。
此时,该一次研磨以双面研磨进行为佳。
作为基底晶圆的多晶硅层成长前的一次研磨,能够适当使用双面研磨。
如同前述,依照本发明的贴合式SOI晶圆的制造方法,能够使贴合式SOI晶圆的制造中的研磨步骤,成为为了在研磨后得到能够抑制贴合后的孔隙产生的多晶硅面所必须的最低限的研磨步骤。因此,能够以低成本而以高生产性得到高质量的贴合式SOI晶圆。
附图说明
图1是显示本发明的贴合式SOI晶圆的制造方法的流程的示意图。
图2是显示本发明的贴合式SOI晶圆的制造方法的实施形式的一例的示意图。
具体实施方式
以下参照图而详细说明关于本发明的实施例,但本发明并不限定于此。
如同前述,作为高频装置用的基板,逐渐采用使SOI晶圆的BOX层的正下方内置作为捕捉载体的层的多晶硅层的方法。于如此的SOI晶圆的制造中,为了实现基底晶圆及贴合晶圆的贴合,基底晶圆上的多晶硅层的表面必须为平滑,而考案有利用研磨除去基底晶圆上的多晶硅层的表面粗糙而进行贴合。
但是,除了为了于基底晶圆的CW面形成的多结晶层中得到能够贴合的平滑面,必须采取将堆栈多晶硅层后的研磨中的研磨量极端扩大等对策,成为问题之外,即使于PW面上堆栈多晶硅层,多晶硅层的表面粗糙亦会较原本的PW面的表面粗糙大幅恶化,为了得到能够贴合的平滑面,必须进行多晶硅层堆栈后的研磨。
此成为与为了得到PW面的研磨相同的步骤,而重复了在堆栈多晶硅层前及堆积后两方面进行研磨的步骤,有研磨步骤的效率显著下降的问题。
于是,发明人持续研究关于能够使贴合式SOI晶圆的制造中的研磨步骤,成为为了在研磨后得到能够抑制贴合后的孔隙的产生的多晶硅面所必须的最低限的研磨步骤的贴合式SOI晶圆的制造方法。
结果,发现了于堆栈多晶硅的步骤中,于化学蚀刻面进行一次研磨后,于经进行一次研磨的面堆栈多晶硅层,于研磨多晶硅层的表面的步骤中,于多晶硅层表面进行二次研磨,或是进行二次研磨及精研磨的步骤,以使贴合式SOI晶圆的制造中的研磨步骤,成为为了在研磨后得到能够抑制贴合后的孔隙的产生的多晶硅面所必须的最低限的研磨步骤的贴合式SOI晶圆的制造方法,而达成本发明。
以下一边参照图1至2,说明本发明的贴合式SOI晶圆的制造方法。
首先,准备具有化学蚀刻面的基底晶圆(参照图1的步骤S11)。
具体而言,准备例如将单晶硅铸锭切片,施加抛光及激光雕刻、化学蚀刻,而具有化学蚀刻面的基底晶圆11(参照图2的(d))。
接着,于基底晶圆的化学蚀刻面进行一次研磨(参照图1的步骤S12)。
具体而言,例如对基底晶圆11的至少一侧的化学蚀刻面(图2中,为基底晶圆11的至少上表面)施以一次研磨,进一步,施加镜面抛光加工(参照图2的(e))。此状态下,基底晶圆11表面的表面粗糙以AFM测定(1μm角)的RMS值为约0.3mm。
接着,于基底晶圆的经进行一次研磨的面堆栈多晶硅层(参照图1的步骤S13)。
具体而言,例如于基底晶圆11的经进行一次研磨的面(图2的(e)的基底晶圆11的上表面)堆栈多晶硅层12(参照图2的(f))。多晶硅层12一般由CVD装置所形成。作为CVD装置的一个形态,虽有以堆栈单晶硅层为目的长晶炉,但于此装置中,亦可透过选择将堆栈温度低温化等的条件,而能够堆栈多晶硅而不是单晶硅。堆栈多晶硅层后的表面的表面粗糙以AFM测定(1μm角)的RMS值为约15nm。
接着,对基底晶圆的多晶硅层表面,进行二次研磨,或是进行二次研磨及精研磨(参照图1的步骤S14)。
具体而言,例如透过对基底晶圆11的多晶硅层12的表面以0.5至1μm左右的研磨量进行二次研磨,进一步因应需求,以较二次研磨更少的研磨量进行精研磨,而能够得到以AFM测定(1μm角)的RMS值为约0.15nm左右的表面粗糙(参照图2的(g))。
由于仅二次研磨亦能够得到以AFM测定(1μm角)的RMS值为约0.20nm以下的表面粗糙,虽然以此表面粗糙状态进行贴合晶圆的贴合亦能够减低贴合不良,但透过在二次研磨后进一步进行精研磨,将表面粗糙更加优质化,能够更进一步减低贴合不良。
另一方面,于贴合晶圆的贴合面形成绝缘膜(参照图1的步骤S15)。
具体而言,例如作为基底晶圆10,准备单晶硅晶圆(参照图2的(a)),施加使成为埋入氧化膜层(BOX层,绝缘膜)16(参照图2的(i))的氧化膜(绝缘膜)13成长的氧化膜成长(例如热氧化处理)(参照图2的(b))。
进一步而言,能够自氧化膜13上方通过离子注入机,注入氢离子或惰性气体离子,而形成离子注入层17(参照图2的(c))。此时,选择离子注入加速电压以能够得到作为目标的剥离硅层(即SOI层15(参照图2的(i))的厚度。
接着透过绝缘层将基底晶圆的多晶硅层的研磨面与贴合晶圆贴合(参照图1的步骤16)
具体而言,例如使形成有多晶硅层12的基底晶圆11,密合而贴合于形成有离子注入层17的贴合晶圆10,使基底晶圆11形成有多晶硅层12的面与贴合晶圆10的注入面接触。
接着,将已贴合的贴合晶圆薄膜化,而形成SOI层(参照图1的步骤S17)。
具体而言,例如于贴合式晶圆施加使微小气泡层产生于离子注入层17的热处理(剥离热处理),于产生的微小汽泡层进行剥离,制作于基底晶圆11上形成有埋入氧化膜16及SOI层15的贴合式晶圆14(参照图2的(i))。另外,此时衍生出具有剥离面19的剥离晶圆18。
如同前述,通过于堆栈多晶硅层的步骤中,于化学蚀刻面进行一次研磨后,不进行二次研磨及精研磨,而于经进行一次研磨的面堆栈多晶硅层,于研磨多晶硅层的表面的步骤中,不于多晶硅层的表面施加一次研磨,而进行二次研磨及精研磨,能够使贴合式SOI晶圆的制造中的研磨步骤,成为为了在研磨后得到能够抑制贴合后的孔隙的产生的多晶硅面所必须的最低限的研磨步骤的贴合式SOI晶圆的制造方法之故,效率极高。
此处,作为基底晶圆11,以使用电阻率为100Ω·cm以上者为佳。
使用如此的基底晶圆,便能够制作适合作为高频装置用的基板的SOI晶圆。
上述中,图1的S11至S14及S15、图2的(a)至(c)及(d)至(g),各别先进行任一个步骤皆可,当然亦可同时进行。
又,以将前述的一次研磨以双面研磨进行为佳。
作为基底晶圆的多晶硅层成长前的一次研磨,能够适当使用双面研磨。
另外,于堆栈多晶硅层前的基底晶圆的表面先进行一次研磨及二次研磨,且于堆栈多晶硅层后于其表面仅施加精研磨步骤的流程中,由于无法将多晶硅的表面粗糙充分降低,因此无法避免于贴合面所产生的孔隙所造成的贴合不良的增加。
以下显示实施例及比较例以更具体说明本发明,但本发明并不限定于此。
(实施例)
作为贴合晶圆,准备直径300mm、p型、10Ω·cm、结晶方向<100>的无COP(crystaloriented particle)的CZ单晶硅晶圆(PW:镜面研磨晶圆),透过热氧化成长200nm的氧化膜后,于离子注入机,以70keV的加速能量注入H+离子6×1016atoms/cm2。
又,作为基底晶圆,对自氧浓度9.6ppma(ASTM’79)、电阻率5200Ω·cm的CA单晶硅切片,且经过抛光及外周打磨、里面激光雕刻的步骤、及化学蚀刻所制作的CW晶圆,以双面研磨机进行一次研磨,将外周部镜面抛光研磨。此时晶圆表面的表面粗糙,以AFM测定(1μm角)的RMS值为约0.3nm。对于此晶圆,于长晶用的长晶炉中,于一次研磨面上以900℃的温度将多晶硅层以2.5μm的厚度进行堆栈后,对多晶硅层的表面,施加研磨量0.5μm的二次研磨及精研磨(皆为单面研磨)。能够于基底晶圆上堆栈有2μm多晶硅层的研磨后的晶圆,得到表面粗糙在AFM测定(1μm角)的RMS值为约0.15nm的晶圆。
将前述贴合晶圆与表面具有多晶硅层的高电阻晶圆(基底晶圆)贴合、施加热处理,则贴合晶圆的氢离子注入层产生剥离。之后,于氢气氛围下进行1150℃30秒的RTA处理(平坦化热处理)后,透过氧化热处理及HF洗净,能够得到SOI层的厚度为150nm,且内置有多晶硅层的SOI晶圆。
实施例的贴合式SOI晶圆中,于氢离子注入层产生剥离的剥离步骤后,由于SOI层不被传递至基底晶圆侧所导致的直径1mm以上的孔隙的产生数为0个。
又,实施例的制造步骤中的晶圆的研磨步骤,为多晶硅层堆栈前的一次研磨、多晶硅层堆栈后的二次研磨及精研磨,若以进行一次「二次研磨+精研磨」时的生产性为1,则实施例的贴合式SOI晶圆的研磨步骤的生产性为1。
(比较例1)
与实施例相同,制造贴合式SOI晶圆。但是,基底晶圆为对自CZ单晶硅切片,经过抛光及外部打磨、里面激光雕刻的步骤、及化学蚀刻所制作的CW晶圆,以双面研磨机进行一次研磨,将外周部镜面抛光研磨后,进一步进行二次研磨及精研磨后之物。此时间点晶圆的表面粗糙,于AFM测定(1μm角)的RMS值为约0.1nm。又,于比较例1中,堆栈多晶硅层后,与实施例2同样进行二次研磨及精研磨,其研磨后的表面粗糙为约0.15nm。
比较例1的贴合式SOI晶圆中,于氢离子注入层产生剥离的剥离步骤后,由于SOI层不被传递至基底晶圆侧所导致的直径1mm以上的孔隙的产生数为0个。
但是,比较例的步骤中,晶圆的研磨步骤,为多晶硅层堆栈前的一次研磨、二次研磨及精研磨、多晶硅层堆栈后的二次研磨及精研磨,若以进行一次“二次研磨+精研磨”时的生产性为1,则比较例的贴合式SOI晶圆的研磨步骤的生产性为0.5。
(比较例2)
与比较例相同,制造贴合式SOI晶圆。但是,基底晶圆为对自CZ单晶硅切片,经过抛光及外部打磨、里面激光雕刻的步骤、及化学蚀刻所制作的CW晶圆,不进行一次研磨。此时间点晶圆的表面粗糙,于AFM测定(1μm角)的RMS值为约10nm。又,于比较例2中,堆栈多晶硅层后的研磨后的表面粗糙,以AFM测定(1μm角)的RMS值约为0.25nm。
比较例2中,由于多晶硅层研磨后的表面粗糙较大而贴合并不充分,于氢离子注入层产生剥离的剥离步骤后,由于SOI层不被传递至基底晶圆侧所导致的直径1mm以上的孔隙的在表面范围内大量产生。
另外,比较例2中,于前述的剥离步骤中,由于孔隙大量产生于表面范围内,贴合式SOI晶圆的制造中止之故,因此不进行研磨步骤的生产性的评价。
前述实施例、比较例1、及比较例2的步骤及结果显示于表1。
表1
※以进行一次「二次研磨+精研磨」时的生产性为1时的生产性
如自表1所知,于基底晶圆研磨步骤仅进行一次研磨的实施例中,得到与于多晶硅层研磨后的基底晶圆研磨步骤经进行一次研磨、二次研磨及精研磨的比较例1同等程度的表面粗糙,由此,与比较例1同样于剥离步骤后不产生直径1mm以上的孔隙,并且得到较比较例1更高的研磨步骤的生产性。又,基底晶圆不进行研磨的比较例2中,由于多晶硅层研磨后的表面粗糙,较实施例、比较例1更大,贴合变得不充分,因此剥离步骤后直径1mm以上的孔隙于表面范围内大量产生,而成为不得不中止贴合式SOI晶圆的制造的状况。
另外,本发明并不为前述实施例所限制。前述实施例为例示,具有与本发明的申请专利范围所记载的技术思想为实质相同的构成,且达成同样作用效果者,皆包含于本发明的技术范围。
Claims (3)
1.一种贴合式SOI晶圆的制造方法,用以制造贴合式SOI晶圆,该贴合式SOI晶圆将贴合晶圆及基底晶圆透过绝缘膜而予以贴合,该贴合晶圆及该基底晶圆由单晶硅构成,该制造方法包含下列步骤:
将多晶硅层堆积于该基底晶圆的贴合面侧;
研磨该多晶硅层的表面;
于该贴合晶圆的贴合面形成该绝缘膜;
透过该绝缘膜将该基底晶圆的该多晶硅层的研磨面与该贴合晶圆贴合;以及
将经贴合的该贴合晶圆薄膜化而形成SOI层,
其中,于堆积该多晶硅层的步骤中,作为该基底晶圆,使用具有化学蚀刻面的晶圆,于该化学蚀刻面进行一次研磨,而使该基底晶圆表面的表面粗糙的RMS值为0.3nm后,于该经一次研磨的面堆积该多晶硅层,
于研磨该多晶硅层的表面的步骤中,于该多晶硅层的表面进行二次研磨,或进行二次研磨及精研磨,而使该多晶硅层表面的表面粗糙的RMS值为0.20nm。
2.如权利要求1所述的贴合式SOI晶圆的制造方法,其中该基底晶圆为电阻率100Ω·cm以上。
3.如权利要求1或2所述的贴合式SOI晶圆的制造方法,其中该一次研磨以双面研磨进行。
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WO2016081367A1 (en) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION |
CN107533953B (zh) | 2015-03-03 | 2021-05-11 | 环球晶圆股份有限公司 | 具有可控膜应力的在硅衬底上沉积电荷捕获多晶硅膜的方法 |
EP3304586B1 (en) | 2015-06-01 | 2020-10-07 | GlobalWafers Co., Ltd. | A method of manufacturing silicon germanium-on-insulator |
JP6447439B2 (ja) * | 2015-09-28 | 2019-01-09 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
CN117198983A (zh) | 2015-11-20 | 2023-12-08 | 环球晶圆股份有限公司 | 使半导体表面平整的制造方法 |
CN116314384A (zh) | 2016-06-08 | 2023-06-23 | 环球晶圆股份有限公司 | 具有经改进的机械强度的高电阻率单晶硅锭及晶片 |
US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
TWI589023B (zh) * | 2016-06-27 | 2017-06-21 | 國立暨南國際大學 | 半導體裝置用基材及使用其之半導體裝置 |
JP6614076B2 (ja) * | 2016-09-07 | 2019-12-04 | 信越半導体株式会社 | 貼り合わせ用基板の表面欠陥の評価方法 |
JP6919579B2 (ja) * | 2018-01-17 | 2021-08-18 | 株式会社Sumco | 貼り合わせウェーハの製造方法、貼り合わせウェーハ |
US10818540B2 (en) | 2018-06-08 | 2020-10-27 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
CN116013777B (zh) * | 2023-03-27 | 2023-06-06 | 成都功成半导体有限公司 | 一种SiC晶圆自动键合热氧生长方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376335B1 (en) * | 2000-02-17 | 2002-04-23 | Memc Electronic Materials, Inc. | Semiconductor wafer manufacturing process |
US6475072B1 (en) * | 2000-09-29 | 2002-11-05 | International Business Machines Corporation | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) |
US6566267B1 (en) * | 1999-11-23 | 2003-05-20 | WACKER SILTRONIC GESELLSCHAFT FüR HALBLEITERMATERIALIEN AG | Inexpensive process for producing a multiplicity of semiconductor wafers |
CN102640278A (zh) * | 2009-12-04 | 2012-08-15 | Soitec公司 | 使电损耗减小的绝缘体上半导体型结构的制造方法及相应的结构 |
JP5532680B2 (ja) * | 2009-05-27 | 2014-06-25 | 信越半導体株式会社 | Soiウェーハの製造方法およびsoiウェーハ |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0513441A (ja) * | 1991-06-28 | 1993-01-22 | Canon Inc | 薄膜mosトランジスタの製造方法 |
FR2838865B1 (fr) * | 2002-04-23 | 2005-10-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee |
WO2005031842A2 (en) * | 2003-09-26 | 2005-04-07 | Universite Catholique De Louvain | Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses |
JP2007067179A (ja) | 2005-08-31 | 2007-03-15 | Shin Etsu Handotai Co Ltd | 半導体ウエーハの鏡面研磨方法及び鏡面研磨システム |
FR2973158B1 (fr) | 2011-03-22 | 2014-02-28 | Soitec Silicon On Insulator | Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences |
JP5807580B2 (ja) | 2012-02-15 | 2015-11-10 | 信越半導体株式会社 | 研磨ヘッド及び研磨装置 |
JP6011930B2 (ja) | 2012-11-05 | 2016-10-25 | 信越半導体株式会社 | シリコンウェーハの評価方法及びそのエッチング液 |
-
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6566267B1 (en) * | 1999-11-23 | 2003-05-20 | WACKER SILTRONIC GESELLSCHAFT FüR HALBLEITERMATERIALIEN AG | Inexpensive process for producing a multiplicity of semiconductor wafers |
US6376335B1 (en) * | 2000-02-17 | 2002-04-23 | Memc Electronic Materials, Inc. | Semiconductor wafer manufacturing process |
US6475072B1 (en) * | 2000-09-29 | 2002-11-05 | International Business Machines Corporation | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) |
JP5532680B2 (ja) * | 2009-05-27 | 2014-06-25 | 信越半導体株式会社 | Soiウェーハの製造方法およびsoiウェーハ |
CN102640278A (zh) * | 2009-12-04 | 2012-08-15 | Soitec公司 | 使电损耗减小的绝缘体上半导体型结构的制造方法及相应的结构 |
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