JP2017505999A - 金属ポスト相互接続部を備えた下部パッケージ - Google Patents

金属ポスト相互接続部を備えた下部パッケージ Download PDF

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JP2017505999A
JP2017505999A JP2016549269A JP2016549269A JP2017505999A JP 2017505999 A JP2017505999 A JP 2017505999A JP 2016549269 A JP2016549269 A JP 2016549269A JP 2016549269 A JP2016549269 A JP 2016549269A JP 2017505999 A JP2017505999 A JP 2017505999A
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die
layer
package
interconnect
metal post
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JP2017505999A5 (enExample
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シーチュン・グ
ラティボル・ラドイチッチ
ドン・ウク・キム
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クアルコム，インコーポレイテッド
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    • H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/15192—Resurf arrangement of the internal vias
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10242—Metallic cylinders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018230534A1 (ja) * 2017-06-16 2018-12-20 株式会社村田製作所 回路基板および回路モジュール、ならびに回路基板の製造方法および回路モジュールの製造方法
JP2022145598A (ja) * 2021-03-19 2022-10-04 ナントン アクセス セミコンダクター シーオー．，エルティーディー 埋め込みパッケージ構造及びその製造方法
US20220406752A1 (en) * 2021-06-17 2022-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die with tapered sidewall in package and fabricating method thereof
JP2023060343A (ja) * 2018-11-30 2023-04-27 ローム株式会社 半導体モジュール
JP7574001B2 (ja) 2019-09-17 2024-10-28 インテル コーポレイション 集積回路パッケージのための高密度相互接続

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9735129B2 (en) * 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9478521B2 (en) * 2014-09-25 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package Structure
US9443799B2 (en) 2014-12-16 2016-09-13 International Business Machines Corporation Interposer with lattice construction and embedded conductive metal structures
US10515884B2 (en) * 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
KR20160122020A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 기판 및 이를 구비하는 반도체 패키지
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US10211160B2 (en) * 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US10438881B2 (en) * 2015-10-29 2019-10-08 Marvell World Trade Ltd. Packaging arrangements including high density interconnect bridge
US10707171B2 (en) 2015-12-22 2020-07-07 Intel Corporation Ultra small molded module integrated with die by module-on-wafer assembly
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US9865566B1 (en) * 2016-06-15 2018-01-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9960328B2 (en) * 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR101942727B1 (ko) * 2016-09-12 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
WO2018063171A1 (en) * 2016-09-28 2018-04-05 Intel Corporation Thermal conductivity for integrated circuit packaging
US10249552B2 (en) * 2017-02-22 2019-04-02 Jmj Korea Co., Ltd. Semiconductor package having double-sided heat dissipation structure
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10504854B2 (en) * 2017-12-07 2019-12-10 Intel Corporation Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same
CN109962152B (zh) * 2017-12-25 2024-06-18 成都万应微电子有限公司 热电冷却基板及封装方法、集成电路芯片及封装方法
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
KR102063470B1 (ko) * 2018-05-03 2020-01-09 삼성전자주식회사 반도체 패키지
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
CN109216298A (zh) * 2018-08-10 2019-01-15 华进半导体封装先导技术研发中心有限公司 一种扇出型芯片封装结构及其制造方法
CN109300882A (zh) * 2018-09-20 2019-02-01 蔡亲佳 堆叠嵌入式封装结构及其制作方法
CN109994438B (zh) * 2019-03-29 2021-04-02 上海中航光电子有限公司 芯片封装结构及其封装方法
US10930592B2 (en) * 2019-05-07 2021-02-23 Google Llc Wafer level fan-out application specific integrated circuit bridge memory stack
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12388061B2 (en) 2019-08-02 2025-08-12 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing semiconductor device
US11171127B2 (en) * 2019-08-02 2021-11-09 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing semiconductor device
US11581262B2 (en) * 2019-10-02 2023-02-14 Qualcomm Incorporated Package comprising a die and die side redistribution layers (RDL)
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11282756B2 (en) * 2020-08-17 2022-03-22 Taiwan Semiconductor Manufacturing Company Limited Organic interposer including stress-resistant bonding structures and methods of forming the same
US11764177B2 (en) * 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US12341116B2 (en) * 2021-01-06 2025-06-24 Huawei Technologies Co., Ltd. Chip package structure, preparation method, and electronic device
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
TWI825975B (zh) * 2021-09-10 2023-12-11 美商愛玻索立克公司 已清洗的封裝用基板的製造方法以及已清洗的封裝用基板
US20230094820A1 (en) 2021-09-22 2023-03-30 Rahul N. Manepalli Microelectronic packages with embedded interposers
US12165952B2 (en) * 2022-02-16 2024-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer directly bonded to bonding pads on a plurality of dies
US20240071938A1 (en) * 2022-08-31 2024-02-29 Intel Corporation Cavity-less interconnect component on glass core

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005166909A (ja) * 2003-12-02 2005-06-23 Fujikura Ltd パッケージ及びその製造方法
JP2012079734A (ja) * 2010-09-30 2012-04-19 Teramikros Inc 半導体装置及び半導体デバイス並びにそれらの製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
JP4498991B2 (ja) * 2005-07-15 2010-07-07 新光電気工業株式会社 半導体装置及び電子装置
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
JP2008091795A (ja) 2006-10-04 2008-04-17 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
US20080136004A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
FR2932004B1 (fr) 2008-06-03 2011-08-05 Commissariat Energie Atomique Dispositif electronique empile et procede de realisation d'un tel dispositif electronique
US8587129B2 (en) 2009-07-31 2013-11-19 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via base and method of manufacture thereof
US20110147908A1 (en) 2009-12-17 2011-06-23 Peng Sun Module for Use in a Multi Package Assembly and a Method of Making the Module and the Multi Package Assembly
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
KR20120048991A (ko) * 2010-11-08 2012-05-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8941222B2 (en) * 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US20130181359A1 (en) 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
US9412689B2 (en) 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
TWI508249B (zh) 2012-04-02 2015-11-11 矽品精密工業股份有限公司 封裝件、半導體封裝結構及其製法
JP6038517B2 (ja) 2012-07-13 2016-12-07 新光電気工業株式会社 配線基板及びその製造方法
US9735087B2 (en) * 2012-09-20 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level embedded heat spreader
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005166909A (ja) * 2003-12-02 2005-06-23 Fujikura Ltd パッケージ及びその製造方法
JP2012079734A (ja) * 2010-09-30 2012-04-19 Teramikros Inc 半導体装置及び半導体デバイス並びにそれらの製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018230534A1 (ja) * 2017-06-16 2018-12-20 株式会社村田製作所 回路基板および回路モジュール、ならびに回路基板の製造方法および回路モジュールの製造方法
US11310914B2 (en) 2017-06-16 2022-04-19 Murata Manufacturing Co., Ltd. Circuit board, circuit module, method of manufacturing circuit board, and method of manufacturing circuit module
JP2023060343A (ja) * 2018-11-30 2023-04-27 ローム株式会社 半導体モジュール
JP7498819B2 (ja) 2018-11-30 2024-06-12 ローム株式会社 半導体モジュール
JP7574001B2 (ja) 2019-09-17 2024-10-28 インテル コーポレイション 集積回路パッケージのための高密度相互接続
US12205902B2 (en) 2019-09-17 2025-01-21 Intel Corporation High-density interconnects for integrated circuit packages
JP2022145598A (ja) * 2021-03-19 2022-10-04 ナントン アクセス セミコンダクター シーオー．，エルティーディー 埋め込みパッケージ構造及びその製造方法
JP7405888B2 (ja) 2021-03-19 2023-12-26 ナントン アクセス セミコンダクター シーオー．，エルティーディー 埋め込みパッケージ構造及びその製造方法
US20220406752A1 (en) * 2021-06-17 2022-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die with tapered sidewall in package and fabricating method thereof
US12308346B2 (en) * 2021-06-17 2025-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die with tapered sidewall in package

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EP3108499A1 (en) 2016-12-28
US20150235991A1 (en) 2015-08-20

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