JP2017505999A - 金属ポスト相互接続部を備えた下部パッケージ - Google Patents
金属ポスト相互接続部を備えた下部パッケージ Download PDFInfo
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- JP2017505999A JP2017505999A JP2016549269A JP2016549269A JP2017505999A JP 2017505999 A JP2017505999 A JP 2017505999A JP 2016549269 A JP2016549269 A JP 2016549269A JP 2016549269 A JP2016549269 A JP 2016549269A JP 2017505999 A JP2017505999 A JP 2017505999A
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- die
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- interconnect
- metal post
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- 239000002184 metal Substances 0.000 title claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 229910000679 solder Inorganic materials 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 19
- 238000007747 plating Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 107
- 238000004519 manufacturing process Methods 0.000 description 17
- 239000011295 pitch Substances 0.000 description 15
- 235000012431 wafers Nutrition 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005553 drilling Methods 0.000 description 8
- 239000012792 core layer Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910010165 TiCu Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010952 in-situ formation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L21/4814—Conductive parts
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/3157—Partial encapsulation or coating
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract
Description
本出願は、2014年2月18日に出願した米国仮特許出願第61/941345号の出願日の優先権を主張するものであり、同仮特許出願は、2014年4月16日に出願した米国特許出願第14/254494号の出願日の優先権を主張するものであり、その両方が本明細書に、参照によりその全体が組み込まれる。
ここで図面に移ると、図1Aは、半導体インターポーザまたはガラスインターポーザ115を含む、金属ポスト改良型下部パッケージ100を示す。あるいは、インターポーザ115は、積層有機インターポーザを備えてもよい。代替実施形態では、インターポーザ115はその代わりに、単一のダイ105のみを支持する基板を備え得る。インターポーザ実施形態と類似して、下部パッケージ単一ダイ実施形態用の基板も、ガラス、半導体、または積層有機ポリマーを含み得る。
図1Aおよび図1Bに示す下部パッケージ100の製造は、ウェーハレベルプロセス(WLP)実施形態において実施されてもよく、個々に実施されてもよい。WLP実施形態では、インターポーザコア120が、初期には、全体として処理されるウェーハまたはパネル(図示せず)の一部である。パネルまたはウェーハは、複数のインターポーザコア120を含み、それらが、パネルまたはウェーハからインターポーザコア120をダイシングする前に、ダイ相互接続110および金属ポスト160を伴って処理される。あるいは、各インターポーザコア120が、パネルまたはウェーハからダイシングされた後に、個々に処理されてもよい。
製造方法は、図4のフローチャートに示すように要約され得る。ステップ400は、基板表面上の誘電体層内の複数のダイ相互接続開口および複数の金属ポスト開口を通じて、再配線層を露出させることを含む。図2Cに示すダイ相互接続開口201の形成、ならびに図2Eに示す金属ポスト開口225の形成が、ステップ400の例である。ステップ405は、ダイ相互接続開口内にダイ相互接続を形成することを含む。図2Dに示すダイ相互接続110の形成が、ステップ405の例である。最後に、ステップ410は、金属ポスト開口内に金属ポストを形成することを含む。図2Fに示す金属ポスト160の形成が、ステップ410の例である。
本明細書に開示した金属ポストを備えた下部パッケージを含む集積回路パッケージは、多種多様な電子システムに組み込まれ得る。たとえば、図5に示すように、セル電話500、ラップトップ505、およびタブレットPC510はすべて、本開示に従って構築された金属ポスト含有下部パッケージを組み込んだ集積回路パッケージを含み得る。音楽プレーヤ、ビデオプレーヤ、通信デバイス、およびパーソナルコンピュータなどの他の例示的な電子システムも、本開示に従って構築された集積回路パッケージを用いて構成され得る。
105 ダイ
107 はんだバンプ
110 ダイ相互接続
115 半導体インターポーザまたはガラスインターポーザ、基板
120 コア層、インターポーザコア
130 誘電体層
135 誘電体層
136 ボード側はんだレジストまたはパッシベーション層
140 上段ダイ側RDLまたは第1のダイ側RDL、上段ダイ側再配線層
150 ボード対向再配線層(RDL)
155 ボード対向はんだボール
156 誘電体層
160 金属ポスト、ピラー
165 モールドコンパウンド
170 上部側再配線層
185 基板貫通ビア
190 上部側はんだレジストまたはパッシベーション層
200 上部パッケージ、上段パッケージ、導電性ブラインドビア
201 ダイ相互接続開口
202 ボード対向面、ボード対向側
203 ダイ対向面
205 下段ダイ側RDLまたは第2のダイ側RDL、下段ダイ側再配線層
206 相互接続、バンプ
210 金属シード層
215 ウェーハまたはパネル、第1のマスク層
220 第2のマスク層
225 金属ポスト開口
240 アンダーフィル
245 モールドコンパウンド
250 完成した下部パッケージ
500 セル電話
505 ラップトップ
510 タブレットPC
Claims (30)
- 基板と、
ダイ側再配線層と、
前記ダイ側再配線層上のシード層と、
前記シード層を通じて前記ダイ側再配線層に電気的に結合された、複数のダイ相互接続と、
前記シード層を通じて前記ダイ側再配線層に電気的に結合された、複数の金属ポストと
を備える、パッケージ。 - 前記複数のダイ相互接続のうちの少なくともサブセットに電気的に結合された、少なくとも1つのダイをさらに備える、請求項1に記載のパッケージ。
- 前記基板が、ガラスインターポーザを備え、前記少なくとも1つのダイが、複数のダイを備え、各ダイが、前記ダイ相互接続のうちの対応するサブセットに電気的に結合される、請求項2に記載のパッケージ。
- 前記複数のダイを少なくとも部分的に封止するモールドコンパウンドをさらに備え、前記ダイ相互接続と前記金属ポストの両方が、銅およびニッケルからなる群から選択された金属を含む、請求項3に記載のパッケージ。
- 前記複数の金属ポストに電気的に結合された上部パッケージをさらに備える、請求項2に記載のパッケージ。
- 前記ダイ相互接続が、複数のはんだバンプを備える、請求項1に記載のパッケージ。
- 前記ダイ相互接続が、複数のはんだピラーを備える、請求項1に記載のパッケージ。
- 前記基板の中を延在する複数の基板貫通ビアと、
前記基板のボード対向面に隣接するボード対向再配線層と
をさらに備え、前記基板貫通ビアのうちの少なくともサブセットが、前記ダイ対向再配線層を前記ボード対向再配線層に電気的に結合させる、請求項1に記載のパッケージ。 - 前記基板の前記ボード対向面に隣接する複数のはんだボールをさらに備え、前記複数のはんだボールが、前記ボード対向再配線層に電気的に結合される、請求項8に記載のパッケージ。
- 前記ダイ対向再配線層および前記ボード対向再配線層がそれぞれ、パターン形成された銅金属層を備える、請求項8に記載のパッケージ。
- 基板上の再配線層に隣接する誘電体層の中に、複数のダイ相互接続開口を形成するステップと、
前記誘電体層の中に、複数の金属ポスト開口を形成するステップと、
前記ダイ相互接続開口内に、ダイ相互接続を形成するステップと、
前記金属ポスト開口内に、金属ポストを形成するステップと
を含む、方法。 - 前記再配線層上にシード層を堆積させるステップをさらに含み、前記ダイ相互接続を形成するステップが、前記シード層の、前記ダイ相互接続開口内に露出した部分の上に、前記ダイ相互接続をめっきするステップを含み、前記金属ポストを形成するステップが、前記シード層の、前記金属ポスト開口内に露出した部分の上に、前記金属ポストをめっきするステップを含む、請求項11に記載の方法。
- 前記ダイ相互接続をめっきするステップ、および前記金属ポストをめっきするステップが、銅およびニッケルからなる群から選択された金属をめっきするステップを含む、請求項12に記載の方法。
- 少なくとも1つのダイを、前記ダイ相互接続のうちの少なくともサブセットに取り付けるステップをさらに含む、請求項11に記載の方法。
- 前記少なくとも1つのダイを取り付けるステップが、複数のダイを前記複数のダイ相互接続に取り付けるステップを含む、請求項14に記載の方法。
- ダイをモールドコンパウンドで少なくとも部分的に封止するステップをさらに含む、請求項15に記載の方法。
- 前記再配線層を、前記基板のダイ対向面に隣接するダイ対向再配線層として形成するステップと、
前記基板のボード対向面上にボード対向再配線層を形成するステップと
をさらに含む、請求項11に記載の方法。 - 前記基板の中を延在する複数の基板貫通ビアを、前記基板貫通ビアが前記ダイ対向再配線層と前記ボード対向再配線層との間を電気的に結合するように形成するステップをさらに含む、請求項17に記載の方法。
- 前記ダイ相互接続をめっきするステップが、前記誘電体層上に第1のマスク層を堆積させるステップと、前記第1のマスク層を、前記ダイ相互接続開口を露出させるようにパターン形成するステップと、前記露出したダイ相互接続開口内に、前記ダイ相互接続をめっきするステップとを含む、請求項13に記載の方法。
- 前記金属ポストをめっきするステップが、前記誘電体層上に第2のマスク層を堆積させるステップと、前記第2のマスク層を、前記金属ポスト開口を露出させるようにパターン形成するステップと、前記露出した金属ポスト開口内に、前記金属ポストをめっきするステップとを含む、請求項19に記載の方法。
- インターポーザと、
複数のダイと、
ダイ側再配線層と、
前記ダイ側再配線層上のシード層と、
前記複数のダイを前記シード層を通じて前記ダイ側再配線層に電気的に結合させるための手段と、
前記ダイ側再配線層に電気的に結合された複数の金属ポストと
を備える、パッケージ。 - 前記インターポーザが、ガラスインターポーザを備える、請求項21に記載のパッケージ。
- 前記インターポーザが、半導体インターポーザを備える、請求項21に記載のパッケージ。
- 前記インターポーザの中を延在する複数の基板貫通ビアをさらに備え、前記複数の基板貫通ビアが、前記ダイ側再配線層に電気的に結合される、請求項21に記載のパッケージ。
- 前記パッケージが、セル電話、ラップトップ、タブレット、音楽プレーヤ、通信デバイス、コンピュータ、およびビデオプレーヤのうちの少なくとも1つに組み込まれる、請求項21に記載のパッケージ。
- 前記金属ポストが、めっき銅金属ポストを備える、請求項21に記載のパッケージ。
- インターポーザの上に、金属ポストおよびダイ相互接続をめっきするステップと、
前記ダイ相互接続の上に、複数のダイをマウントするステップと
を含む、方法。 - 前記金属ポストおよび前記ダイ相互接続をめっきするステップが、前記金属ポストおよび前記ダイ相互接続をシード層の上にめっきするステップを含む、請求項27に記載の方法。
- 前記シード層を原子層堆積を通じて堆積させるステップをさらに含む、請求項28に記載の方法。
- 前記ダイおよび前記金属ポストをモールドコンパウンドで部分的に包覆するステップをさらに含む、請求項28に記載の方法。
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US14/254,494 US10971476B2 (en) | 2014-02-18 | 2014-04-16 | Bottom package with metal post interconnections |
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