CN106030791A - 具有金属桩互连的底部封装 - Google Patents

具有金属桩互连的底部封装 Download PDF

Info

Publication number
CN106030791A
CN106030791A CN201580008881.4A CN201580008881A CN106030791A CN 106030791 A CN106030791 A CN 106030791A CN 201580008881 A CN201580008881 A CN 201580008881A CN 106030791 A CN106030791 A CN 106030791A
Authority
CN
China
Prior art keywords
tube core
interconnection
layer
metalline stake
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580008881.4A
Other languages
English (en)
Inventor
S·顾
R·拉多伊契奇
D·W·金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106030791A publication Critical patent/CN106030791A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10242—Metallic cylinders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供了包括多个金属桩的底部封装基板，该多个金属桩通过管芯侧重分布层电耦合至多个管芯互连。金属桩和管芯互连被镀敷到底部封装基板上的晶种层上。

Description

具有金属桩互连的底部封装
相关申请的交叉引用
本申请要求于2014年2月18日提交的美国临时专利申请序列号61/941,345的提交日的优先权，该临时申请要求于2014年4月16日提交的美国专利申请序列号14/254,494的提交日的优先权，这两篇申请的全部内容通过援引纳入于此。
技术领域
本申请涉及集成电路封装，尤其涉及具有金属桩互连的底部封装。
背景
有机基板由于其低成本而通常在层叠封装架构中使用。例如，触发器管芯(诸如微处理器)可通过多个焊料凸块或铜柱耦合至用于底部封装的有机基板的第一表面。为了支持至顶部封装基板的耦合或互连，底部封装基板具有足够大的占用面积，从而底部封装管芯在底部封装基板的第一表面上存在周界。该周界可随后支持至顶部封装的焊球互连。尽管结果所得的层叠封装架构由于其低成本而非常流行，但是有机基板通常不适于现代的细间距管芯，因为有机基板仅容适相对粗略的互连间距。该互连间距是基板至管芯互连(诸如，微凸块或铜柱)与底部封装至顶部封装互连(诸如，焊球)之间的分隔。
由于针对有机基板的互连间距限制，用于现代的细间距管芯的底部封装基板通常包括玻璃或半导体中介体。与有机基板形成对比，玻璃或半导体中介体支持细间距互连。因此将细间距管芯安装到中介体上是常规的，因为玻璃或硅中介体实现必要的细间距互连。多个细间距管芯(诸如，第一处理器管理和第二处理器管芯)可安装到同一中介体上。中介体通过重分布层(RDL)从每个管芯接收细间距互连(诸如，微凸块或铜柱)，该互连使得每个管芯能通过RDL与其他(诸)管芯通信。尽管结果所得的中介体封装因此是有利的，因为它容适必要的细间距互连，但是使处理器与相关联的外部存储器(诸如，使用层叠封装(PoP)构造的DRAM管芯)对接是常规的。但是中介体的占用面积已经有点大，因为它必须具有必要的表面面积以支持细间距管芯。
如果此类中介体还包括围绕细间距管芯的周界以向上存储器封装基板提供用于常规PoP焊球互连的空间，则中介体占用面积变得过多。例如，在底部封装的制造期间用模塑复合物来包裹中介体上的管芯和焊球互连是常规的。被包住的焊球必须随后被暴露，诸如通过使用对模塑复合物的激光钻孔。来自激光的热要求焊球与管芯之间的某个禁用(keep-out)距离。用于底部封装的结果所得的中介体因此需要相对较大的占用面积以不仅支持管芯和焊球，而且还支持焊球与管芯之间的禁用距离。另外，焊球必须相对较大以耦合至上封装。此种相对较大的互连尺寸要求相应较大的互连间距。中介体占用面积因此必须足够大以支持具有其必不可少的间距的焊球以及焊球与管芯之间的相关联的禁用面积两者，这减少了密度并且是昂贵的。作为替换方案，中介体可包括支持互连条(诸如，印刷电路条或硅或玻璃互连条)的周界。互连条包括与焊球相对的数个镀敷通孔。但在互连条中制造镀敷通孔还要求关于互连条外周界的某个距离或禁用面积。因此，不管常规中介体包括焊球还是互连条，中介体占用面积必须相对较大。
相应地，在本领域存在对具有减少的占用面积的底部封装基板(诸如，中介体)的需要。
概述
底部封装被提供有用于形成至顶部封装的互连的镀敷金属桩。与使用焊球或互连条以形成至上封装或附加管芯的互连的常规底部封装相比，该镀敷金属桩实现底部封装的减少的占用面积。底部封装包括支持一个或多个管芯的底部封装基板。在一些实施例中，底部封装基板可包括支持多个管芯的玻璃、硅、或层叠有机中介体。在替换性实施例中，底部封装基板可包括支持单个管芯的玻璃基板、半导体基板、或层叠有机基板。
为了提供减少的占用面积，底部封装基板包括通过重分布层(RDL)耦合至管芯互连的多个镀敷金属桩。由底部封装基板支持的(诸)管芯通过管芯互连耦合至RDL，从RDL耦合至金属桩，以及从金属桩耦合至顶部封装基板。与常规条互连实施例形成对比，金属桩和管芯互连两者被镀敷到覆盖RDL的晶种层上。管芯互连和金属桩可在管芯(或多个管芯)被附连至底部封装基板之前被镀敷到晶种层上。与常规的条互连或焊球实施例形成对比，金属桩可因此被沉积而无需禁用面积。与常规架构相比，本文公开的结果所得的底部封装基板因此具有有利地增强的密度。
附图简述
图1A是根据本公开的实施例的包括金属桩的底部封装的横截面视图。
图1B是图1A的底部封装在其接收顶部封装以形成层叠封装(PoP)构造时的横截面视图。
图2A是在沉积管芯互连和金属桩之前用于形成图1A的底部封装的中介体的横截面视图。
图2B是在沉积晶种层之后的图2A的中介体的横截面视图。
图2C是在沉积并图案化第一掩模层以形成管芯互连之后的图2B的中介体的横截面视图。
图2D是在沉积管芯互连并移除第一掩模层之后的图2C的中介体的横截面视图。
图2E是在沉积并图案化第二掩模层以形成金属桩之后的图2D的中介体的横截面视图。
图2F是在沉积金属桩并移除第二掩模层之后的图2E的中介体的横截面视图。
图2G是在一对管芯的附连之后的图2F的中介体的横截面视图。
图2H是在沉积模塑复合物以包裹管芯并在附连焊球之后的图2G的中介体的横截面视图。
图2I是在背侧研磨并形成面向板的重分布层和焊球之后的图2H的中介体的横截面视图。
图2I是在划片以完成底部封装的构造之后的图2I的中介体的横截面视图。
图3是示出关于管芯的金属桩的布置的图2J的底部封装的平面图。
图4是根据本公开的实施例的概述用于底部封装的制造方法的流程图。
图5解说了根据本公开的实施例的纳入底部封装的一些示例电子系统。
本公开的各实施例及其优势通过参考以下详细描述而被最好地理解。应当领会，在一个或多个附图中，相同的参考标记被用来标识相同的元件。
详细描述
为了避免来自常规使用焊球或条互连以将底部封装电耦合至顶部封装的过量占用面积需求，底部封装被提供有镀敷金属桩以形成至顶部封装的互连。与使用焊球或互连条以形成至上封装或附加管芯的互连的常规底部封装相比，该电镀金属桩实现底部封装的减少的占用面积。底部封装包括支持一个或多个管芯的底部封装基板。在一些实施例中，底部封装基板可包括支持多个管芯的玻璃、硅、或层叠有机中介体。在替换性实施例中，底部封装基板可包括支持单个管芯的玻璃、半导体或层叠有机基板。
因为本文公开的金属桩被镀敷在底部封装基板上，所以与要求将互连条嵌入到底部封装基板中的额外处理步骤的常规使用互连条相比，制造成本显著降低。此外，互连条制造通常要求对通孔的激光钻孔，该通孔随后被镀敷以在互连条中形成金属桩。互连条因此要求围绕其整个周界的相对较大的禁用面积。相反，本文公开的用于底部封装的金属桩的镀敷不需要激光钻孔。与不仅关于(诸)管芯而且还关于底部封装基板的周界使用互连条相比，被镀敷的金属桩因此需要减少的禁用面积。相应地，所公开的底部封装提供增加的密度和降低的制造成本。
为了提供减少的占用面积并增加密度，被镀敷的金属桩在底部封装中通过重分布层(RDL)电耦合至管芯互连。在一个实施例中，管芯互连包括金属柱。就此而言，常规中介体还可具有将管芯互连(诸如，金属柱)电耦合至条互连中的金属桩的重分布层。但常规的条互连是与底部封装基板分开制造的。在常规制造过程中，形成条互连的基板被钻孔(诸如通过激光或机械钻孔)以形成随后被镀敷以完成条互连桩的多个通孔。由于在条互连基板中形成通孔的钻孔或机械加工工艺，各通孔(以及因此将最终填充各通孔的金属桩)必须与条互连基板周界间隔某个禁用距离。如较早所讨论的，包含条互连的底部封装基板中的结果所得的禁用距离限制密度并且因此增加成本。
截然不同地，本文公开的金属桩不是在条互连中被分开制造的。相反，所公开的金属桩就地被制造在底部封装基板上。为了实现该就地形成，晶种层覆盖重分布层。介电层随后覆盖晶种层。窗口在介电层中敞开以形成互连开口以及还有金属桩开口。金属随后可被镀敷到暴露于管芯互连开口和金属桩开口中的晶种层部分上以形成管芯互连和金属桩。
因为暴露于管芯互连开口中的晶种层与暴露于金属桩开口中的晶种层相同，该晶种层在本文也被标记为单个晶种层。管芯互连和金属桩可在管芯(或多个管芯)被附连至底部封装基板之前被沉积到晶种层上。与使用互连条相比，金属桩可因此被形成而无需减少的关于基板边缘和关于(诸)管芯两者的禁用面积。相反，互连条从此类条的晶片划片并因此需要较大的禁用面积。与常规架构相比，本文公开的结果所得的底部封装基板因此具有有利地增强的密度和较低的制造成本。可参考以下示例实施例更好地领会这些有利特征。
示例实施例
现在转向附图，图1A解说了包括半导体或玻璃中介体115的金属桩增强型底部封装100。替换地，中介体115可包括层叠有机中介体。在替换性实施例中，中介体115可取而代之包括仅支持单个管芯105的基板。类似于中介体的实施例，用于底部封装单芯片实施例的基板可包括玻璃、半导体或层叠有机聚合物。
每个管芯105通过多个互连(诸如，焊料凸块107)耦合至基板115上的相应多个管芯互连110。管芯互连110还电耦合至管芯侧重分布层，该重分布层进而电耦合至多个金属桩160。在底部封装100中，管芯侧重分布层包括上部或第一管芯侧RDL 140和下部或第二管芯侧RDL 205。替换性实施例可具有用于管芯侧重分布层的恰好单个金属层或者可具有两个以上金属层。在底部封装100中，互连110电耦合至下部管芯侧RDL 205。进而，下部管芯侧RDL 205电耦合至上部管芯侧RDL 140，RDL 140随后电耦合至金属桩160。在一个实施例中，管芯互连110可被认为包括用于将管芯105电耦合至管芯侧重分布层(诸如，下部管芯侧RDL 205)的装置。管芯互连110和金属桩160可包括任何合适的镀敷金属，诸如铜或镍。类似地，本文公开的各种重分布层(诸如，铜和下部管芯侧重分布层140和205)可包括铜、镍、或其他导电金属。上部和下部管芯侧重分布层140和205在介电层130内形成导体或互连以将管芯互连110电耦合至金属桩160中的相应各个金属桩。例如，特定管芯互连110(诸如，管芯互连110a)可能需要电耦合至特定金属桩160，诸如金属桩160a。上部管芯侧RDL 140和下部管芯侧RDL 205因此将这些结构电耦合在一起。另外，上部和下部管芯侧RDL 140和205包括导体(未解说)以在管芯105之间电耦合管芯至管芯信号。类似地，下部管芯侧RDL 205将管芯105电耦合至多个穿板通孔185。
穿板通孔185从下部管芯侧RDL 205通过基板115的核心层120延伸至面向板的重分布层(RDL)150，RDL 150进而电耦合至面向板的焊球155。核心层120的组成取决于在底部封装100中使用的基板。例如，在玻璃中介体实施例中，核心层120将包括玻璃。类似地，在半导体中介体实施例中，核心层120将包括半导体。面向板的重分布层150可通过介电层156与核心层120绝缘。例如，介电层156可被层叠到核心层120上以还使穿板通孔185排成一行。板侧阻焊或钝化层136包括开口，以使得面向板的重分布层150的暴露焊盘部分可接收焊球155。焊球155电耦合至电路板(未解说)或底层封装。
模塑复合物165部分包覆管芯105和金属桩160。金属桩160还可电耦合至模塑复合物165和管芯105上的顶侧重分布层170。顶侧阻焊或钝化层190覆盖顶侧重分布层170。在替换性实施例中，顶侧重分布层170可通过钝化层190与管芯105绝缘，钝化层190包括开口以暴露顶侧重分布层170中的焊盘。这些开口可接收来自顶部封装200的互连206(诸如，焊料凸块或铜柱)，如图1B中所示。上部封装200在图1B中被示为恰好在其被安装到底部封装100之前。因此凸块206尚不与图1B中的顶侧重分布层170接触。顶侧重分布层170允许柱160与来自顶部封装200的互连206之间的扇出。现在将讨论示例制造方法。
示例制造方法
图1A和1B中示出的底部封装100的制造可在晶片级工艺(WLP)实施例中或个体地执行。在WLP实施例中，中介体核120可能最初是将作为整体被处理的晶片或面板(未解说)的一部分。该面板或晶片可能包括多个中介体核120，在将中介体核120从该面板或晶片划片之前用管芯互连110和金属桩160来处理中介体核120。替换地，每个中介体核120可在其从面板或晶片划片之后被个体地处理。
中介体核120可用各种方法配置有穿板通孔185。例如，中介体核120可以被激光钻孔或镀敷以形成通孔185。替换地，例如，可使用激光钻孔或机械加工来形成数个盲通孔，并且随后在暴露这些盲通孔的盲端的研磨步骤之前在中介体核120中镀敷该数个盲通孔，由此这些盲通孔形成穿板通孔185。例如，图2A解说了包括多个导电盲通孔200的中介体核120的横截面。在该实施例中，中介体核120是晶片或面板215的一部分，从而实现WLP制造技术。为了形成导电盲通孔200，中介体核120的面向管芯的表面被激光钻孔、蚀刻或机械钻孔以形成多个盲通孔，该多个盲通孔随后被镀敷以形成导电盲通孔200。在镀敷之前，盲通孔可用介电层(未解说)(诸如，图1A中示出的介电层156)来作衬里。
如图2A中所示，中介体核120的面向板的表面202尚未被接地以暴露导电盲通孔200的末端，从而形成关于图1A和1B讨论的穿板通孔185。因为图2A正解说初始制造步骤，所以图1A和1B中示出的穿板通孔185尚未形成。在形成导电盲通孔200之后，介电层135被沉积在支持介电层135的中介体核120的面向管芯的表面203上。例如，介电层135可以被层叠到面向管芯的表面203上。在此类实施例中，介电层135可包括聚酰亚胺、味之素构建膜、基于苯并环丁烯的聚合物、或其他合适的电介质材料。替换地，介电层135可被旋涂到面向管芯的表面203上或使用化学气相沉积技术来沉积。介电层135可分阶段地沉积以允许掩模步骤，因此可在介电层135内形成管芯侧重分布层(诸如，上部管芯侧重分布层140)。例如，金属(诸如铜或镍)可使用镀敷或无电镀敷技术来沉积以形成上部管芯侧RDL 140。如以上所讨论的，在本文公开的各种重分布层中可使用多个金属层。因此，介电层135可包括附加的管芯侧重分布层(诸如，如关于上部管芯侧RDL 140所讨论的类似地形成的下部管芯侧RDL 205)。在一些实施例中，中介体核120可包括半导体，诸如具有一些导电性的硅。为了防止此类导电基板短路，下部管芯侧RDL 205可通过介电层135与中介体核120绝缘，如图2B中所示。替换地，如果中介体核120包括玻璃或有机材料，则下部管芯侧RDL 205可接触中介体核120，如图1A中所示。
在其沉积之后，介电层135可被处理，诸如通过蚀刻以形成开口以供后续形成金属桩160和管芯互连110，如关于图1A和1B所讨论的。例如，介电层135可被图案化以包括管芯互连开口201，管芯互连开口201使下部管芯侧RDL205的相应部分暴露。类似地，介电层135可被图案化以包括金属桩开口225，金属桩开口225还使上部管芯侧RDL 140的相应部分暴露。
在形成管芯互连开口201和金属桩开口225之后，可随后用金属晶种层210来覆盖介电层135，如图2B中所示。例如，金属晶种层210可包括例如使用物理气相技术沉积的TiCu、TiW或铜。注意，单个晶种层210使管芯互连开口201和金属桩开口225两者排成一行。
如图2C中所示，第一掩模层215(诸如，湿或干蚀刻掩模层)可随后被沉积在晶种层210上并被图案化以重新暴露管芯互连开口201。在一些实施例中，与其在图2A中的尺寸相比，重新暴露可扩大管芯互连开口201。第一掩模层215因此是以与将填充管芯互连开口201的管芯互连(尚未形成)的期望高度匹配的厚度来沉积的。以此方式，管芯互连110可随后被镀敷到管芯互连开口201中，如图2D中所示。例如，合适的金属(诸如，铜或镍)可被电镀以形成管芯互连110。图2C的第一掩模层215可随后在此时从面板或晶片215剥离或移除。
图1A和1B的金属桩160具有与管芯互连110相比更大的高度或长度。因此，在一些实施例中，金属桩160在镀敷管芯互连110时不被镀敷，因为第一掩模层215具有与管芯互连110而非金属桩160的期望高度匹配的高度。金属桩160的形成可随后始于在晶种层210上沉积第二掩模层220，如图2E中所示。与第一掩模层215(图2C)相比，第二掩模层220具有更大厚度或高度以便与管芯互连110相比容适金属桩160的更大高度。类似于第一掩模层215，第二掩模层220被图案化以重新暴露并扩大金属桩开口225。
金属桩160可随后被镀敷到金属桩开口225中，且第二掩模层220被剥离或以其他方式移除，如图2F中所示。类似地，晶种层210的所暴露部分也在此时被蚀刻掉。然而，将保留管芯互连110和金属桩160被镀敷到其上的晶种层210的那些部分(未解说)。晶种层210的蚀刻可在管芯互连110和金属桩160下方保留的那些部分上产生相同的底切量(未解说)。
图2G中解说了管芯105的附连。管芯105上的互连(诸如，焊料凸块107或铜柱)电耦合至面板或晶片215上的相应管芯互连110。底部填料240还可在此时被应用以辅助将管芯105固定至面板或晶片215。
在管芯105已经被附连之后，模塑复合物245可随后被应用以至少部分地封装管芯105，如图2H中所示。模塑复合物也部分地封装金属桩160。金属桩和管芯105两者的上表面可在应用模塑复合物245之后暴露。替换地，研磨过程可被用于使金属桩160暴露。
穿板通孔185可随后暴露在中介体核120的底表面或面向板的表面上。例如，制造商可研磨晶片或面板215的面向板的一侧202以暴露导电盲通孔200的盲端(例如，图2H中示出)从而形成穿板通孔185。面向板的重分布层150可随后连同阻焊或钝化层136一起被沉积在面向板的表面202上，该阻焊或钝化层136被图案化以形成焊球155的开口，如图2I中所示。
因为以上关于图2A到图2I讨论的制造步骤涉及WLP实施例，所以这些步骤可全部在完整晶片或面板215上执行。从面板215划片因此提供了完整的底部封装250，如图2J中所示。
为了提供对底部封装250的密度优势的较好领会，在图3中的平面图中示出了其面向管芯的表面。金属桩160被安排在关于管芯105的底部封装250的周界上。模塑复合物245填充金属桩160与管芯105之间的空间。但此类安排不需要如在常规互连条封装中那样在金属桩160与管芯105之间包括禁用面积。如先前所讨论的，互连条的制造要求关于其周界的某个禁用面积，因为互连条基板通常被激光钻孔以形成用于金属桩的后续镀敷的通孔。此类钻孔不能距互连条基板周界太近地执行。截然不同地，金属桩160被沉积在与在其上沉积管芯互连110相同的晶种层210上，如关于例如图2F所讨论的。对于将焊球用于至顶部封装的互连的常规底部封装而言，密度变得甚至更差。因此，与常规办法相比，底部封装250已经有利地增加了密度。现在将讨论概述制造过程的流程图。
示例制造概述方法
该制造方法可概述为如图4的流程图中所示。步骤400包括通过基板表面上的介电层内的多个管芯互连开口和多个金属桩开口来暴露重分布层。图4C中示出的管芯互连开口201的形成以及图2E中示出的金属桩开口235的形成是步骤400的示例。步骤405包括在管芯互连开口中形成管芯互连。图2D中示出的管芯互连110的形成提供了步骤402的示例。最后，步骤410包括在金属桩开口中形成金属桩。图2F中示出的金属桩160的形成提供了步骤410的示例。
示例电子系统
包括如本文所公开的具有金属桩的底部封装的集成电路封装可被纳入到各种各样的电子系统中。例如，如图5中所示，蜂窝电话500、膝上型设备505和平板PC 510都可以包括纳入根据本公开构建的包含金属桩的底部封装的集成电路封装。其他示例性电子系统(诸如音乐播放器、视频播放器、通信设备和个人计算机)也可以用根据本公开构建的集成电路封装来配置。
如本领域普通技术人员至此将领会的并取决于手头的具体应用，可以在本公开的设备的材料、装置、配置和使用方法上做出许多修改、替换和变动而不会脱离本公开的精神和范围。有鉴于此，本公开的范围不应当被限定于本文中所解说和描述的特定实施例(因为其仅是作为本公开的一些示例)，而应当与所附权利要求及其功能等同方案完全相当。

Claims (30)

1.一种封装，包括：
基板；
管芯侧重分布层；
所述管芯侧重分布层上的晶种层；
通过所述晶种层电耦合至所述管芯侧重分布层的多个管芯互连；以及
通过所述晶种层电耦合至所述管芯侧重分布层的多个金属桩。
2.如权利要求1所述的封装，其特征在于，进一步包括电耦合至所述多个管芯互连的至少子集的至少一个管芯。
3.如权利要求2所述的封装，其特征在于，所述基板包括玻璃中介体，并且其中所述至少一个管芯包括多个管芯，每个管芯电耦合至所述管芯互连的相应子集。
4.如权利要求3所述的封装，其特征在于，进一步包括至少部分地封装所述多个管芯的模塑复合物，并且其中所述管芯互连和所述金属桩两者都包括选自由铜和镍构成的组中的金属。
5.如权利要求2所述的封装，其特征在于，进一步包括电耦合至所述多个金属桩的顶部封装。
6.如权利要求1所述的封装，其特征在于，所述管芯互连包括多个焊料凸块。
7.如权利要求1所述的封装，其特征在于，所述管芯互连包括多个焊柱。
8.如权利要求1所述的封装，其特征在于，进一步包括：
延伸通过所述基板的多个穿板通孔；
与所述基板的面向板的表面毗邻的面向板的重分布层，其中所述穿板通孔的至少子集将所述面向管芯的重分布层电耦合至所述面向板的重分布层。
9.如权利要求8所述的封装，其特征在于，进一步包括毗邻所述基板的所述面向板的表面的多个焊球，其中所述多个焊球电耦合至所述面向板的重分布层。
10.如权利要求8所述的封装，其特征在于，所述管芯侧重分布层和所述面向板的重分布层各自包括经图案化的铜金属层。
11.一种方法，包括：
在基板上通过毗邻重分布层的介电层来形成多个管芯互连开口；
通过所述介电层来形成多个金属桩开口；
在所述管芯互连开口中形成管芯互连；以及
在所述金属桩开口中形成金属桩。
12.如权利要求11所述的方法，其特征在于，进一步包括：
在所述重分布层上沉积晶种层，其中形成所述管芯互连包括将所述管芯互连镀敷到所述晶种层的暴露于所述管芯互连开口内的部分上，并且其中形成所述金属桩包括将所述金属桩镀敷到所述晶种层的暴露于所述金属桩开口内的部分上。
13.如权利要求12所述的方法，其特征在于，镀敷所述管芯互连和所述金属桩包括镀敷选自由铜和镍构成的组中的金属。
14.如权利要求11所述的方法，其特征在于，进一步包括将至少一个管芯附连至所述管芯互连的至少子集。
15.如权利要求14所述的方法，其特征在于，附连所述至少一个管芯包括将多个管芯附连至所述多个管芯互连。
16.如权利要求15所述的方法，其特征在于，进一步包括至少部分地用模塑复合物来封装管芯。
17.如权利要求11所述的方法，其特征在于，进一步包括：
形成所述重分布层作为与所述基板的面向管芯的表面毗邻的面向管芯的重分布层；以及
在所述基板的面向板的表面上形成面向板的重分布层。
18.如权利要求17所述的方法，其特征在于，进一步包括：
形成延伸通过所述基板的多个穿板通孔，以使得所述穿板通孔电耦合在所述面向管芯的重分布层与所述面向板的重分布层之间。
19.如权利要求13所述的方法，其特征在于，镀敷所述管芯互连包括在所述介电层上沉积第一掩模层，图案化所述第一掩模层以暴露所述管芯互连开口，以及将所述管芯互连镀敷到所暴露的管芯互连开口中。
20.如权利要求19所述的方法，其特征在于，镀敷所述金属桩包括在所述介电层上沉积第二掩模层，图案化所述第二掩模层以暴露所述金属桩开口，以及将所述金属桩镀敷到所暴露的金属桩开口中。
21.一种封装，包括：
中介体；
多个管芯；
管芯侧重分布层；
所述管芯侧重分布层上的晶种层；
用于通过所述晶种层来将所述多个管芯电耦合至所述管芯侧重分布层的装置；以及
电耦合至所述管芯侧重分布层的多个金属桩。
22.如权利要求21所述的封装，其特征在于，所述中介体包括玻璃中介体。
23.如权利要求21所述的封装，其特征在于，所述中介体包括半导体中介体。
24.如权利要求21所述的封装，其特征在于，进一步包括延伸通过所述中介体的多个穿板通孔，其中所述多个穿板通孔电耦合至所述管芯侧重分布层。
25.如权利要求21所述的封装，其特征在于，所述封装被纳入到以下至少一者中：蜂窝电话、膝上型设备、平板设备、音乐播放器、通信设备、计算机和视频播放器。
26.如权利要求21所述的封装，其特征在于，所述金属桩包括经镀敷的铜金属桩。
27.一种方法，包括：
将金属桩和管芯互连镀敷到中介体上；以及
将多个管芯安装到所述管芯互连上。
28.如权利要求27所述的方法，其特征在于，镀敷所述金属桩和所述管芯互连包括将所述金属桩和所述管芯互连镀敷到晶种层上。
29.如权利要求28所述的方法，其特征在于，进一步包括通过原子层沉积来沉积所述晶种层。
30.如权利要求28所述的方法，其特征在于，进一步包括用模塑复合物来部分地包覆所述管芯和所述金属桩。
CN201580008881.4A 2014-02-18 2015-02-06 具有金属桩互连的底部封装 Pending CN106030791A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461941345P 2014-02-18 2014-02-18
US61/941,345 2014-02-18
US14/254,494 US10971476B2 (en) 2014-02-18 2014-04-16 Bottom package with metal post interconnections
US14/254,494 2014-04-16
PCT/US2015/014870 WO2015126638A1 (en) 2014-02-18 2015-02-06 Bottom package with metal post interconnections

Publications (1)

Publication Number Publication Date
CN106030791A true CN106030791A (zh) 2016-10-12

Family

ID=53798778

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580008881.4A Pending CN106030791A (zh) 2014-02-18 2015-02-06 具有金属桩互连的底部封装

Country Status (5)

Country Link
US (1) US10971476B2 (zh)
EP (1) EP3108499B1 (zh)
JP (1) JP2017505999A (zh)
CN (1) CN106030791A (zh)
WO (1) WO2015126638A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216298A (zh) * 2018-08-10 2019-01-15 华进半导体封装先导技术研发中心有限公司 一种扇出型芯片封装结构及其制造方法

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9735129B2 (en) * 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9478521B2 (en) 2014-09-25 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package Structure
US9443799B2 (en) * 2014-12-16 2016-09-13 International Business Machines Corporation Interposer with lattice construction and embedded conductive metal structures
US10515884B2 (en) * 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
KR20160122020A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 기판 및 이를 구비하는 반도체 패키지
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US10211160B2 (en) * 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US10438881B2 (en) 2015-10-29 2019-10-08 Marvell World Trade Ltd. Packaging arrangements including high density interconnect bridge
US10707171B2 (en) * 2015-12-22 2020-07-07 Intel Corporation Ultra small molded module integrated with die by module-on-wafer assembly
US9865566B1 (en) * 2016-06-15 2018-01-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR101942727B1 (ko) * 2016-09-12 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
US10729000B2 (en) * 2016-09-28 2020-07-28 Intel Corporation Thermal conductivity for integrated circuit packaging
US10249552B2 (en) * 2017-02-22 2019-04-02 Jmj Korea Co., Ltd. Semiconductor package having double-sided heat dissipation structure
CN211858622U (zh) 2017-06-16 2020-11-03 株式会社村田制作所 电路基板及电路模块
US10504854B2 (en) * 2017-12-07 2019-12-10 Intel Corporation Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same
CN109962152A (zh) * 2017-12-25 2019-07-02 北京万应科技有限公司 热电冷却基板及封装方法、集成电路芯片及封装方法
US10468339B2 (en) * 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
KR102063470B1 (ko) * 2018-05-03 2020-01-09 삼성전자주식회사 반도체 패키지
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10910344B2 (en) * 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
CN109300882A (zh) * 2018-09-20 2019-02-01 蔡亲佳 堆叠嵌入式封装结构及其制作方法
CN109994438B (zh) * 2019-03-29 2021-04-02 上海中航光电子有限公司 芯片封装结构及其封装方法
US10930592B2 (en) * 2019-05-07 2021-02-23 Google Llc Wafer level fan-out application specific integrated circuit bridge memory stack
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11282756B2 (en) * 2020-08-17 2022-03-22 Taiwan Semiconductor Manufacturing Company Limited Organic interposer including stress-resistant bonding structures and methods of forming the same
US20220216171A1 (en) * 2021-01-06 2022-07-07 Huawei Technologies Co., Ltd. Chip package structure, preparation method, and electronic device
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法
US20220406752A1 (en) * 2021-06-17 2022-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die with tapered sidewall in package and fabricating method thereof
TWI825975B (zh) * 2021-09-10 2023-12-11 美商愛玻索立克公司 已清洗的封裝用基板的製造方法以及已清洗的封裝用基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1499590A (zh) * 2002-11-05 2004-05-26 �¹������ҵ��ʽ���� 半导体器件及其制造方法
US20070013064A1 (en) * 2005-07-15 2007-01-18 Shinko Electric Industries Co., Ltd. Semiconductor device and electronic apparatus
CN101159261A (zh) * 2006-10-04 2008-04-09 新光电气工业株式会社 半导体器件及其制造方法
US20110114377A1 (en) * 2008-06-03 2011-05-19 Jean Brun Stacked electronic device and method of making such an electronic device
CN103208487A (zh) * 2012-01-13 2013-07-17 台湾积体电路制造股份有限公司 用于较薄堆叠封装件结构的方法和装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
JP3975194B2 (ja) 2003-12-02 2007-09-12 株式会社フジクラ パッケージの製造方法
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US20080136004A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US8587129B2 (en) 2009-07-31 2013-11-19 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via base and method of manufacture thereof
US20110147908A1 (en) 2009-12-17 2011-06-23 Peng Sun Module for Use in a Multi Package Assembly and a Method of Making the Module and the Multi Package Assembly
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
JP2012079734A (ja) 2010-09-30 2012-04-19 Teramikros Inc 半導体装置及び半導体デバイス並びにそれらの製造方法
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
KR20120048991A (ko) * 2010-11-08 2012-05-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8941222B2 (en) * 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9412689B2 (en) 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
TWI508249B (zh) 2012-04-02 2015-11-11 矽品精密工業股份有限公司 封裝件、半導體封裝結構及其製法
JP6038517B2 (ja) 2012-07-13 2016-12-07 新光電気工業株式会社 配線基板及びその製造方法
US9735087B2 (en) * 2012-09-20 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level embedded heat spreader
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1499590A (zh) * 2002-11-05 2004-05-26 �¹������ҵ��ʽ���� 半导体器件及其制造方法
US20070013064A1 (en) * 2005-07-15 2007-01-18 Shinko Electric Industries Co., Ltd. Semiconductor device and electronic apparatus
CN101159261A (zh) * 2006-10-04 2008-04-09 新光电气工业株式会社 半导体器件及其制造方法
US20110114377A1 (en) * 2008-06-03 2011-05-19 Jean Brun Stacked electronic device and method of making such an electronic device
CN103208487A (zh) * 2012-01-13 2013-07-17 台湾积体电路制造股份有限公司 用于较薄堆叠封装件结构的方法和装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216298A (zh) * 2018-08-10 2019-01-15 华进半导体封装先导技术研发中心有限公司 一种扇出型芯片封装结构及其制造方法

Also Published As

Publication number Publication date
EP3108499A1 (en) 2016-12-28
EP3108499B1 (en) 2021-09-08
JP2017505999A (ja) 2017-02-23
US10971476B2 (en) 2021-04-06
WO2015126638A1 (en) 2015-08-27
US20150235991A1 (en) 2015-08-20

Similar Documents

Publication Publication Date Title
CN106030791A (zh) 具有金属桩互连的底部封装
CN102770957B (zh) 模穿孔聚合物块封装
TWI445144B (zh) 堆疊晶圓級封裝與相關製造方法
DE112012002506B4 (de) Mikroelektronische Vorrichtung, Stapelchippackung und Rechnersystem, das diese enthält, Verfahren zur Herstellung eines Mehrfachkanalkommunikationsweges in dieser und Verfahren zum Ermöglichen einer elektrischen Kommunikation zwischen Komponenten einer Stapelchippackung
KR102385549B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
DE102019117027A1 (de) Halbleiter-package und verfahren für dessen bildung
DE102015113085A1 (de) Umverteilungsleitungen mit gestapelten Durchkontaktierungen
DE102019128460A1 (de) Halbleiterpackages und verfahren für deren herstellung
US10497659B2 (en) Double plated conductive pillar package substrate
TW201448700A (zh) 在芯片和基板之間的新型端接和連接
SE537874C2 (sv) CTE-anpassad interposer och metod att tillverka en sådan
CN105140213A (zh) 一种芯片封装结构及封装方法
DE102019118492A1 (de) Eingebettete spannungsreglerstruktur undverfahren zum bilden derselben
DE102018110872B3 (de) Integrierte Fan-Out-Package und deren Ausbildungsverfahren
CN106328604A (zh) 芯片封装
US9583365B2 (en) Method of forming interconnects for three dimensional integrated circuit
DE102013106271A1 (de) Verfahren zur Herstellung einer Chipkapselung, Verfahren zur Herstellung einer Wafer-Level-Kapselung, Chipkapselung und Wafer-Level-Kapselung
US20230384684A1 (en) Method for removing resistor layer, and method of manufacturing semiconductor
DE102020115150B4 (de) Giga-interposer-integration durch chip-on-wafer-on-substrat und verfahren zur bildung von chip-on-wafer-on-substrate-paketen
DE102020124229A1 (de) Halbleitervorrichtung und verfahren
CN106328624A (zh) 制造具有多层囊封的传导基板的半导体封装的方法及结构
CN112397445B (zh) Tsv导电结构、半导体结构及制备方法
CN105789171A (zh) 具有预定义通孔图案的电子封装及制作和使用其的方法
US8258009B2 (en) Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof
CN103337463A (zh) 一种铜柱微凸点结构的制作方法及其结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20161012

RJ01 Rejection of invention patent application after publication