TW201448700A - 在芯片和基板之間的新型端接和連接 - Google Patents
在芯片和基板之間的新型端接和連接 Download PDFInfo
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- TW201448700A TW201448700A TW103107147A TW103107147A TW201448700A TW 201448700 A TW201448700 A TW 201448700A TW 103107147 A TW103107147 A TW 103107147A TW 103107147 A TW103107147 A TW 103107147A TW 201448700 A TW201448700 A TW 201448700A
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Abstract
一種將芯片貼附至基板的方法,所述基板具有外層,所述外層包括嵌入在如阻焊層的電介質中的通孔柱,所述通孔柱的端部與所述電介質齊平,所述方法包括以下步驟:(o)任選地移除有機清漆,(p)將包括端接有焊料凸點的引腳的芯片定位為接觸所述通孔柱的暴露端部,和(q)加熱熔融所述焊料凸點並使所述通孔的端部被焊料潤濕。
Description
本發明涉及端接互連結構以及在芯片和基板之間的連接。
在對於越來越複雜的電子元件的小型化需求越來越大的帶動下,諸如計算機和電信設備等消費電子產品的集成度越來越高。這已經導致要求支撐結構如IC基板和IC插件具有通過介電材料彼此電絕緣的高密度的多個導電層和通孔。
這種支撐結構的總體要求是可靠性和適當的電氣性能、薄度、剛度、平整度、散熱性好和有競爭力的單價。
在實現這些要求的各種途徑中,一種廣泛實施的創建層間互連通孔的製造技術是采用激光鑽孔,所鑽出的孔穿透後續布設的介電基板直到最後的金屬層,後續填充金屬,通常是銅,該金屬通過鍍覆技術沈積在其中。這種成孔方法有時也被稱為“鑽填”,由此產生的通孔可稱為“鑽填通孔”。
但是,鑽填孔方法存在大量缺點。因為每個通孔需要單獨鑽孔,所以生產率受限,並且製造複雜的多通孔IC基板和插件的成本變得高昂。在大型陣列中,通過鑽填方法難以生產出高密度和高品質、彼此緊密相鄰且具有不同的尺寸和形狀的通孔。此外,激光鑽出的通孔具有穿過
介電材料厚度的粗糙側壁和內向錐度。該錐形減小了通孔的有效直徑。特別是在超小通孔直徑的情況下,也可能對於在先的導電金屬層的電接觸產生不利影響,由此導致可靠性問題。而且,在被鑽的電介質是包括聚合物基質中的玻璃或陶瓷纖維的複合材料時,側壁特別粗糙,並且這種粗糙度可能會導致產生雜散電感。
鑽出的通孔的填充過程通常是通過銅電鍍來完成的。在鑽出的孔中進行電鍍可能會導致凹痕,其中在通孔端部出現小坑。或者,當通孔通道被填充超過其容納量的銅時,可能造成溢出,從而產生突出超過周圍材料的半球形上表面。凹痕和溢出往往在如製造高密度基板和插件時所需的後續上下堆疊通孔時造成困難。此外,應該認識到,大的通孔通道難以均勻填充,特別是在其位於插件或IC基板設計的同一互連層內的小通孔附近時。
雖然可接受的尺寸和可靠性範圍正在隨著時間的推移而改善,但是上文所述的缺點是鑽填技術的內在缺陷,並且會限制可製造的通孔的尺寸範圍。還應該注意的是,激光鑽孔是製造圓形通孔通道的最好方法。雖然理論上可以通過激光銑削製造狹縫形狀的通孔通道,但是,實際上可製造的鑽填孔的幾何形狀範圍比較有限,並且在給定支撐結構中的通孔通常是圓柱形的並且基本相同。
通過鑽填工藝製造通孔是昂貴的,並且難以利用相對具有成本效益的電鍍工藝用銅來均勻和一致地填充由此形成的通孔通道。
在複合介電材料中激光鑽出的通孔實際上被限制在60×
10-6m的最小直徑,並且由於所涉及的燒蝕過程以及所鑽的複合材料的性質,甚至因此而遭受到顯著的錐度形狀以及粗糙側壁的不利影響。
除了上文所述的激光鑽孔的其它限制外,鑽填技術的另一限制在於難以在同一層中產生不同直徑的通孔,這是因為當鑽出不同尺寸的通孔通道並隨後用金屬填充以製造不同尺寸通孔時,通孔通道的填充速率不同。因此,作為鑽填技術的特征性的凹痕或溢出的典型問題被惡化,因為不可能對不同尺寸通孔同時優化沈積技術。
克服鑽填方法的許多缺點的可選解決方案是利用又稱為“圖案鍍覆(pattern plating)”的技術,通過將銅或其它金屬沈積到在光刻膠中形成的圖案內來製造。
在圖案鍍覆中,首先沈積種子層。然後在其上沈積光刻膠層,隨後曝光形成圖案,並且選擇性移除該圖案以制成暴露出種子層的溝槽。通過將銅沈積到光刻膠溝槽中來形成通孔柱。然後移除剩余的光刻膠,蝕刻掉種子層,並在其上及其周圍層壓通常為聚合物浸漬玻璃纖維氈的介電材料,以包圍所述通孔柱。然後,可以使用各種技術和工藝來減薄所述介電材料,將其一部分移除並暴露出所述通孔柱端部以允許由此導電接地,用於在其上構建下一金屬層。可在其上通過重複該過程來沈積後續的金屬導體層和通孔柱,以形成所需的多層結構。
在一個替代但緊密關聯的技術即下文所稱的“面板鍍覆(panel plating)”中,將連續的金屬層或合金層沈積到基板上。在基板端部沈積光刻膠層,並在其中顯影出圖案。剝除顯影光刻膠的圖案,選擇性
地暴露出其下的金屬,該金屬可隨後被蝕刻掉。未顯影的光刻膠保護其下方的金屬不被蝕刻掉,並留下直立的特征結構和通孔的圖案。
在剝除未顯影的光刻膠後,在所述直立的銅特征結構和/或通孔柱上及其周圍可以層壓介電材料,如聚合物浸漬玻璃纖維氈。在平坦化後,可以通過重複上述過程在其上沈積後續的金屬導體層和通孔柱以構建所需的多層結構。
通過上述圖案鍍覆或面板鍍覆方法創建的通孔層通常被稱為銅制的“通孔柱”和特徵層。
應該認識到,微電子演化的一般推動力涉及製造更小、更薄、更輕和更大功率的高可靠性產品。使用厚且有芯的互連不能得到超輕薄的產品。為了在互連IC基板或“插件”中形成更高密度的結構,需要具有甚至更小連接的更多層。事實上,有時希望在彼此的端部上堆疊元件。
如果在銅或其它合適的犧牲基板上鍍覆沈積層壓結構,則可以蝕刻掉基板,留下獨立的無芯層壓結構。可以在預先附著在犧牲基板上的側面上沈積其它層,由此能夠形成雙面累積,從而最大限度地減少翹曲並有助於實現平坦化。
一種製造高密度互連的靈活技術是構建由在介電基質中的具有各種幾何形狀和形式的金屬通孔或通孔柱特徵結構構成的圖案或面板鍍覆多層結構。所述金屬可以是銅,所述電介質可以是纖維增強聚合物,通常使用的是具有高玻璃化轉變溫度(Tg)的聚合物,例如聚酰亞胺。這些互連可以是有芯的或無芯的,並可包括用於堆疊元件的空腔。它們可具
有奇數或偶數層,並且所述通孔可具有非圓形形狀。實現技術描述在授予Amitec-Advanced Multilayer Interconnect Technologies Ltd.的現有專利中。
例如,赫爾維茨(Hurwitz)等人的題為“先進多層無芯支撐結構及其製造方法(Advanced multilayer coreless support structures and method for their fabrication)”的美國專利US 7,682,972描述了一種製造包括在電介質中的通孔陣列的獨立膜的方法,所述膜用作構建優異的電子支撐結構的前體。該方法包括以下步驟:在包圍犧牲載體的電介質中製造導電通孔膜,和將所述膜與犧牲載體分離以形成獨立的層壓陣列。基於該獨立膜的電子基板可通過將所述層壓陣列減薄和平坦化,隨後端接通孔來形成。該公報通過引用全文並入本文。
赫爾維茨(Hurwitz)等人的題為“用於芯片封裝的無芯空腔基板及其製造方法(Coreless cavity substrates for chip packaging and their fabrication)”的美國專利US 7,669,320描述了一種製造IC支撐體的方法,所述IC支撐體用於支撐與第二IC芯片串聯的第一IC芯片;所述IC支撐體包括在絕緣周圍材料中的銅特徵結構和通孔的交替層的堆疊,所述第一IC芯片可粘合至所述IC支撐體,所述第二IC芯片可粘合在所述IC支撐體內部的空腔中,其中所述空腔是通過蝕刻掉銅基座和選擇性蝕刻掉累積的銅而形成的。該公報通過引用全文並入本文。
赫爾維茨(Hurwitz)等人的題為“集成電路支撐結構及其製造方法(integrated circuit support structures and their fabrication)”的美國專利US 7,635,641描述了一種製造電子基板的方法,包括以下步驟:(A)選
擇第一基礎層;(B)將第一蝕刻阻擋層沈積到所述第一基礎層上;(C)形成交替的導電層和絕緣層的第一半堆疊體,所述導電層通過貫穿絕緣層的通孔而互連;(D)將第二基礎層施加到所述第一半堆疊體上;(E)將光刻膠保護塗層施加到第二基礎層上;(F)蝕刻掉所述第一基礎層;(G)移除所述光刻膠保護塗層;(H)移除所述第一蝕刻阻擋層;(I)形成交替的導電層和絕緣層的第二半堆疊體,導電層通過貫穿絕緣層的通孔而互連;其中所述第二半堆疊體具有與第一半堆疊體基本對稱的構造;(J)將絕緣層施加到交替的導電層和絕緣層的所述第二半堆疊體上;(K)移除所述第二基礎層,以及,(L)通過將通孔末端暴露在所述堆疊體的外表面上並對其施加端子來端接基板。該公報通過引用全文並入本文。
在美國專利US7,682,972、US 7,669,320和US 7,635,641中描述的通孔柱技術適合大規模生產,同時電鍍極大數目的通孔。如上所述,現有技術的鑽填通孔具有約60微米的最小有效直徑。與之對比的是,利用光刻膠和電鍍的通孔柱技術能夠獲得更高密度的通孔。通孔直徑可以小到30微米,並且可以在同一層內共同製造不同幾何形狀和尺寸的通孔。
隨著時間的推移,期望鑽填技術和通孔柱沈積技術二者均能夠製造進一步微型化並且具有更高密度的通孔和特徵結構的基板。然而,似乎通孔柱技術的開發有可能保持競爭優勢。
基板能夠實現芯片與其它元件的連接。芯片必須接合至基板上,從而提供可靠的電連接以實現芯片與基板之間的電通信。
將基板與芯片互連的高密度引線技術之一是成熟的“倒裝
芯片技術”,其中在芯片端接焊盤上生長焊料凸點(bump)、無鉛焊料凸點或在其端部具有焊料或無鉛焊料的銅凸點,然後將芯片倒裝與基板上表面焊盤上的凸點以互連。隨著芯片凸點和引腳變得越來越密集,先進基板常常配備有自身輔助與芯片凸點互連的凸點。在基板焊盤上的這種凸點也稱為“SoP”(焊盤上焊料)凸點,通常由焊料或無鉛焊料構成。它們通常通過模板印刷並隨後回流焊或者通過化學鍍或電鍍工藝並隨後回流焊施加至基板端接焊盤上。
當芯片凸點與SoP凸點通過回流焊接觸時,SoP凸點的焊料有助於產生與芯片凸點的可靠的機械及電接觸。如果沒有SoP,則芯片凸點的焊料可能不足或者可能不能充分流動和潤濕基板端接焊盤的整個表面,由此造成可靠性風險或甚至是在芯片與基板之間斷開連接。這種擔憂尤為必要,因為大部分基板具有阻焊外保護層,其本來就鋪展在端接基板焊盤上由此遮蔽這些焊盤使得難以在沒有SoP凸點的情況下接觸這些焊盤。
在現有技術中熟知的是芯片凸點的尺寸和間距必須與SoP凸點的尺寸和間距盡可能對準。隨著芯片技術的不斷發展,芯片變得越來越密集,因為需要甚至更高的接觸密度,使得連接凸點也變得甚至更為密集。由此,在基板上施加SoP凸點也變得甚至更加具有挑戰性。與前期基板製造步驟相比,施加SoP本來就是一個更低良品率的制程,並且它是基板製造中的最終工藝步驟之一,由此增加了廢品率、返工率、測試和成本。此外,下一代SoP凸點的間距越微細,則在回流焊之後和芯片組裝期間相
鄰凸點之間發生短路故障的可能性就越高,從而進一步降低良品率並增加整體封裝成本。
隨著柱尺寸的縮減,保持各個引線彼此電絕緣以防止短路變得越來越困難。焊接也變得複雜,焊料過少會導致部分連接斷開,而焊料過多則存在導致附近連接短路的風險。
本發明的實施方案解決了這些問題。
需要發現一種在基板端接焊盤與倒裝芯片凸點之間進行互連的新結構。該新結構要求具有當前可製造的SoP凸點結構所達到的高良品率,較少間距限制以及較低單位成本。
新結構要求確保具有低或有限體積焊料的更細間距的倒裝芯片凸點仍能夠可靠地直接連接基板端接焊盤。
期望該技術在基板上導體表面上使用低成本的現有阻焊溶液結構,而且該結構與銅端接焊盤具有基本相同的水平,以允許焊料易於進入和流動至這些焊盤上。
還期望發現一種能夠支撐具有非圓形焊盤端子的端接倒裝芯片基板焊盤的技術,以有助於在這些焊盤與倒裝芯片凸點之間創造更大的接觸面積以及有助於在基板面受到該焊盤限制的基板區域上進行導體布線。
本發明的實施方案涉及一種多層複合電子結構,包括至少一對在X-Y平面內延伸的特徵層,每個相鄰對的特徵層由內通孔層隔開,
所述通孔層包括在垂直於X-Y平面的Z方向上連接相鄰特徵層的通孔柱,所述通孔柱嵌入在內電介質層中,所述多層複合電子結構還包括由嵌入在外介電材料中的外通孔柱層構成的端子,其被減薄以暴露出外通孔柱層的端部。
通常,暴露的外通孔柱層與倒裝芯片凸點可互聯。
優選地,嵌入在外介電材料中的具有暴露端部的減薄的外通孔柱層是基本平坦的。
通常,嵌入在外介電材料中的具有暴露端部的減薄的外通孔柱層具有小於3微米的粗糙度。
任選地,所述通孔柱利用可焊接金屬通過回流焊連接至所述倒裝芯片凸點。
作為替代方案,所述通孔柱通過Z-導電各向異性粘接材料連接至所述倒裝芯片凸點。
在一些實施方案中,所述通孔柱或下方端接焊盤中的至少其一的形狀不是圓形。
在一些實施方案中,所述通孔柱或下方端接焊盤中的至少其一的形狀選自橢圓形、正方形、矩形和長方形。
通常,所述外介電層包括聚合物。
任選地,所述外介電層包括阻焊層。
任選地,所述外通孔柱包括銅。
在一些實施方案中,發送給用戶的所述多層複合電子結構
還包括施加在所述外通孔柱的暴露端部上的有機清漆,用以防止通孔柱金屬氧化。
在一些實施方案中,發送給用戶的所述多層複合電子結構具有端接金或鎳的外通孔柱,以防其氧化。
任選地,至少一個外層通孔柱具有小於50微米的直徑。
任選地,至少一個外層通孔柱具有小於40微米的直徑。
任選地,至少一個外層通孔柱具有30微米或30微米以下的直徑。
任選地,所述多層複合電子結構在Z方向上的厚度超過50微米。
任選地,端接焊盤層和至少一個外通孔柱層可通過包括以下步驟的方法製造:(a)獲得基板,所述基板包括經處理暴露出銅的下方通孔柱層;(b)用種子層覆蓋所述基板;(c)在所述種子層上施加第一光刻膠層;(d)曝光和顯影所述光刻膠以形成端接焊盤的負性圖案;(e)在所述負性圖案中沈積金屬以製造特徵層;(f)剝除所述第一光刻膠層;(g)施加第二光刻膠層;(h)曝光和顯影出負性圖案,在所述負性圖案中包括多個外通孔柱;(i)在所述負性圖案中沈積金屬層;(j)剝除所述第二光刻膠,留下所述特徵層和直立的多個外通孔柱;(k)移除所述種子層;(l)在外通孔層中的所述多個通孔柱上層壓介電材料;
(m)平坦化所述介電材料以暴露出所述多個通孔柱的端部。
在一些實施方案中,所述介電材料層是阻焊層。
在一些實施方案中,施加以下限制條件中至少其一:(i)所述種子層包括銅;(ii)所述金屬層包括銅;(iii)所述介電材料包括聚合物;(iv)所述介電材料還包括陶瓷或玻璃內含物。
在一些實施方案中,所述方法還包括附加步驟(n1)在所述外通孔柱層中的銅柱的暴露端部上施加有機清漆。
在其它實施方案中,所述方法還包括附加步驟(n2)在所述外通孔柱層中的銅通孔柱的暴露端部上沈積鎳或金。
在一個替代方法中,所述至少一個外通孔柱層通過以下步驟製造:(i)獲得基板,所述基板包括暴露出銅的下方特徵層;(ii)用種子層覆蓋所述基板;(iii)在所述種子層上沈積金屬層;(iv)在所述金屬層上施加光刻膠層;(v)曝光和顯影出外通孔柱的正性圖案;(vi)蝕刻掉暴露的所述金屬層;(vii)剝除所述光刻膠,留下直立在所述外通孔層中的多個通孔柱;(viii)移除所述種子層;(xi)在所述外層中的所述多個通孔柱上層壓外介電材料;(x)平坦化並減薄,以暴露出所述外通孔柱層的金屬。
在一些實施方案中,施加以下限制條件至少其一:(a)所述種子層包括銅;(b)所述通孔柱層包括銅;(c)所述外介電材料包括聚合物;(d)所述外介電材料包括阻焊層。
在一些實施方案中,所述方法還包括步驟(x)a在所述通孔柱的暴露端部上沈積清漆。
在其它實施方案中,所述方法還包括步驟(x)b在所述外通孔柱的暴露端部上沈積金或鎳。
第三方面涉及一種將芯片貼附至基板的方法,所述基板具有外層,所述外層包括嵌入在電介質中的通孔柱,所述通孔柱的端部與所述電介質齊平,所述方法包括以下步驟:(p)將包括端接有焊料凸點的引腳的芯片定位為接觸所述通孔柱的暴露端部;(q)加熱熔融所述焊料凸點並使所述外通孔的端部被焊料潤濕。
任選地,所述方法還包括預備步驟(o)移除有機清漆以暴露出所述銅通孔柱的端部。
一種將芯片貼附至基板的替代方法,所述基板具有外層,所述外層包括嵌入在電介質中的通孔柱,所述通孔柱的端部與所述電介質齊平,所述方法包括以下步驟:(p)將具有端接有Z方向各向異性導電膜的引腳的芯片定位為接觸所述基板的通孔柱的暴露端部;(q)在Z方向上施加壓力。
術語微米或μm是指微米或10-6米。
100、101‧‧‧芯片
102‧‧‧銅凸點、端子、凸點
103‧‧‧焊盤
104‧‧‧鈍化層
105‧‧‧頂部、凸點、芯片、焊料
200‧‧‧基板
202‧‧‧阻焊層、介電材料、電介質
204‧‧‧特徵層
205‧‧‧介電材料
206‧‧‧通孔層、通孔、內通孔柱層
208‧‧‧基板焊盤、焊盤層、端接焊盤、通孔柱、端子
208a‧‧‧通孔柱
208b‧‧‧通孔柱
210‧‧‧SoP凸點
218‧‧‧清漆
220‧‧‧鎳或金
300‧‧‧基板
306‧‧‧銅端接柱陣列、銅端接柱、柱、外通孔柱層、外通孔層
圖1是現有技術的多層複合支撐結構的簡化截面圖,該結構具有連接至基板上端接焊盤的SoP凸點,還示出具有對應焊料凸點的芯片,該焊料凸點定位為用於與倒裝芯片連接。
圖2是具有用於接收圖1芯片的新基板端接結構的圖1基板的示意性截面圖。
圖3是示出可由此製造本發明的結構的一種方法的第一流程圖。
圖4是示出可由此製造本發明的結構的一種變化方法的第二流程圖。
圖5是示出可由此將芯片貼附在基板結構上的方法的流程圖。
不同附圖中的相同附圖標記和指示表示相同的要素。
為了更好地理解本發明並示出本發明的實施方式,純粹以舉例的方式參照附圖進行參考描述。
具體參照附圖時,必須強調的是特定的圖示是示例性的並且目的僅在於說明性地討論本發明的優選實施方案,並且基於提供被認為是對於本發明的原理和概念方面的描述最有用和最易於理解的圖示的原因而被呈現。就此而言,沒有試圖將本發明的結構細節以超出對本發明基本理解所必需的詳細程度來圖示;參照附圖的說明使本領域技術人員認識到本發明的幾種形式可如何實際體現出來。
在以下說明中,涉及的是包括在介電基質中的金屬通孔的支撐結構,特別是在聚合物基質中的銅通孔柱,所述聚合物基質例如是玻璃纖維增強的聚酰亞胺、環氧樹脂或BT(雙馬來酰亞胺/三嗪)樹脂或它
們的共混物。
Access公司的光刻膠及圖案或面板鍍覆以及層壓技術的特徵是可以製造包括具有非常多通孔柱的基板的非常大陣列的大面板,如在赫爾維茨(Hurwitz)等人的美國專利US 7,682,972,US 7,669,320和US 7,635,641中所描述的,這些文件通過引用並入本文。這種面板是基本平坦和基本光滑的。
Access公司的技術的另一特徵在於利用光刻膠通過電鍍制成的通孔可以比通過鑽填形成的通孔更窄。目前,最窄的鑽填通孔為約60微米。利用光刻膠通過電鍍,可實現低於50微米,甚至小至30微米的分辨率。
圖1示出包括芯片101自身的端接芯片100,在其端接焊盤103上配置有銅凸點102並且具有保護性鈍化層104。銅凸點102具有焊料或無鉛焊料頂部105,其備用於通過回流焊與基板200的SoP凸點210接觸。現有技術的基板200通常包括特徵層204,特徵層204通過通孔層206連接,包封在通常為玻璃纖維增強聚合物的介電材料205中,並且終止於被阻焊層202彼此隔離絕緣的大量端接基板焊盤208。提供連接基板焊盤208的SoP凸點210。當芯片凸點105接觸SoP凸點210並且在回流焊過程中被加熱時,SoP凸點205的焊料與芯片凸點105一起熔化並生成可靠的粘接和電子接觸。
在通孔通過鑽填技術製造時,通孔通常具有基本圓形的截面,因為它們首先是在電介質中鑽出激光孔的。由於電介質是非均勻的和各向異性的並且由具有無機填料和玻璃纖維增強體的聚合物基質構成,所
以其圓形截面通常具有粗糙邊緣,並且其截面可能略微偏離真正的圓形形狀。此外,通孔趨於具有一定的錐度,成為逆截頭圓錐,而不是圓柱形。最後,可得到的最窄通孔具有約60微米的直徑。但是,預期隨著時間的推移,該尺寸將縮減,從而實現更加微型化和更密集的封裝。如美國專利US 7,682,972,US 7,669,320和US 7,635,641中所述,例如,圖1的基板200的主結構或者可以通過在光刻膠中顯影的圖案內鍍覆(圖案鍍覆)製造,或者通過面板鍍覆接著選擇性蝕刻來製造,任何一種方法均會留下直立的通孔柱,然後在其上層壓介電材料。為了便於加工和滿足剛度要求,所用的用於製造內通孔層的電介質可為由用聚合物基質浸漬的玻璃纖維織造束構成的預浸料。
利用“鑽填通孔”的方法,由於截面控制和形狀方面的困難,使得不能製造非圓形孔。由於激光鑽孔的限制,還存在約50-60微米直徑的最小通孔尺寸。這些困難在上文的背景技術部分中作了詳細描述,並且這些困難特別涉及由於銅通孔填充電鍍過程導致的凹痕和/或半球形頂部、由於激光鑽孔過程導致的通孔錐度形狀和側壁粗糙、以及由於在“布線模式(routing mode)”中用以產生在聚合物/玻璃電介質中的溝槽而使用的用於銑削狹縫的昂貴的激光鑽孔機所導致的較高成本。
除了前文所述的激光鑽孔的其它限制外,鑽填技術的另一限制在於難以在同一層中產生不同直徑的通孔,這是因為當鑽出不同尺寸的通孔通道然後用金屬填充以製造不同尺寸通孔時,通孔通道是以不同的速率被填充的。因此,作為鑽填技術特徵的凹痕或溢出(圓頂)的典型問
題被惡化,因為不可能同時對不同尺寸通孔來優化沈積技術。因此,在實際應用中,鑽填通孔具有基本圓形截面,盡管由於基板的不均勻特性導致有時略微變形,並且所有通孔具有基本相同的截面。
此外,應該注意的是,在複合介電材料如聚酰亞胺/玻璃或環氧樹脂/玻璃或BT(雙馬來酰亞胺/三嗪)樹脂/玻璃或它們與陶瓷和/或其它填料顆粒的共混物中的激光鑽出的通孔實際上被限於約60×10-6米直徑的最小尺寸,即使如此,由於所鑽的複合材料的特性而導致存在顯著的錐度形狀以及側壁粗糙,這均為所涉及的剝蝕過程的結果。
利用鍍覆和光刻膠技術的靈活性,已經發現可以成本有效地製造出形狀和尺寸範圍廣泛的通孔。此外,可以在同一層中製造出不同形狀和尺寸的通孔。這在使用銅圖案鍍覆方法時尤其有利,通過首先沈積金屬種子層,接著沈積光刻膠材料並在其中顯影光滑、筆直,無錐度的溝槽,隨後在通過在暴露的種子層上圖案鍍覆而得的這些溝槽中沈積銅來填充這些溝槽。與鑽填通孔方法相反的是,通孔柱技術使得光刻膠層中的溝槽被填充從而得到無凹痕、無圓頂的銅連接器。在銅沈積後,隨後剝除光刻膠,然後移除金屬種子層並在其上和其周圍施加一個永久的電介質。由此產生的“通孔導體”結構可使用在赫爾維茨(Hurwitz)等人的美國專利US 7,682,972,US 7,669,320和US 7,635,641中描述的工藝流程。
利用電鍍,已經實現了直徑約30微米的微通孔。微通孔之間的間隔可小於20微米。鑽填技術不允許製造這麽小的通孔,現有技術中對於鑽填通孔而言存在約60微米直徑的有效下限。
任選地,如現有技術那樣,各個通孔可具有在X-Y平面內基本圓形的截面。此外,因為通孔柱是通過在光刻膠中鍍覆並隨後在其周圍施加電介質制成,所以可以通過電鍍技術實現比鑽填技術可得到的光滑得多的通孔,因為在鑽填技術中電介質的非均勻性和各向異性會導致粗糙表面的孔。
然而,與鑽填技術產生的通孔不同,通過鍍覆方式製造的通孔不必是圓形的。通孔可以在X-Y平面內不對稱。例如,它們在X-Y平面的第一方向上延伸量可以是在垂直於第一方向的X-Y平面的第二方向上的延伸量的至少3倍,並且更加線性。
鑒於鑽填通孔由於凹痕和圓頂效應而被有效地限制在約60微米直徑,在通過電鍍形成通孔的一些實施方案中,至少一個通孔具有小於50微米的直徑,可能小於40微米。事實上,在一些實施方案中,至少一個通孔可具有30微米或30微米以下的直徑。
通過將通孔柱嵌入電介質中並且抛光以暴露出通孔柱的端部,可以獲得表面粗糙度小於3微米的基本平坦的陣列。
端接焊盤208可具有更細的間距(pitch),但是這使得將其與芯片進行精確連接變得更具挑戰性。
參照圖2,示出圖1的芯片100以及基板300和二者的連接對準。
基板300包括通過通孔206連接在一起的銅特徵層204,與基板200比照基本相似。應當認識到,基板200的內層數目、通孔和特徵結構
密度可以極大地變化。所示的基板300具有2個內特徵層和3個通孔堆,只是用於圖示目的的簡化示意圖。
接著描述有利於進一步微型化並且具有高可靠性、良好的良品率和較少浪費的新型端接結構和方法。通常通過在光刻膠中進行圖案電鍍或者通過利用下述方法面板電鍍然後蝕刻掉多余材料來製造銅端接柱陣列306。接著在銅端接柱306上方和周圍布設阻焊層202,並且將阻焊層202和銅端接柱306結構抛光平坦,暴露出柱306的頂部。可以采用機械、化學或化學機械抛光(CMP)。利用CMP可以實現基本光滑、平坦並且在整個陣列上起伏變化小於3微米的表面處理。
銅柱306的暴露頂部可用有機清漆218覆蓋,有機清漆218可用合適的有機溶劑移除,該有機溶劑溶解清漆218,但不溶解阻焊層202。作為替代方案,銅柱306外層暴露的銅可用鎳或金220塗覆。
通過將端接芯片100的焊料凸點105與銅柱306連接,焊料用量最小。然而,主要是因為用於暴露出通孔306的外層端部的減薄工藝所致的基本平坦和光滑,使得所形成的焊接連接極為可靠。並且與圖1所示的現有技術相比,可以實現在低短路和斷路概率下具有高可靠性和良好的良品率。
參照圖3,在一些實施方案中,至少一個外通孔層通過包括以下步驟的方法製造:獲得基板,所述基板包括經處理暴露出銅的下方通孔層206’-步驟(a);和用種子層(通常是銅)覆蓋所述基板-步驟(b)。在所述種子層上施加第一光刻膠薄層-步驟(c);以及曝光和顯影所
述第一光刻膠薄層以形成特徵結構的負性圖案-步驟(d)。在所述特徵結構的負性圖案中沈積金屬,通常是銅-步驟(e)以形成焊盤層208;以及剝除所述第一光刻膠薄層-步驟(f),留下直立的焊盤層208。接著,施加第二光刻膠厚層-步驟(g)以及在其中曝光和顯影出通孔柱306的第二負性圖案-步驟(h)。在所述第二圖案中顯影出的溝槽內沈積金屬層,通常是銅-步驟(i);以製造包括通孔柱306的外通孔柱層。應該注意的是,各個通孔柱306可具有彼此不同的尺寸。此外,它們的截面不必是圓形的,而可以是例如橢圓形、正方形或矩形。這種靈活性能夠實現高封裝密度。
剝除所述第二光刻膠層-步驟(j),留下直立的外通孔柱層306和下方的焊盤層208;移除暴露的種子層-步驟(k)。這可以通過將結構暴露於濕蝕刻過程來完成,例如采用氫氧化銨或氯化銅。隨後,在外通孔柱層306上沈積阻焊層材料-步驟(l)。
沈積外通孔柱層306的方法基本類似於對內通孔柱層206所使用的方法,其中為了進一步積層和提高剛性,介電材料通常是複合材料,其包含聚合物基質例如聚酰亞胺、環氧樹脂、雙馬來酰亞胺樹脂、三嗪樹脂及其共混物並且還包含陶瓷或玻璃。通常,用於基板200的內層的電介質提供為織造纖維束浸漬在含陶瓷填料的聚合物樹脂預浸料中構成的預浸料。至於外層,可以使用較廉價的材料,例如阻焊層202。可將阻焊層202或其它介電材料減薄以暴露出外通孔柱306的金屬端部-步驟(m)。該減薄可利用機械研磨或抛光、化學抛光或化學機械抛光(CMP)完成。該減薄也使得基板200的外表面平坦化。
製造成型通孔的設備由於允許形成正方形、矩形或橢圓形的通孔端部和端接焊盤而能夠實現更高的封裝密度。這可以在具有更高的X-Y平面封裝密度的同時,允許在Z(穿過基板)方向上沿著這些通孔306進行導體布線。
端接芯片100可焊接至外通孔柱306的暴露銅端部上。由於銅易於氧化,所以為了運輸和儲存,外通孔柱306端部暴露的銅可用有機清漆218覆蓋-步驟(n1),有機清漆218可用合適的有機溶劑移除,該有機溶劑溶解清漆218,但不溶解阻焊層202。作為替代方案,外通孔層306暴露的銅可用鎳或金220塗覆-步驟(n2)。
參照圖4,在一個變化的製造方法中,外通孔端接柱層306可通過以下步驟製造:獲得基板,所述基板包括經平坦化而暴露出銅的下方通孔柱層206-步驟(i),接著用種子層覆蓋下方通孔層206-步驟(ii),其通常為銅並且通常通過濺射或化學鍍沈積。在所述種子層上沈積金屬層-步驟(iii)。該金屬層通常為銅並且可通過電鍍沈積。在所述金屬層上施加光刻膠層-步驟(iv),然後在其中曝光和顯影出端接焊盤208的正性圖案-步驟(v)。蝕刻掉暴露的所述金屬層-步驟(vi)。蝕刻銅可利用銅蝕刻劑例如氫氧化銨或氯化銅進行。接著,剝除所述光刻膠-步驟(vii),留下直立的通孔層,然後在端接焊盤層208上層壓介電材料202-步驟(viii)。介電材料202可以是預浸料,但是為了降低成本,也可以是例如簡單聚合物或阻焊層。
可以減薄介電層202-步驟(ix)以暴露出端接焊盤208的表
面,例如利用化學或機械抛光或研磨或化學機械抛光。該減薄也使端接焊盤層208平坦化。
可以重複步驟(i)~(ix)以在端接焊盤208上沈積通孔柱306用以連接端接芯片105的端子102。
作為替代方案,端接焊盤可以制作得更厚。
由於銅易於氧化,所以為了運輸和儲存,暴露的銅可用有機清漆218覆蓋-步驟(x)a,有機清漆218可用合適的溶劑移除,保留阻焊層216。作為替代方案,暴露的銅可用鎳或金220塗覆-步驟(x)b。如下文參照圖5所述,芯片100可焊接至外通孔層306暴露的銅上。
現在參照圖2~5,描述一種將芯片100貼附至基板300的方法,基板300具有外層,該外層包括嵌入在電介質202(通常是阻焊層)中的通孔柱208,通孔柱208的端部與電介質202齊平該方法包括以下步驟:(o)如果提供了防止通常為銅的通孔柱208氧化的有機清漆218,則移除有機清漆218;(p)將包括端接有焊料凸點的引腳102的端接芯片100定位為接觸通孔208的暴露端部;和(q)加熱熔融焊料凸點105並使通孔208的端部被焊料潤濕。
由於利用化學、機械或化學機械抛光暴露出外層的通孔208的端部,所以基板300的整個陣列基本平坦並且可以光滑至粗糙度小於3微米。這有利於僅在端接芯片100的芯片引腳102上使用微凸點105進行焊接,因為基板300的平坦性使得不接觸的風險很小。因為只需要非常少的焊料,所以相鄰通孔柱208a、208b之間短路的風險被降到最低。
由此,可以形成具有直徑小於60微米的端子208的基板300,
目前直徑可以為30微米。芯片100可以利用最小量的焊料105焊接至這些端子208上。
事實上,可以利用Z-導電各向異性粘接材料,完全不使用焊料,將芯片100的倒裝芯片凸點102連接至通孔柱208。
各向異性導電膜(通常稱為ACF)是一種無鉛的環境友好型粘接體系,其已在平板顯示器工業中使用超過30年,用以製造驅動電子器件與顯示器的玻璃基板之間的電連接和機械連接。
玻璃上芯片(COG)應用現在通常以間距小至25微米間隔10微米方式使用ACF,而各向異性的柔性薄膜上芯片(aCOF)已經穩定在40微米間距範圍,成為一種標准技術。這些驅動器芯片中的單獨一個可具有超過1300個焊盤,它們在ACF組裝工藝中均同時互連。與COG和aCOF相比,aCOB(各向異性的板上芯片)組裝仍不成熟。然而,它們已經在堅固且成本敏感的封裝需要高密度和低剖面特徵的應用中在過去數年取得了長足的進展。
上述說明只是以解釋性的方式提供。應當認識到本發明能夠具有多種變化形式。
已經描述了本發明的若幹實施方案。然而,應當理解的是,可以進行各種改變而不偏離本發明的實質和範圍。因此,其它實施方案也在所附請求項書的範圍之內。
因此,本領域技術人員將會認識到,本發明不限於上文中具體圖示和描述的內容。而且,本發明的範圍由所附請求項限定,包括上文所述的各個技術特徵的組合和子組合以及其變化和改進,本領域技術人員在閱讀前述說明後將會預見到這樣的組合、變化和改進。
在請求項書中,術語“包括”及其變體例如“包含”、“含有”等是指所列舉的要素被包括在內,但一般不排除其它要素。
100‧‧‧芯片
102‧‧‧銅凸點、端子、凸點
103‧‧‧焊盤
104‧‧‧鈍化層
105‧‧‧頂部、凸點、芯片、焊料
202‧‧‧阻焊層、介電材料、電介質
204‧‧‧特徵層
205‧‧‧介電材料
206‧‧‧通孔層、通孔、內通孔柱層
208‧‧‧基板焊盤、焊盤層、端接焊盤、通孔柱、端子
218‧‧‧有機清漆
220‧‧‧鎳或金
300‧‧‧基板
306‧‧‧銅柱
Claims (29)
- 一種多層複合電子結構,包括至少一對在X-Y平面內延伸的特徵層,每個相鄰對的特徵層由內通孔層間隔開,所述通孔層包括在垂直於X-Y平面的Z方向上連接相鄰特徵層的通孔柱,所述通孔柱嵌入在內層電介質中,所述多層複合電子結構還包括由嵌入在外介電材料中的外通孔柱層構成的端子,其被減薄以暴露出外通孔柱層的端部。
- 如請求項1所述的多層複合電子結構,其中暴露的外通孔柱層與倒裝芯片凸點可互連。
- 如請求項1所述的多層複合電子結構,其中嵌入在外介電材料中的具有暴露端部的減薄的外通孔柱層是基本平坦的。
- 如請求項3所述的多層複合電子結構,其中嵌入在外介電材料中的具有暴露端部的減薄的外通孔柱層具有小於3微米的粗糙度。
- 如請求項2所述的多層複合電子結構,其中所述通孔柱利用可焊接金屬通過回流焊連接至所述倒裝芯片凸點。
- 如請求項2所述的多層複合電子結構,其中所述通孔柱通過Z-導電各向異性粘接材料連接至所述倒裝芯片凸點。
- 如請求項2所述的多層複合電子結構,其中所述通孔柱或下方端接焊盤中的至少其一的形狀不是圓形。
- 如請求項7所述的多層複合電子結構,其中所述通孔柱或下方端接焊盤中的至少其一的形狀選自橢圓形、正方形、矩形和長方形。
- 如請求項1所述的多層複合電子結構,其中所述外介電層包括聚合物。
- 如請求項1所述的多層複合電子結構,其中所述外介電層包括阻焊層。
- 如請求項1所述的多層複合電子結構,其中所述外通孔柱包括銅。
- 如請求項1所述的多層複合電子結構,還包括施加在所述外通孔柱的暴露端部上的有機清漆,用以防止通孔柱金屬氧化。
- 如請求項1所述的多層複合電子結構,其中所述外通孔柱端接金或鎳以防止氧化。
- 如請求項1所述的多層複合電子結構,其中至少一個外層通孔柱 具有小於50微米的直徑。
- 如請求項1所述的多層複合電子結構,其中至少一個外層通孔柱具有小於40微米的直徑。
- 如請求項1所述的多層複合電子結構,其中至少一個外層通孔柱具有30微米或30微米以下的直徑。
- 如請求項1所述的多層複合電子結構,其中所述多層複合電子結構在Z方向上的厚度超過50微米。
- 如請求項1所述的多層複合電子結構,其中端接焊盤層和至少一個外通孔柱層可通過包括以下步驟的方法製造:(a)獲得基板,所述基板包括經處理暴露出銅的下方通孔柱層;(b)用種子層覆蓋所述基板;(c)在所述種子層上施加第一光刻膠層;(d)曝光和顯影所述光刻膠以形成端接焊盤的負性圖案;(e)在所述負性圖案中沈積金屬以製造特徵層;(f)剝除所述第一光刻膠層;(g)施加第二光刻膠層;(h)曝光和顯影出負性圖案,在所述負性圖案中包括多個外通孔柱;(i)在所述負性圖案中沈積金屬層;(j)剝除所述光刻膠,留下所述特徵層和直立的多個外通孔柱;(k)移除所述種子層;(l)在外通孔層中的所述多個通孔柱上層壓介電材料;(m)平坦化所述介電材料以暴露出所述多個通孔柱的端部。
- 如請求項18所述的多層複合電子結構,其中所述介電層是阻焊層。
- 如請求項18所述的多層複合電子結構,其中施加以下限制條件中的至少其一:(i)所述種子層包括銅;(ii)所述金屬層包括銅;(iii)所述介電材料包括聚合物;(iv)所述介電材料還包括陶瓷或玻璃內含物。
- 如請求項18所述的多層複合電子結構,其中所述方法包括附加步驟:(n1)在所述外通孔柱層中的銅柱的暴露端部上施加有機清漆。
- 如請求項18所述的多層複合電子結構,其中所述方法包括附加步驟:(n2)在所述外通孔柱層中的銅通孔柱的暴露端部上沈積鎳或金。
- 如請求項1所述的多層複合電子結構,其中所述至少一個外通孔柱層通過以下步驟製造:(i)獲得基板,所述基板包括暴露出銅的下方特徵層;(ii)用種子層覆蓋所述基板;(iii)在所述種子層上沈積金屬層;(iv)在所述金屬層上施加光刻膠層;(v)曝光和顯影出外通孔柱的正性圖案;(vi)蝕刻掉暴露的所述金屬層;(vii)剝除所述光刻膠層,留下直立在所述外通孔層中的多個通孔柱;(viii)移除所述種子層;(xi)在所述外層中的所述多個通孔柱上層壓外介電材料;(x)平坦化並減薄,以暴露出所述外通孔柱層的金屬。
- 如請求項23所述的多層複合電子結構,其中施加以下限制條件中的至少其一:(a)所述種子層包括銅;(b)所述通孔層包括銅;(c)所述外介電材料包括聚合物;(d)所述外介電材料包括阻焊層。
- 如請求項23所述的多層複合電子結構,其中所述方法還包括步驟:(x)a在所述通孔柱的暴露端部上沈積清漆。
- 如請求項23所述的多層複合電子結構,其中所述方法還包括步驟:(x)b在所述外通孔柱的暴露端部上沈積金或鎳。
- 一種將芯片貼附至基板的方法,所述基板具有外層,所述外層包 括嵌入在電介質中的通孔柱,所述通孔柱的端部與所述電介質齊平,所述方法包括以下步驟:(p)將包括端接有焊料凸點的引腳的芯片定位為接觸所述通孔柱的暴露端部;(q)加熱熔融所述焊料凸點並使所述外通孔的端部被焊料潤濕。
- 如請求項27所述的方法,還包括預備步驟(0)移除有機清漆以暴露出所述銅通孔柱的端部。
- 一種將芯片貼附至基板的方法,所述基板具有外層,所述外層包括嵌入在電介質中的通孔柱,所述通孔柱的端部與所述電介質齊平,所述方法包括以下步驟:(p)將具有端接有Z方向各向異性導電膜的引腳的芯片定位為接觸所述通孔柱的暴露端部;(q)在Z方向上施加壓力。
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