JP2016529729A - 半導体ダイおよびパッケージジグソーサブマウント - Google Patents
半導体ダイおよびパッケージジグソーサブマウント Download PDFInfo
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- JP2016529729A JP2016529729A JP2016537425A JP2016537425A JP2016529729A JP 2016529729 A JP2016529729 A JP 2016529729A JP 2016537425 A JP2016537425 A JP 2016537425A JP 2016537425 A JP2016537425 A JP 2016537425A JP 2016529729 A JP2016529729 A JP 2016529729A
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- submount
- jigsaw
- recess
- contact
- motherboard
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Abstract
Description
Claims (22)
- 絶縁材料から形成され、比較的狭い縁部面と、第1および第2の比較的大きな正面の面とを有する平坦な基板と、
縁部面に沿って形成される少なくとも1つの凹部と、
前記少なくとも1つの凹部の各々の特定の面に形成される導電材料の層と、
半導体デバイスとの電気接点を形成するように構成される前記第1の正面の面上の第1の複数のソルダリングパッドと、
各々が前記第1の複数のソルダリングパッドにおける特定のソルダリングパッドを前記少なくとも1つの凹部の特定の凹部の導電材料の層に電気接続する導電接続部と、
を備える、半導体デバイスを外部回路に接続するためのサブマウント。 - 前記導電接続部が前記第1の正面の面上に導電トレースを備える、請求項1に記載のサブマウント。
- 前記導電接続部が、前記平坦な基板の内部に位置決めされた内部導体を備える、請求項1または2に記載のサブマウント。
- 半導体デバイスとの電気接点を形成するように構成された前記第2の正面の面上の第2の複数のソルダリングパッドを備える、請求項1から3のいずれかに記載のサブマウント。
- 各々が前記第2の正面の面上の前記第2の複数のソルダリングパッドの特定のソルダリングパッドを前記少なくとも1つの凹部の特定の凹部の面に形成された導電材料の層に電気接続する導電接続部を備える、請求項4に記載のサブマウント。
- 前記第2の正面の面上のソルダリングパッドに電気接続された前記導電接続部が、前記第2の正面の面上の導電トレースを備える、請求項5に記載のサブマウント。
- 前記第2の正面の面上のソルダリングパッドに電気接続された前記導電接続部が、前記平坦な基板の内部に位置決めされた内部導体を備える、請求項5または6に記載のサブマウント。
- 前記少なくとも1つの凹部の特定の凹部が円形の凹面を有する、前記請求項のいずれかに記載のサブマウント。
- 前記少なくとも1つの凹部の特定の凹部の凹面が、ポリライン凹面である、前記請求項のいずれかに記載のサブマウント。
- 特定の凹部の凹面の少なくとも一部における角度が、前記第1および第2の正面の面の特定の正面の面に対して鋭角に角度が付けられる、前記請求項のいずれかに記載のサブマウント。
- 前記サブマウントの縁部面の特定の領域が、前記第1および第2の正面の面の特定の正面の面に対して鋭角に角度が付けられる、前記請求項のいずれかに記載のサブマウント。
- 前記縁部面が、第1および第2のカット面を備えるカット面が刻まれた面である、請求項11に記載のサブマウント。
- 前記第2のカット面の特定の領域が、導電材料の層によって覆われる、請求項12に記載のサブマウント。
- 前記基板が、前記第2のカット面にある導電材料の層との電気接点を形成する内部導体を備える、請求項13に記載のサブマウント。
- 前記基板が、前記第2のカット面にある導電材料の層との電気接点を形成しない内部導体を備える、請求項13に記載のサブマウント。
- 前記第2のカット面が、前記第1および第2の正面の面の両面に対して90°に配向される、請求項12から15のいずれかに記載のサブマウント。
- 鋭角に角度が付けられた前記縁部面の領域が、第2のカット面である、請求項12から15のいずれかに記載のサブマウント。
- 2つの正面の面を有する絶縁基板と、
導電材料から前記基板の正面の面上に形成され、前記サブマウント上の凹部の導電層に電気接続されるように構成される接触ランドと、
を備え、前記請求項のいずれかに記載のサブマウントを設置することができるマザーボード。 - 前記基板の正面の面内に形成された凹部を備え、前記正面の面内の凹部が、前記サブマウントに設置された半導体デバイスを収容するように寸法が決められる、請求項18に記載のマザーボード。
- 前記正面の面内の凹部が、前記マザーボードの前記基板内に底面を有するブラインド凹部である、請求項19に記載のマザーボード。
- 前記半導体デバイスの作動によって生成される熱を消散させるように構成された材料の層を備える、請求項20に記載のマザーボード。
- 前記正面の面内の凹部が、前記マザーボードの基板を貫通する、請求項19に記載のマザーボード。
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PCT/IL2013/050730 WO2015029004A1 (en) | 2013-08-28 | 2013-08-28 | Semiconductor die and package jigsaw submount |
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WO2023017632A1 (ja) * | 2021-08-10 | 2023-02-16 | ヌヴォトンテクノロジージャパン株式会社 | 半導体レーザ装置、はんだ付きサブマウント、はんだ付き集合サブマウント、及び、半導体レーザ装置の検査方法 |
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CN105430897B (zh) * | 2015-12-29 | 2018-09-04 | 广东欧珀移动通信有限公司 | 电路板及移动终端 |
FR3049155B1 (fr) * | 2016-03-15 | 2018-04-13 | Alstom Transport Technologies | Carte electronique comprenant un circuit intercalaire a demi-trous metallises |
DE102017215048A1 (de) * | 2017-08-29 | 2019-02-28 | Conti Temic Microelectronic Gmbh | Schaltungsträger für Leistungselektronik und Leistungselektronikmodul mit einem Schaltungsträger |
TWI647581B (zh) * | 2017-11-22 | 2019-01-11 | 緯創資通股份有限公司 | 電路板以及佈局結構 |
US11294435B2 (en) * | 2018-12-14 | 2022-04-05 | Dell Products L.P. | Information handling system high density motherboard |
CN112672498A (zh) * | 2020-12-11 | 2021-04-16 | 中国北方发动机研究所(天津) | 一种贴片式电路板 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04304659A (ja) * | 1991-04-01 | 1992-10-28 | Nec Corp | 混成集積回路装置 |
JPH07135290A (ja) * | 1993-09-14 | 1995-05-23 | Toshiba Corp | マルチチップモジュール |
JPH08139220A (ja) * | 1994-11-04 | 1996-05-31 | Ibiden Co Ltd | リードレスチップキャリア及びその製造方法 |
JPH118445A (ja) * | 1997-06-18 | 1999-01-12 | Toyota Motor Corp | 回路基板 |
JPH11121641A (ja) * | 1997-10-08 | 1999-04-30 | Nec Corp | 半導体装置及びその製造方法 |
JP2002299782A (ja) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | 回路基板 |
JP2003163101A (ja) * | 2001-11-28 | 2003-06-06 | Kyocera Corp | 複合電子部品 |
JP2009099816A (ja) * | 2007-10-18 | 2009-05-07 | Panasonic Corp | 半導体装置とその製造方法および半導体装置の実装方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5631898B2 (ja) * | 1974-01-11 | 1981-07-24 | ||
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
JPH0823149A (ja) * | 1994-05-06 | 1996-01-23 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US5811879A (en) * | 1996-06-26 | 1998-09-22 | Micron Technology, Inc. | Stacked leads-over-chip multi-chip module |
TW456004B (en) * | 1998-02-10 | 2001-09-21 | Nissha Printing | Substrate sheet for semiconductor module, method and apparatus for manufacturing the same |
JP2001077301A (ja) * | 1999-08-24 | 2001-03-23 | Amkor Technology Korea Inc | 半導体パッケージ及びその製造方法 |
US6545868B1 (en) * | 2000-03-13 | 2003-04-08 | Legacy Electronics, Inc. | Electronic module having canopy-type carriers |
US6713854B1 (en) * | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
US6693358B2 (en) * | 2000-10-23 | 2004-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
US6830959B2 (en) * | 2002-01-22 | 2004-12-14 | Fairchild Semiconductor Corporation | Semiconductor die package with semiconductor die having side electrical connection |
US6842585B2 (en) * | 2002-04-18 | 2005-01-11 | Olympus Optical Co., Ltd. | Camera |
JP3896029B2 (ja) * | 2002-04-24 | 2007-03-22 | 三洋電機株式会社 | 混成集積回路装置の製造方法 |
US7250352B2 (en) * | 2002-04-24 | 2007-07-31 | Sanyo Electric Co., Ltd. | Methods for manufacturing a hybrid integrated circuit device |
CN100413070C (zh) * | 2004-01-30 | 2008-08-20 | 松下电器产业株式会社 | 部件内置模块、配备部件内置模块的电子设备以及部件内置模块的制造方法 |
US7258549B2 (en) * | 2004-02-20 | 2007-08-21 | Matsushita Electric Industrial Co., Ltd. | Connection member and mount assembly and production method of the same |
JP2006209068A (ja) * | 2004-12-28 | 2006-08-10 | Sony Corp | 光導波路、光導波路モジュール及び光導波路モジュールの製造方法 |
KR20080003802A (ko) * | 2005-04-15 | 2008-01-08 | 로무 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
US7919717B2 (en) * | 2005-08-19 | 2011-04-05 | Honeywell International Inc. | Three-dimensional printed circuit board |
CN101405084B (zh) * | 2006-03-20 | 2011-11-16 | 皇家飞利浦电子股份有限公司 | 用于电子微流体设备的系统级封装台 |
JP5148849B2 (ja) * | 2006-07-27 | 2013-02-20 | スタンレー電気株式会社 | Ledパッケージ、それを用いた発光装置およびledパッケージの製造方法 |
US7952183B2 (en) * | 2007-10-29 | 2011-05-31 | Kabushiki Kaisha Toshiba | High capacity memory with stacked layers |
US7829977B2 (en) * | 2007-11-15 | 2010-11-09 | Advanced Semiconductor Engineering, Inc. | Low temperature co-fired ceramics substrate and semiconductor package |
JP5108496B2 (ja) * | 2007-12-26 | 2012-12-26 | 三洋電機株式会社 | 回路基板およびその製造方法、回路装置およびその製造方法 |
JP5193837B2 (ja) * | 2008-03-21 | 2013-05-08 | 株式会社東芝 | 半導体メモリカード |
KR101429722B1 (ko) * | 2008-07-28 | 2014-09-25 | 삼성전자주식회사 | 적층된 칩들을 갖는 전자 장치 형성 방법 |
CN103329255A (zh) * | 2011-01-18 | 2013-09-25 | 富士电机株式会社 | 反向阻断型半导体元件的制造方法 |
-
2013
- 2013-08-28 GB GB1519493.9A patent/GB2532869A/en not_active Withdrawn
- 2013-08-28 CN CN201380078827.8A patent/CN106663673A/zh active Pending
- 2013-08-28 JP JP2016537425A patent/JP2016529729A/ja active Pending
- 2013-08-28 US US14/428,376 patent/US9831144B2/en active Active
- 2013-08-28 WO PCT/IL2013/050730 patent/WO2015029004A1/en active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04304659A (ja) * | 1991-04-01 | 1992-10-28 | Nec Corp | 混成集積回路装置 |
JPH07135290A (ja) * | 1993-09-14 | 1995-05-23 | Toshiba Corp | マルチチップモジュール |
JPH08139220A (ja) * | 1994-11-04 | 1996-05-31 | Ibiden Co Ltd | リードレスチップキャリア及びその製造方法 |
JPH118445A (ja) * | 1997-06-18 | 1999-01-12 | Toyota Motor Corp | 回路基板 |
JPH11121641A (ja) * | 1997-10-08 | 1999-04-30 | Nec Corp | 半導体装置及びその製造方法 |
JP2002299782A (ja) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | 回路基板 |
JP2003163101A (ja) * | 2001-11-28 | 2003-06-06 | Kyocera Corp | 複合電子部品 |
JP2009099816A (ja) * | 2007-10-18 | 2009-05-07 | Panasonic Corp | 半導体装置とその製造方法および半導体装置の実装方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023017632A1 (ja) * | 2021-08-10 | 2023-02-16 | ヌヴォトンテクノロジージャパン株式会社 | 半導体レーザ装置、はんだ付きサブマウント、はんだ付き集合サブマウント、及び、半導体レーザ装置の検査方法 |
Also Published As
Publication number | Publication date |
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CN106663673A (zh) | 2017-05-10 |
WO2015029004A1 (en) | 2015-03-05 |
GB2532869A (en) | 2016-06-01 |
US20160163610A1 (en) | 2016-06-09 |
GB201519493D0 (en) | 2015-12-16 |
US9831144B2 (en) | 2017-11-28 |
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