JP2016213464A - 積層パッケージ素子およびその製造方法 - Google Patents
積層パッケージ素子およびその製造方法 Download PDFInfo
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- JP2016213464A JP2016213464A JP2016093765A JP2016093765A JP2016213464A JP 2016213464 A JP2016213464 A JP 2016213464A JP 2016093765 A JP2016093765 A JP 2016093765A JP 2016093765 A JP2016093765 A JP 2016093765A JP 2016213464 A JP2016213464 A JP 2016213464A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000007789 sealing Methods 0.000 claims abstract description 51
- 238000007639 printing Methods 0.000 claims abstract description 5
- 238000010146 3D printing Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910010293 ceramic material Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000012778 molding material Substances 0.000 claims description 4
- 239000002861 polymer material Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 36
- 239000004065 semiconductor Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
10a 第1のプリントヘッド
10b 第2のプリントヘッド
20 3D印刷
100 第1の基板
102 第1のボンディングパッド
110 第2の基板
112 第2のボンディングパッド
120 封止層
122 ボンディングワイヤ
122a 第1部分
122b 第2部分
200、200’ 積層パッケージ素子
300 方法
Claims (13)
- 積層パッケージ素子の製造方法であって、
複数の第2のボンディングパッドを含む第2の基板を、複数の第1のボンディングパッドを含む第1の基板上に接着し、
3次元(3D)印刷を実行し、前記第1の基板と前記第2の基板を被覆する封止層を形成し、複数のボンディングワイヤを封止層内に形成し、各ボンディングワイヤは、前記複数の第1のボンディングパッドの中の1つに接続された第1部分を含む積層パッケージ素子の製造方法。 - 前記封止層は、成形材料、セラミック材料、ポリマー材料、樹脂材料、または誘電材料を含む請求項1に記載の積層パッケージ素子の製造方法。
- 前記複数のボンディングワイヤは、金、銀、銅、アルミニウム、または他の合金を含む請求項1に記載の積層パッケージ素子の製造方法。
- 各ボンディングワイヤは、複数の第2のボンディングパッドの中の1つに接続される第2部分を含む請求項1に記載の積層パッケージ素子の製造方法。
- 前記ボンディングワイヤの前記第1部分と前記第2部分は、互いに接続され、前記封止層によって完全に被覆される請求項4に記載の積層パッケージ素子の製造方法。
- 前記ボンディングワイヤの前記第1部分と前記第2部分は、互いに分離され、前記封止層から露出された一端をそれぞれ有する請求項4に記載の積層パッケージ素子の製造方法。
- 3D印刷を実行するように用いられる3Dプリンタは、少なくとも2つのプリンタヘッドを有し、3D印刷の間に少なくとも2つの異なる材料が同時に形成される請求項1に記載の積層パッケージ素子の製造方法。
- 複数の第1のボンディングパッドを有する第1の基板、
前記第1の基板上に接着され、複数の第2のボンディングパッドを有する第2の基板、
前記第1の基板と前記第2の基板を被覆する封止層、および
前記封止層内にある複数のボンディングワイヤを含み、
各ボンディングワイヤは、前記複数の第1のボンディングパッドの中の1つに接続された第1部分を含み、前記封止層および前記複数のボンディングワイヤは、3D印刷に用いられる材料で形成される積層パッケージ素子。 - 前記封止層は、成形材料、セラミック材料、ポリマー材料、樹脂材料、または誘電材料を含む請求項8に記載の積層パッケージ素子。
- 前記複数のボンディングワイヤは、金、銀、銅、アルミニウム、または他の合金を含む請求項8に記載の積層パッケージ素子。
- 各ボンディングワイヤは、複数の第2のボンディングパッドの中の1つに接続される第2部分を含む請求項8に記載の積層パッケージ素子。
- 前記ボンディングワイヤの前記第1部分と前記第2部分は、互いに接続され、前記封止層によって完全に被覆される請求項11に記載の積層パッケージ素子。
- 前記ボンディングワイヤの前記第1部分と前記第2部分は、互いに分離され、前記封止層から露出された一端をそれぞれ有する請求項11に記載の積層パッケージ素子。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510230568.7 | 2015-05-08 | ||
CN201510230568.7A CN106206331B (zh) | 2015-05-08 | 2015-05-08 | 堆叠封装装置及其制造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2016213464A true JP2016213464A (ja) | 2016-12-15 |
JP6254217B2 JP6254217B2 (ja) | 2017-12-27 |
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JP2016093765A Active JP6254217B2 (ja) | 2015-05-08 | 2016-05-09 | 積層パッケージ素子およびその製造方法 |
Country Status (3)
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US (1) | US9881901B2 (ja) |
JP (1) | JP6254217B2 (ja) |
CN (1) | CN106206331B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10147660B2 (en) | 2011-10-27 | 2018-12-04 | Global Circuits Innovations, Inc. | Remapped packaged extracted die with 3D printed bond connections |
US10177054B2 (en) | 2011-10-27 | 2019-01-08 | Global Circuit Innovations, Inc. | Method for remapping a packaged extracted die |
US10128161B2 (en) * | 2011-10-27 | 2018-11-13 | Global Circuit Innovations, Inc. | 3D printed hermetic package assembly and method |
US9870968B2 (en) | 2011-10-27 | 2018-01-16 | Global Circuit Innovations Incorporated | Repackaged integrated circuit and assembly method |
WO2020123308A1 (en) * | 2018-12-14 | 2020-06-18 | Yazaki Corporation | Additive manufacturing techniques for producing a network of conductive pathways on a substrate |
CN112136212B (zh) * | 2019-04-24 | 2022-07-29 | 深圳市汇顶科技股份有限公司 | 芯片互联装置、集成桥结构的基板及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158352A (ja) * | 2005-12-07 | 2007-06-21 | Samsung Electro Mech Co Ltd | 配線基板の製造方法及び配線基板 |
JP2007214238A (ja) * | 2006-02-08 | 2007-08-23 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2008258611A (ja) * | 2007-03-30 | 2008-10-23 | Xerox Corp | インクジェット印刷によるワイヤ層、封止層及び遮蔽層の形成方法 |
WO2014209994A2 (en) * | 2013-06-24 | 2014-12-31 | President And Fellows Of Harvard College | Printed three-dimensional (3d) functional part and method of making |
WO2015041189A1 (ja) * | 2013-09-17 | 2015-03-26 | 東レエンジニアリング株式会社 | 多層配線基板の製造方法及びこれに用いる三次元造形装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007027287A (ja) * | 2005-07-14 | 2007-02-01 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7564137B2 (en) * | 2006-04-27 | 2009-07-21 | Atmel Corporation | Stackable integrated circuit structures and systems devices and methods related thereto |
TWI414048B (zh) * | 2008-11-07 | 2013-11-01 | Advanpack Solutions Pte Ltd | 半導體封裝件與其製造方法 |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US9935028B2 (en) | 2013-03-05 | 2018-04-03 | Global Circuit Innovations Incorporated | Method and apparatus for printing integrated circuit bond connections |
CN202394859U (zh) * | 2011-11-29 | 2012-08-22 | 日月光半导体(上海)股份有限公司 | 半导体封装构造 |
CN103327741B (zh) * | 2013-07-04 | 2016-03-02 | 江俊逢 | 一种基于3d打印的封装基板及其制造方法 |
US9099575B2 (en) | 2013-07-16 | 2015-08-04 | Cree, Inc. | Solid state lighting devices and fabrication methods including deposited light-affecting elements |
US9818665B2 (en) * | 2014-02-28 | 2017-11-14 | Infineon Technologies Ag | Method of packaging a semiconductor chip using a 3D printing process and semiconductor package having angled surfaces |
CN103942530A (zh) * | 2014-03-03 | 2014-07-23 | 孙立民 | 一种具有防伪功能的指纹感应装置 |
WO2016111512A1 (en) * | 2015-01-09 | 2016-07-14 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
-
2015
- 2015-05-08 CN CN201510230568.7A patent/CN106206331B/zh active Active
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- 2016-02-04 US US15/015,919 patent/US9881901B2/en active Active
- 2016-05-09 JP JP2016093765A patent/JP6254217B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158352A (ja) * | 2005-12-07 | 2007-06-21 | Samsung Electro Mech Co Ltd | 配線基板の製造方法及び配線基板 |
JP2007214238A (ja) * | 2006-02-08 | 2007-08-23 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2008258611A (ja) * | 2007-03-30 | 2008-10-23 | Xerox Corp | インクジェット印刷によるワイヤ層、封止層及び遮蔽層の形成方法 |
WO2014209994A2 (en) * | 2013-06-24 | 2014-12-31 | President And Fellows Of Harvard College | Printed three-dimensional (3d) functional part and method of making |
WO2015041189A1 (ja) * | 2013-09-17 | 2015-03-26 | 東レエンジニアリング株式会社 | 多層配線基板の製造方法及びこれに用いる三次元造形装置 |
Also Published As
Publication number | Publication date |
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US20160329305A1 (en) | 2016-11-10 |
US9881901B2 (en) | 2018-01-30 |
JP6254217B2 (ja) | 2017-12-27 |
CN106206331A (zh) | 2016-12-07 |
CN106206331B (zh) | 2019-02-01 |
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