CN110858573A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN110858573A
CN110858573A CN201910784507.3A CN201910784507A CN110858573A CN 110858573 A CN110858573 A CN 110858573A CN 201910784507 A CN201910784507 A CN 201910784507A CN 110858573 A CN110858573 A CN 110858573A
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China
Prior art keywords
chip
pad
semiconductor chip
semiconductor
wiring
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Pending
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CN201910784507.3A
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English (en)
Inventor
李赛别
孙由京
李承鲁
韩元吉
韩昊秀
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN110858573A publication Critical patent/CN110858573A/zh
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

提供了一种半导体封装件。半导体封装件包括：包括至少一个接合焊盘的安装衬底；第一半导体芯片，其设置在安装衬底上，并且包括第一半导体芯片的上表面上的第一突起；第一间隔球，其电连接至第一半导体芯片；第一凸球，其电连接至第一间隔球；以及第一布线，其将第一凸球和接合焊盘电连接，而不接触第一突起，其中第一布线包括在远离接合焊盘的方向上延伸的第一部分和在接近接合焊盘的方向上延伸的第二部分。

Description

半导体封装件
相关申请的交叉引用
本申请要求于2018年8月24日提交的韩国专利申请No.10-2018-0099332的优先权，该申请的公开内容以引用方式整体并入本文中。
技术领域
根据本发明构思的示例性实施例的设备和方法涉及一种包括折叠环(foldedloop)和普通环(normal loop)的半导体封装件。
背景技术
近来，半导体芯片在需要实现高性能元件的同时其尺寸有所增加。此外，为了满足半导体封装件的多功能化和高容量，开发了一种多芯片半导体封装件，其中多个半导体芯片堆叠在一个封装件中。
然而，随着使用半导体封装件的电子装置的细薄化，半导体封装件的尺寸趋于减小。为了满足这种电子装置尺寸缩小的趋势，正在对能够减小半导体封装件尺寸的方法进行各种研究。
发明内容
本发明构思的各个实施例提供了一种提高产品可靠性的小型化半导体封装件。
然而，本发明构思不限于本文所述的这些实施例，相反，通过参照这些实施例的详细描述，各种其它实施例对于本发明构思所属领域的普通技术人员将变得清楚。
根据本发明构思的一些实施例，提供了一种半导体封装件，该半导体封装件可包括：包括至少一个接合焊盘的安装衬底；第一半导体芯片，其设置在安装衬底上，并且包括第一半导体芯片的上表面上的第一突起；第一间隔球，其电连接至第一半导体芯片；第一凸球，其电连接至第一间隔球；以及第一布线，其将第一凸球和接合焊盘电连接，而不接触第一突起，其中第一布线包括在远离接合焊盘的方向上延伸的第一部分和在接近接合焊盘的方向上延伸的第二部分。
根据本发明构思的一些实施例，提供了一种半导体封装件，该半导体封装件可包括：至少一个接合焊盘；第一半导体芯片，其包括连接至接合焊盘的第一芯片焊盘和从第一芯片焊盘的上表面突出的第一突起；第一芯片焊盘上的第一间隔球；第一间隔球上的第一凸球；第一布线，其将第一凸球与接合焊盘连接，而不接触第一突起；第二半导体芯片，其设置在第一半导体芯片上，并且包括连接至接合焊盘的第二芯片焊盘和从第二芯片焊盘的上表面突出的第二突起；第二凸球，其直接连接至第二芯片焊盘；以及第二布线，其将第二凸球和接合焊盘连接，而不接触第二突起，其中第一布线包括在远离接合焊盘的方向上延伸的第一部分和在接近接合焊盘的方向上延伸的第二部分，并且第二布线不在远离接合焊盘的方向上延伸。
根据本发明构思的一些实施例，提供了一种半导体封装件，该半导体封装件可包括：包括至少一个接合焊盘的安装衬底；第一半导体芯片，其设置在安装衬底上，并且包括第一芯片焊盘和从第一芯片焊盘突出的第一突起；第二半导体芯片，其设置在第一半导体芯片上，并且包括第二芯片焊盘和从第二芯片焊盘的上表面突出的第二突起；第三半导体芯片，其设置在第二半导体芯片上，并且包括第三芯片焊盘和从第三芯片焊盘的上表面突出的第三突起；以及第一布线、第二布线和第三布线，其将第一芯片焊盘、第二芯片焊盘和第三芯片焊盘分别连接至接合焊盘，其中第二布线通过设置在第二芯片焊盘上的第二间隔球和设置在第二间隔球上的第二凸球连接至第二芯片焊盘，其中第一芯片焊盘和第三芯片焊盘不在竖直方向上与第二半导体芯片重叠，其中第二芯片焊盘在竖直方向上与第一半导体芯片和第三半导体芯片重叠，并且其中第二布线包括在远离接合焊盘的方向上延伸的第一部分，和在接近接合焊盘的方向上延伸的第二部分。
附图说明
通过参照附图详细描述本发明构思的示例性实施例，本发明构思的以上和其它方面和特征将变得更加清楚，其中：
图1是示出根据一些实施例的半导体封装件的示意图；
图2是用于描述包括根据一些实施例的半导体芯片区的晶圆的示意图；
图3A和图3B是用于解释根据一些实施例的形成半导体芯片的突起的处理的示意图；
图4是根据一些实施例的按照放大方式示出图1的区A的放大图；
图5是示出其中根据一些实施例的半导体芯片竖直地堆叠的半导体封装件的示意图；
图6是示出根据一些实施例的半导体封装件的示意图；
图7是示出根据一些实施例的半导体封装件的示意图；以及
图8至图16是用于解释根据一些实施例的制造半导体封装件的方法的中间阶段图。
具体实施方式
本文提供的实施例都是示例性的，不限制本发明构思。以下描述中提供的实施例不排除与也在本文中提供的或者未在本文中提供但是符合本发明构思的另一示例或另一实施例的一个或多个特征相关。例如，除非在描述中另作说明，否则即使在特定示例中描述的内容未在不同的示例中描述，也可理解为所述内容与所述不同示例相关或组合。
应该理解，当元件或层被称作“位于”另一元件或层“上”、“位于”另一元件或层“上方”、“在”另一元件或层“上”、“连接至”或“耦接至”另一元件或层时，其可直接位于另一元件或层上、位于另一元件或层上方、在另一元件或层上、连接至或耦接至另一元件或层，或者可存在中间元件或层。相反，当元件被称作“直接位于”另一元件或层“上”、“直接位于”另一元件或层“上方”、“直接在”另一元件或层“上”、“直接连接至”或“直接耦接至”另一元件或层时，不存在中间元件或层。相同标号始终指代相同元件。如本文所用，术语“和/或”包括相关所列项之一或多个的任何和所有组合。
图1是示出根据一些实施例的半导体封装件的示意图。
参照图1，半导体封装件可包括安装衬底100、第一半导体芯片120a、第一粘合剂膜121、第一间隔球150a、第一凸球160a、第一布线170a和第一模制树脂180。
第一半导体芯片120a可设置在安装衬底100上。第一粘合剂膜121可设置在第一半导体芯片120a与安装衬底100之间。例如，第一半导体芯片120a可通过第一粘合剂膜121固定至安装衬底100。例如，第一粘合剂膜121可为芯片贴附膜(DAF)。
安装衬底100可包括在设置有第一半导体芯片120a的表面上的第一接合焊盘110a。第一半导体芯片120a可包括在与连接至安装衬底100的表面相对的表面上的第一芯片焊盘130a。
第一间隔球150a可设置在第一半导体芯片120a上。例如，第一间隔球150a可连接至第一半导体芯片120a的第一芯片焊盘130a。第一凸球160a可设置在第一间隔球150a上。例如，第一凸球160a可连接至第一间隔球150a。
第一布线170a可将第一半导体芯片120a与安装衬底100电连接。例如，第一布线170a可将第一半导体芯片120a的第一芯片焊盘130a与安装衬底100的第一接合焊盘110a连接，从而将第一半导体芯片120a与安装衬底100电连接。
第一模制树脂180可形成在安装衬底100上以覆盖第一半导体芯片120a、第一粘合剂膜121、第一接合焊盘110a、第一间隔球150a、第一凸球160a和第一布线170a。第一模制树脂180可保护半导体封装件的内部构成元件。例如，第一模制树脂180可防止或减小外部冲击传递至安装衬底100、第一半导体芯片120a、第一粘合剂膜121、第一接合焊盘110a、第一间隔球150a、第一凸球160a和第一布线170a。例如，第一模制树脂180可为环氧模塑料(EMC)，但是实施例不限于此。
根据一些实施例，安装衬底100可为封装衬底，并且可为例如印刷电路板(PCB)、陶瓷衬底等。在安装衬底100的下表面上，也就是说，在与设置有第一半导体芯片120a的安装表面相对的表面上，可形成将半导体封装件电连接至外部装置的外部端子(例如，焊料球或引线框)。第一接合焊盘110a可电连接至外部端子(连接至外部装置)，并且可将电信号供应至第一半导体芯片120a。可替换地，第一接合焊盘110a可为例如接地焊盘，并且可电连接至安装衬底100中的地线。第一接合焊盘110a示为例如设置在安装衬底100的外壳中，但是实施例不限于此。
根据一些实施例，例如，第一半导体芯片120a可为存储器芯片、逻辑芯片等。当第一半导体芯片120a为逻辑芯片时，可以考虑到将被执行的操作而进行各种设计。当第一半导体芯片120a是存储器芯片时，存储器芯片可为例如非易失性存储器芯片。例如，第一半导体芯片120a可为闪速存储器芯片。例如，第一半导体芯片120a可为NAND闪速存储器芯片和NOR闪速存储器芯片之一。然而，根据本发明构思的技术想法的存储器装置的形式不限于此。在一些实施例中，第一半导体芯片120a可为相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)和电阻随机存取存储器(RRAM)之一。
根据一些实施例，第一半导体芯片120a的第一芯片焊盘130a可电连接至第一半导体芯片120a内的半导体元件。因此，第一接合焊盘110a接收到的电信号可通过第一布线170a传输至第一半导体芯片120a的第一芯片焊盘130a。传输至第一半导体芯片120a的第一芯片焊盘130a的电信号可传输至第一半导体芯片120a内的半导体元件。
根据一些实施例，第一半导体芯片120a可包括第一突起140a。第一突起140a可包括从第一半导体芯片的上表面120a_us在竖直方向Z上突出的一部分。在一些附图中，第一突起140a示为从第一半导体芯片的上表面120a_us在竖直方向Z上突出的矩形部分，但是实施例不限于此。例如，第一突起140a可具有诸如三角形或倾斜三角形的各种形状。将参照图2、图3A和图3B描述产生第一半导体芯片120a的第一突起140a的处理。
图2是用于描述包括根据一些实施例的半导体芯片区的晶圆的示意图。图3A和图3B是用于解释形成根据一些实施例的半导体芯片的突起的处理的示意图。
参照图2，晶圆200可包括第一半导体芯片区20和第二半导体芯片区21。例如，第一半导体芯片区20和第二半导体芯片区21可在平面方向X、Y上排列在晶圆200上。切割区22可设置在第一半导体芯片区20与第二半导体芯片区21之间。第一半导体芯片区20和第二半导体芯片区21中的每一个可包括驱动半导体芯片所需的内部电路。
参照图3A和图3B，通过沿着切割区22将第一半导体芯片区20和第二半导体芯片区21分离，可产生对应的半导体芯片(20_芯片、21_芯片)。例如，第一半导体芯片区20和第二半导体芯片区21可基于切割区22在x方向和-x方向上分离。通过将第一半导体芯片区20和第二半导体芯片区21分离形成的半导体芯片(20_芯片、21_芯片)可分别包括突起20_pt、21_pt。此时，可由于构成半导体芯片(20_芯片、21_芯片)的材料的特性而产生突起20_pt、21_pt。可替换地，可由于当将第一半导体芯片区20和第二半导体芯片区21沿着切割区22分离产生的外部应力而产生突起20_pt、21_pt。然而，实施例不限于产生突起20_pt、21_pt的这些原因。除上述原因之外，半导体芯片(20_芯片、21_芯片)中的每一个可由于各种原因包括突起20_pt、21_pt。
再参照图1，例如，第一布线170a可包括金、铜、铝等。第一布线170a可通过例如毛细管形成，但是实施例不限于此。稍后将描述形成第一布线170a的处理的示例。
根据一些实施例，第一布线170a可形成为具有钩形的折叠环。钩形意指包括在远离第一接合焊盘110a的方向上延伸的一部分以及在靠近第一接合焊盘110a的方向上延伸的一部分的形状。折叠环意指与在其中第一布线170a连接至第一凸球160a的一部分相邻的布线具有褶皱形状。为了示出性解释将参照图4提供描述。
图4是按照放大方式示出图1的区A的放大图。
参照图4，第一布线170a可包括在远离第一接合焊盘110a的方向上延伸的第一部分170a1和在靠近第一接合焊盘110a的方向上延伸的第二部分170a2。换句话说，第一布线170a可具有钩形。此外，第一布线170a可具有如下形状：在该形状中与连接至第一凸球160a的部分邻近的部分向下起褶皱。换句话说，第一布线170a可形成为具有钩形的折叠环。
根据一些实施例，由于第一布线170a形成为折叠环，因此第一布线的高度H1可小于一般接合线的高度。在另一半导体芯片竖直地堆叠在第一半导体芯片120a上的情况下，由于第一布线的高度H1小于一般接合线的高度，因此可将更多的芯片堆叠在同一区中。因此，通过将第一布线170a形成为折叠环，半导体封装件可小型化。
根据一些实施例，第一布线170a不与第一半导体芯片120a的第一突起140a接触。当第一布线170a与第一半导体芯片120a的第一突起140a接触时，可能发生第一半导体芯片120a的有缺陷操作。因此，根据一些实施例，通过在第一凸球160a与第一半导体芯片120a的第一芯片焊盘130a之间插入第一间隔球150a，可防止第一布线170a与第一半导体芯片120a的第一突起140a之间短路。第一间隔球150a的高度可基于第一突起140a的高度而改变。
根据一些实施例，由于第一布线170a不与第一半导体芯片120a的第一突起140a接触，因此半导体封装件的可靠性可提高。另外，由于第一布线的高度H1减小，并且更多半导体芯片可堆叠，因此半导体封装件的集成度可提高。
图5是示出其中根据一些实施例的半导体芯片竖直地堆叠的半导体封装件的示意图。
参照图5，根据一些实施例的半导体封装件可包括安装衬底100、第一半导体芯片120a、第二半导体芯片120b、第三半导体芯片120c、第一间隔球150a、第二间隔球150b、第一凸球160a、第二凸球160b、第三凸球160c、第一布线170a、第二布线170b、第三布线170c、第一粘合剂膜121、第二粘合剂膜122、第三粘合剂膜123和模制树脂180。
图5所示的构成元件中的每一个可类似于上述图1的那些。因此，将省略或简单解释重复的描述。根据一些实施例，第一半导体芯片120a可包括第一芯片焊盘130a和从第一半导体芯片的上表面120a_us突出的第一突起140a。第二半导体芯片120b可包括第二芯片焊盘130b和从第二半导体芯片120b的上表面突出的第二突起140b。第三半导体芯片120c可包括第三芯片焊盘130c和从第三半导体芯片120c的上表面突出的第三突起140c。
第一半导体芯片120a可设置在安装衬底100上。例如，第一半导体芯片120a可经第一粘合剂膜121附着于安装衬底100。
第一间隔球150a可连接至第一半导体芯片120a的第一芯片焊盘130a。第一凸球160a可连接至第一间隔球150a。第一布线170a可连接至第一凸球160a和第一接合焊盘110a。换句话说，第一芯片焊盘130a和第一接合焊盘110a可通过第一布线170a电连接。也就是说，第一半导体芯片120a和安装衬底100可经第一布线170a彼此电连接。在一些实施例中，第一布线170a可形成为具有钩形的折叠环。
根据一些实施例，第一布线170a不与第一半导体芯片120a的第一突起140a接触。另外，第一布线170a不与第二半导体芯片120b接触。当第一布线170a与第一半导体芯片120a的第一突起140a和第二半导体芯片120b接触时，在半导体封装件中可发生有缺陷的操作。因此，根据一些实施例，通过在第一布线170a形成为具有钩形的折叠环的情况下将第一间隔球150a插入于第一半导体芯片120a的第一凸球160a与第一芯片焊盘130a之间，可防止第一布线170a与第一半导体芯片120a的第一突起140a和第二半导体芯片120b的短路。第一间隔球150a的高度可考虑第一突起140a的高度和第一半导体芯片120a与第二半导体芯片120b之间的距离而改变。
根据一些实施例，由于第一布线170a不与第一半导体芯片120a的第一突起140a和第二半导体芯片120b接触，因此半导体封装件的可靠性可提高。另外，由于第一布线的高度H1减小，并且可堆叠更多半导体芯片，因此半导体封装件的集成度可提高。
第二半导体芯片120b可布置在第一半导体芯片120a上。例如，第二半导体芯片120b可经第二粘合剂膜122附着于第一半导体芯片120a。换句话说，第二粘合剂膜122可设置在第一半导体芯片120a和第二半导体芯片120b之间。
第一粘合剂膜121和第二粘合剂膜122可为例如芯片贴附膜(DAF)，并且可为布线可穿入的材料。第一粘合剂膜121的厚度和第二粘合剂膜122的厚度可根据附着的位置而不同。布线可穿入的粘合剂膜(例如，第一布线170a穿入的第二粘合剂膜122)可例如比第一粘合剂膜121更厚，从而可保护第一布线170a。这里，表达“穿入粘合剂膜的布线”意指即使粘合剂膜设置在布线上，由于粘合剂膜包围布线，布线的形状也保持不变。
第二间隔球150b可连接至第二半导体芯片120b的第二芯片焊盘130b。第二凸球160b可连接至第二间隔球150b。第二布线170b可连接至第二凸球160b和第一接合焊盘110a。换句话说，第二芯片焊盘130b和第一接合焊盘110a可通过第二布线170b彼此电连接。也就是说，第二半导体芯片120b和安装衬底100可经第二布线170b彼此电连接。第二布线170b可形成为具有钩形的折叠环。按照与上述的相同方式，第二布线170b不与第二半导体芯片120b的第二突起140b和第三半导体芯片120c接触。
第三半导体芯片120c可设置在第二半导体芯片120b上。例如，第三半导体芯片120c可经第三粘合剂膜123附着于第二半导体芯片120b。换句话说，第三粘合剂膜123可设置在第二半导体芯片120b和第三半导体芯片120c之间。第三粘合剂膜123也可为DAF。
第三凸球160c可直接连接至第三半导体芯片120c的第三芯片焊盘130c。换句话说，间隔球可不布置在第三半导体芯片120c上。第三布线170c可连接至第三凸球160c和第一接合焊盘110a。换句话说，第三芯片焊盘130c和第一接合焊盘110a可通过第三布线170c彼此电连接。第三布线170c可形成为普通环。在一些实施例中，普通环可为无皱形式。另外，当第三布线170c不在远离第一接合焊盘110a的方向上延伸时，第三布线170c可称作普通环。根据一些实施例的普通环可为正向环(forward loop)或反向环(reverse loop)。当布线接合的起始点是半导体芯片的芯片焊盘时，环称作正向环。另一方面，当布线接合的起始点是安装衬底的接合焊盘时，环称作反向环。根据一些实施例，第三布线170c不与第三半导体芯片120c的第三突起140c接触。
根据一些实施例，就第三半导体芯片120c而言，另一半导体芯片可不再堆叠在其顶部上。因此，第三半导体芯片120c可通过具有普通环形式的第三布线170c连接至第一接合焊盘110a。在一些实施例中，第三布线的高度H2可高于第一布线的高度H1。因此，即使在第三半导体芯片120c的第三芯片焊盘130c上不形成间隔球，第三布线170c也可不接触第三突起140c。
第一半导体芯片120a的第一芯片焊盘130a、第二半导体芯片120b的第二芯片焊盘130b和第三半导体芯片120c的第三芯片焊盘130c分别电连接至第一半导体芯片120a内部的半导体元件、第二半导体芯片120b内部的半导体元件和第三半导体芯片120c内部的半导体元件。由于第一芯片焊盘130a、第二芯片焊盘130b和第三芯片焊盘130c电连接至第一接合焊盘110a，因此第一芯片焊盘130a、第二芯片焊盘130b和第三芯片焊盘130c必须是对应的半导体芯片中的执行相同角色的焊盘。因此，根据一些实施例的第一半导体芯片120a、第二半导体芯片120b和第三半导体芯片120c可为具有相同构造的半导体芯片。
根据一些实施例，第一半导体芯片120a至第三半导体芯片120c可均匀堆叠。换句话说，假设第一半导体芯片120a至第三半导体芯片120c是相同尺寸的半导体芯片，第一半导体芯片120a至第三半导体芯片120c可在竖直方向上堆叠。换句话说，第一半导体芯片120a的第一芯片焊盘130a可与第二半导体芯片120b和第三半导体芯片120c竖直重叠。另外，第二半导体芯片120b的第二芯片焊盘130b可与第一半导体芯片120a和第三半导体芯片120c竖直重叠。此外，第三半导体芯片120c的第三芯片焊盘130c可与第一半导体芯片120a和第二半导体芯片120b竖直重叠。
图6是示出根据一些实施例的半导体封装件的示意图。
参照图6，根据一些实施例的半导体封装件可包括安装衬底100、第一半导体芯片120a、第二半导体芯片120b、第三半导体芯片120c、第一间隔球150a、第二间隔球150b、第一凸球160a、第二凸球160b、第三凸球160c、第一布线170a、第二布线170b、第三布线170c、第一粘合剂膜121、第二粘合剂膜122、第三粘合剂膜123和模制树脂180。
图6所示的各个构成元件可与上述图1和图5中的那些相似。因此，将省略或简单解释重复的描述。
根据一些实施例，安装衬底100可包括第一接合焊盘110a和第二接合焊盘110b。第一接合焊盘110a和第二接合焊盘110b可分别电连接至外部端子(连接至外部装置)。例如，第一接合焊盘110a电连接至第一焊料球(未示出)，第二接合焊盘110b可电连接至第二焊料球(未示出)。可替换地，第一接合焊盘110a和第二接合焊盘110b可为例如接地焊盘，并且可电连接至安装衬底100中的地线。第一接合焊盘110a和第二接合焊盘110b例如示为布置在安装衬底100的外壳中，但是实施例不限于此。
根据一些实施例，第一半导体芯片120a和第二半导体芯片120b可连接至第一接合焊盘110a。此外，第三半导体芯片120c可连接至第二接合焊盘110b。根据一些实施例，第一半导体芯片120a和第二半导体芯片120b可为相同构造的半导体芯片，第一半导体芯片120a和第三半导体芯片120c可为不同构造的半导体芯片。然而，实施例不限于此。
图6示出了第一半导体芯片120a和第二半导体芯片120b连接至第一接合焊盘110a并且第三半导体芯片120c连接至第二接合焊盘110b的构造，但是实施例不限于此。例如，第一半导体芯片120a连接至第一接合焊盘110a，第二半导体芯片120b和第三半导体芯片120c可连接至第二接合焊盘110b。本发明构思的技术领域的普通技术人员可实施包括具有各种布置方式的半导体芯片的半导体封装件。
图7是示出根据一些实施例的半导体封装件的示意图。
参照图7，根据一些实施例的半导体封装件可包括安装衬底100、第一半导体芯片120a、第二半导体芯片120b、第三半导体芯片120c、第四半导体芯片120d、第五半导体芯片120e、第二间隔球150b、第四间隔球150d、第一凸球160a、第二凸球160b、第三凸球160c、第四凸球160d、第五凸球160e、第一布线170a、第二布线170b、第三布线170c、第四布线170d、第五布线170e、第一粘合剂膜121、第二粘合剂膜122、第三粘合剂膜123、第四粘合剂膜124、第五粘合剂膜125和模制树脂180。
图7所示的各个构成元件可与上述图1、图5和图6的那些相似。因此，将省略或简单解释重复的描述。
根据一些实施例，第一半导体芯片120a可设置在安装衬底100上。安装衬底100和第一半导体芯片120a可经第一粘合剂膜121彼此附着。第二半导体芯片120b可设置在第一半导体芯片120a上。第一半导体芯片120a和第二半导体芯片120b可经第二粘合剂膜122彼此附着。第三半导体芯片120c可设置在第二半导体芯片120b上。第二半导体芯片120b和第三半导体芯片120c可经第三粘合剂膜123彼此附着。第四半导体芯片120d可设置在第三半导体芯片120c上。第三半导体芯片120c和第四半导体芯片120d可经第四粘合剂膜124彼此附着。第五半导体芯片120e可设置在第四半导体芯片120d上。第四半导体芯片120d和第五半导体芯片120e可经第五粘合剂膜125彼此附着。
第一半导体芯片120a至第五半导体芯片120e可按照z字形堆叠。换句话说，第一半导体芯片120a的第一芯片焊盘130a和第三半导体芯片120c的第三芯片焊盘130c可不分别接触第二粘合剂膜122和第四粘合剂膜124。然而，第二半导体芯片120b的第二芯片焊盘130b和第四半导体芯片120d的第四芯片焊盘130d可分别接触第三粘合剂膜123和第五粘合剂膜125。
换句话说，第一半导体芯片120a的第一芯片焊盘130a、第三半导体芯片120c的第三芯片焊盘130c和第五半导体芯片120e的第五芯片焊盘130e可不与第二半导体芯片120b和第四半导体芯片120d竖直重叠。此外，第二半导体芯片120b的第二芯片焊盘130b和第四半导体芯片120d的第四芯片焊盘130d可在竖直方向上与第一半导体芯片120a、第三半导体芯片120c和第五半导体芯片120e重叠。
根据一些实施例，第一凸球160a、第三凸球160c和第五凸球160e可分别直接连接至第一半导体芯片120a的第一芯片焊盘130a、第三半导体芯片120c的第三芯片焊盘130c和第五半导体芯片120e的第五芯片焊盘130e。换句话说，间隔球可不分离地连接至第一半导体芯片120a的顶部、第三半导体芯片120c的顶部和第五半导体芯片120e的顶部。
第一布线170a、第三布线170c和第五布线170e可分别连接至第一凸球160a、第三凸球160c和第五凸球160e。由于第一半导体芯片120a的第一芯片焊盘130a和第二半导体芯片120b不在竖直方向上重叠，因此第一布线170a可形成为普通环。换句话说，由于第一半导体芯片120a的第一芯片焊盘130a具有在其顶部形成普通环的足够高度，因此第一布线170a可形成为普通环。相似地，第三布线170c和第五布线170e可形成为普通环。
根据一些实施例，第二间隔球150b和第四间隔球150d可分别布置在第二半导体芯片120b的第二芯片焊盘130b和第四半导体芯片120d的第四芯片焊盘130d上。此外，第二间隔球150b和第四间隔球150d可分别连接至第二凸球160b和第四凸球160d。
第二布线170b和第四布线170d可分别连接至第二凸球160b和第四凸球160d。由于第二半导体芯片120b的第二芯片焊盘130b和第三半导体芯片120c在竖直方向上重叠，因此第二布线170b可形成为具有钩形的折叠环。换句话说，由于第二半导体芯片120b的第二芯片焊盘130b不具有在顶部形成普通环的足够高度，因此第二布线170b可形成为折叠环。相似地，第四布线170d可形成为具有钩形的折叠环。
即使图7示出了第一布线170a至第五布线170e均连接至第一接合焊盘110a，但是实施例不限于此。例如，第一布线170a至第五布线170e中的至少一个可连接至与第一接合焊盘110a不同的接合焊盘。
图8至图16是用于解释制造根据一些实施例的半导体封装件的方法的中间阶段图。将省略或简单解释鉴于以上实施例的重复或相似描述。
参照图8，将第一半导体芯片120a设置在安装衬底100上。可通过第一粘合剂膜121将第一半导体芯片120a附着于安装衬底100。接着，具有合适大小(例如，使得将形成在第一间隔球150a上的第一布线170a不与第一半导体芯片120a的第一突起140a和第二半导体芯片120b接触)的第一间隔球150a形成在第一半导体芯片120a的第一芯片焊盘130a上。本发明构思的技术领域的普通技术人员可根据需要改变第一间隔球150a的大小。
参照图9和图10，毛细管920可形成第一自由空气球(free air ball，FAB)910。通过在第一方向1001上移动毛细管920以按压第一自由空气球910，可在第一间隔球150a上形成第一凸球160a。
参照图11和图12，通过在远离第一接合焊盘110a的第二方向1101上移动毛细管920，可形成第一布线170a的第一部分(图4的170a1)。接着，通过在靠近第一接合焊盘110a的第三方向1102、第四方向1103和第五方向1104上移动毛细管920，可形成第一布线170a的第二部分(图4的170a2)。也就是说，可通过图9至图12的工艺形成具有钩形的折叠环。
参照图13，第二半导体芯片120b设置在第一半导体芯片120a上。第二半导体芯片120b可通过第二粘合剂膜122附着于第一半导体芯片120a。接着，具有合适大小的第二间隔球150b形成在第二半导体芯片120b的第二芯片焊盘130b上。本发明构思的技术领域的普通技术人员可根据需要改变第二间隔球150b的大小。
参照图14，按照与上述方法相似的方式形成第二凸球160b和第二布线170b。在一些实施例中，第二布线170b可形成为具有钩形的折叠环。
参照图15和图16，第三半导体芯片120c设置在第二半导体芯片120b上。第三半导体芯片120c可通过第二粘合剂膜122附着于第二半导体芯片120b。与第一半导体芯片120a和第二半导体芯片120b不同，在第三半导体芯片120c的第三芯片焊盘130c上不形成间隔球。在毛细管920形成第二自由空气球1510并且相对于第三半导体芯片120c的第三芯片焊盘130c按压第二自由空气球1510以形成第三凸球160c之后，在靠近第一接合焊盘110a的方向上形成布线，以形成第三布线170c。在一些实施例中，第三布线170c可形成为普通环。即使图15和图16示出了作为普通环的第三布线170c形成为正向环，但是实施例不限于此。
然后，通过在安装衬底10和第一半导体芯片120a至第三半导体芯片120c上填充模制树脂180制造图5的半导体封装件。
虽然参照图8至图16描述了制造图5的半导体封装件的方法，但是实施例不限于此。本发明构思的技术领域的普通技术人员可通过根据需要增加、改变或删除特定工序来制造包括本发明构思的技术思想的半导体封装件。
虽然已经参照本发明构思的示例性实施例特别示出和描述了本发明构思，但是本领域普通技术人员应该理解，在不脱离由权利要求限定的本发明构思的精神和范围的情况下，可对其作出各种形式和细节上的修改。因此，期望当前实施例在所有方面被认为是示出性而非限制性的，应该参照权利要求而非以上描述来指明本发明构思的范围。

Claims (20)

1.一种半导体封装件，包括：
安装衬底，其包括至少一个接合焊盘；
第一半导体芯片，其设置在所述安装衬底上，并且包括所述第一半导体芯片的上表面上的第一突起；
第一间隔球，其电连接至所述第一半导体芯片；
第一凸球，其电连接至所述第一间隔球；以及
第一布线，其将所述第一凸球和所述接合焊盘电连接，而不接触所述第一突起，
其中，所述第一布线包括在远离所述接合焊盘的方向上延伸的第一部分和在接近所述接合焊盘的方向上延伸的第二部分。
2.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片包括电连接至所述第一间隔球的第一芯片焊盘。
3.根据权利要求1所述的半导体封装件，还包括：
第二半导体芯片，其设置在所述第一半导体芯片上，并且包括所述第二半导体芯片的上表面上的第二突起；
第二凸球，其直接连接至所述第二半导体芯片；以及
第二布线，其将所述第二凸球与所述安装衬底电连接，而不接触所述第二突起。
4.根据权利要求3所述的半导体封装件，其中，所述第二凸球电连接至所述接合焊盘。
5.根据权利要求4所述的半导体封装件，其中，所述第一半导体芯片和所述第二半导体芯片具有相同结构。
6.根据权利要求3所述的半导体封装件，其中，所述接合焊盘包括第一接合焊盘和第二接合焊盘，并且
其中，所述第二凸球电连接至所述第二接合焊盘。
7.根据权利要求6所述的半导体封装件，其中，所述第一半导体芯片和所述第二半导体芯片具有不同结构。
8.根据权利要求3所述的半导体封装件，其中，所述第二布线不在远离所述接合焊盘的方向上延伸。
9.根据权利要求1所述的半导体封装件，还包括覆盖所述第一半导体芯片和所述安装衬底的模制树脂。
10.一种半导体封装件，包括：
至少一个接合焊盘；
第一半导体芯片，其包括连接至所述接合焊盘的第一芯片焊盘和从所述第一芯片焊盘的上表面突出的第一突起；
所述第一芯片焊盘上的第一间隔球；
所述第一间隔球上的第一凸球；
第一布线，其将所述第一凸球与所述接合焊盘连接，而不接触所述第一突起；
第二半导体芯片，其设置在所述第一半导体芯片上，并且包括连接至所述接合焊盘的第二芯片焊盘和从所述第二芯片焊盘的上表面突出的第二突起；
第二凸球，其直接连接至所述第二芯片焊盘；以及
第二布线，其将所述第二凸球和所述接合焊盘连接，而不接触所述第二突起，
其中，所述第一布线包括在远离所述接合焊盘的方向上延伸的第一部分和在接近所述接合焊盘的方向上延伸的第二部分，并且
其中，所述第二布线不在远离所述接合焊盘的方向上延伸。
11.根据权利要求10所述的半导体封装件，还包括：
第三半导体芯片，其包括连接至所述接合焊盘的第三芯片焊盘和从所述第三芯片焊盘的上表面突出的第三突起；
所述第三芯片焊盘上的第二间隔球；
所述第二间隔球上的第三凸球；以及
第三布线，其将所述第三凸球与所述接合焊盘连接，而不接触所述第三突起，
其中，所述第三半导体芯片设置在所述第一半导体芯片和所述第二半导体芯片之间，并且
其中，所述第三布线包括在远离所述接合焊盘的方向上延伸的第三部分和在接近所述接合焊盘的方向上延伸的第四部分。
12.根据权利要求11所述的半导体封装件，其中，所述接合焊盘包括多个接合焊盘，并且
其中，所述第一布线、所述第二布线和所述第三布线中的每一个连接至所述接合焊盘中的至少一个。
13.根据权利要求12所述的半导体封装件，其中，所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片具有相同结构。
14.根据权利要求12所述的半导体封装件，其中，所述第一布线、所述第二布线和所述第三布线中的一个或两个连接至所述接合焊盘中的一个，并且所述第一布线、所述第二布线和所述第三布线中的剩余一个或两个连接至所述接合焊盘中的另一个。
15.根据权利要求11所述的半导体封装件，其中，所述第一半导体芯片和所述第二半导体芯片具有相同结构，并且
其中，所述第三半导体芯片的结构与所述第一半导体芯片的结构不同。
16.根据权利要求10所述的半导体封装件，还包括设置在所述第一半导体芯片和所述第二半导体芯片之间的粘合剂膜。
17.根据权利要求10所述的半导体封装件，还包括覆盖所述第一半导体芯片和所述第二半导体芯片的模制树脂。
18.一种半导体封装件，包括：
安装衬底，其包括至少一个接合焊盘；
第一半导体芯片，其设置在所述安装衬底上，并且包括第一芯片焊盘和从所述第一芯片焊盘的上表面突出的第一突起；
第二半导体芯片，其设置在所述第一半导体芯片上，并且包括第二芯片焊盘和从所述第二芯片焊盘的上表面突出的第二突起；
第三半导体芯片，其设置在所述第二半导体芯片上，并且包括第三芯片焊盘和从所述第三芯片焊盘的上表面突出的第三突起；以及
第一布线、第二布线和第三布线，其将所述第一芯片焊盘、所述第二芯片焊盘和所述第三芯片焊盘分别连接至所述接合焊盘，
其中，所述第二布线通过设置在所述第二芯片焊盘上的第二间隔球和设置在所述第二间隔球上的第二凸球连接至所述第二芯片焊盘，
其中，所述第一芯片焊盘和所述第三芯片焊盘不在竖直方向上与所述第二半导体芯片重叠，
其中，所述第二芯片焊盘在所述竖直方向上与所述第一半导体芯片和所述第三半导体芯片重叠，并且
其中，所述第二布线包括在远离所述接合焊盘的方向上延伸的第一部分和在接近所述接合焊盘的方向上延伸的第二部分。
19.根据权利要求18所述的半导体封装件，其中，所述第一布线不在远离所述接合焊盘的方向上延伸，并且
其中，所述第三布线不在远离所述接合焊盘的方向上延伸。
20.根据权利要求18所述的半导体封装件，还包括：
第一凸球，其直接连接至所述第一芯片焊盘和所述第一布线；以及
第三凸球，其直接连接至所述第三芯片焊盘和所述第三布线。
CN201910784507.3A 2018-08-24 2019-08-23 半导体封装件 Pending CN110858573A (zh)

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