JP2015109325A - パッケージ基板の加工方法 - Google Patents
パッケージ基板の加工方法 Download PDFInfo
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- JP2015109325A JP2015109325A JP2013250864A JP2013250864A JP2015109325A JP 2015109325 A JP2015109325 A JP 2015109325A JP 2013250864 A JP2013250864 A JP 2013250864A JP 2013250864 A JP2013250864 A JP 2013250864A JP 2015109325 A JP2015109325 A JP 2015109325A
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- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 238000003672 processing method Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000003566 sealing material Substances 0.000 claims description 19
- 238000007789 sealing Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 4
- 239000002390 adhesive tape Substances 0.000 description 9
- 238000003384 imaging method Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000008393 encapsulating agent Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
【解決手段】 基板と、交差する複数の分割予定ラインで区画された基板上の各デバイス領域にそれぞれ搭載された複数のデバイスチップと、該デバイスチップを封止する封止材層と、からなるパッケージ基板の加工方法であって、該デバイス領域とは異なる領域で該基板側から切削ブレードを該パッケージ基板に該封止材層を貫通する深さに切り込ませ、該分割予定ラインに対して所定の位置関係を有する切削痕を形成する切削痕形成ステップと、該切削痕形成ステップを実施した後、切削ブレードで該切削痕を基に該封止材層側からパッケージ基板を該分割予定ラインに沿って切削する切削ステップと、を備えたことを特徴とするパッケージ基板の加工方法が提供される。
【選択図】図4
Description
11 パッケージ基板
12 撮像ユニット
13 基板
17 デバイスチップ
18 切削ブレード
21 封止材層
22,24 粘着テープ
Claims (2)
- 基板と、交差する複数の分割予定ラインで区画された基板上の各デバイス領域にそれぞれ搭載された複数のデバイスチップと、該デバイスチップを封止する封止材層と、からなるパッケージ基板の加工方法であって、
該デバイス領域とは異なる領域で該基板側から切削ブレードを該パッケージ基板に該封止材層を貫通する深さに切り込ませ、該分割予定ラインに対して所定の位置関係を有する切削痕を形成する切削痕形成ステップと、
該切削痕形成ステップを実施した後、切削ブレードで該切削痕を基に該封止材層側からパッケージ基板を該分割予定ラインに沿って切削する切削ステップと、
を備えたことを特徴とするパッケージ基板の加工方法。 - 該切削痕形成ステップでは、複数の分割予定ラインにそれぞれ対応した複数の切削痕を形成する請求項1記載のパッケージ基板の加工方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013250864A JP6257291B2 (ja) | 2013-12-04 | 2013-12-04 | パッケージ基板の加工方法 |
TW103137393A TWI626682B (zh) | 2013-12-04 | 2014-10-29 | Processing method of package substrate |
US14/554,444 US9117898B2 (en) | 2013-12-04 | 2014-11-26 | Method of fabricating a plurality of cut marks on a substrate |
CN201410730177.7A CN104701256B (zh) | 2013-12-04 | 2014-12-04 | 封装基板的加工方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013250864A JP6257291B2 (ja) | 2013-12-04 | 2013-12-04 | パッケージ基板の加工方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015109325A true JP2015109325A (ja) | 2015-06-11 |
JP6257291B2 JP6257291B2 (ja) | 2018-01-10 |
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JP2013250864A Active JP6257291B2 (ja) | 2013-12-04 | 2013-12-04 | パッケージ基板の加工方法 |
Country Status (4)
Country | Link |
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US (1) | US9117898B2 (ja) |
JP (1) | JP6257291B2 (ja) |
CN (1) | CN104701256B (ja) |
TW (1) | TWI626682B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017028100A (ja) * | 2015-07-22 | 2017-02-02 | 株式会社ディスコ | アライメント方法 |
JP2017147304A (ja) * | 2016-02-16 | 2017-08-24 | 株式会社ディスコ | 切削方法 |
JP2018060882A (ja) * | 2016-10-04 | 2018-04-12 | 株式会社ディスコ | パッケージ基板の加工方法 |
JP2019212773A (ja) * | 2018-06-05 | 2019-12-12 | 株式会社ディスコ | 矩形被加工物の加工方法 |
CN111341713A (zh) * | 2018-12-18 | 2020-06-26 | 中芯集成电路(宁波)有限公司 | 一种封装方法和封装结构 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6887722B2 (ja) * | 2016-10-25 | 2021-06-16 | 株式会社ディスコ | ウェーハの加工方法及び切削装置 |
JP7150401B2 (ja) * | 2018-11-20 | 2022-10-11 | 株式会社ディスコ | 被加工物の加工方法 |
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JP2002289628A (ja) * | 2001-03-23 | 2002-10-04 | Seiko Epson Corp | 画像認識方法及び画像認識装置並びに半導体装置の製造方法及び製造装置 |
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JP2013058653A (ja) * | 2011-09-09 | 2013-03-28 | Disco Abrasive Syst Ltd | 板状物の分割方法 |
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- 2014-12-04 CN CN201410730177.7A patent/CN104701256B/zh active Active
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JP2000223445A (ja) * | 1999-01-29 | 2000-08-11 | Mitsubishi Electric Corp | Lsiダイシング装置及びダイシング方法 |
US20010055856A1 (en) * | 2000-06-13 | 2001-12-27 | Su Tao | Method of dicing a wafer from the back side surface thereof |
JP2002289628A (ja) * | 2001-03-23 | 2002-10-04 | Seiko Epson Corp | 画像認識方法及び画像認識装置並びに半導体装置の製造方法及び製造装置 |
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JP2017028100A (ja) * | 2015-07-22 | 2017-02-02 | 株式会社ディスコ | アライメント方法 |
JP2017147304A (ja) * | 2016-02-16 | 2017-08-24 | 株式会社ディスコ | 切削方法 |
JP2018060882A (ja) * | 2016-10-04 | 2018-04-12 | 株式会社ディスコ | パッケージ基板の加工方法 |
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CN111341713A (zh) * | 2018-12-18 | 2020-06-26 | 中芯集成电路(宁波)有限公司 | 一种封装方法和封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20150155205A1 (en) | 2015-06-04 |
CN104701256B (zh) | 2019-03-08 |
TW201528360A (zh) | 2015-07-16 |
CN104701256A (zh) | 2015-06-10 |
JP6257291B2 (ja) | 2018-01-10 |
US9117898B2 (en) | 2015-08-25 |
TWI626682B (zh) | 2018-06-11 |
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