JP2014150279A - 炭化珪素半導体装置 - Google Patents
炭化珪素半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 35
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 34
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- 238000009826 distribution Methods 0.000 description 10
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Abstract
【解決手段】炭化珪素半導体基板と、炭化珪素半導体基板の主面上に配設された第1導電型のドリフト層と、ドリフト層の一部に配設され、それぞれが半導体素子として動作するセルが複数形成されたセル領域と、ドリフト層のセル領域とは別の領域の上層部に配設される第2導電型のウエル層と、ウエル層の上方に配設された絶縁膜と、絶縁膜上およびセル領域の上方に配設されたゲート電極と、ウエル層の上方に形成され、ゲート電極と電気的に接続されたゲートパッドと、ウエル層と電気的に接続されたソース電極とを備え、ウエル層は、1×1019cm−3以上1×1021cm−3以下の第2導電型の不純物濃度を有する不純物領域を含んでいる。
【選択図】図18
Description
本実施の形態に係るSiC半導体装置の一例として、n型チャネルSiC―MOSFETについて、その構造およびその製造方法並びにその評価を、以下に記載する。
従来法により作製されたSiC−MOSFETにおいては、スイッチング速度を上げていくと、ゲートパッド部下方乃至はゲートフィンガー部下方に位置するp型ウエル層1の電圧分布が大きくなり、ゲート絶縁膜が破壊された。しかしながら、本実施の形態の製造方法により作製されたSiC−MOSFETでは、同様の条件下においても、ゲート絶縁膜6が破壊されることは無く、p型半導体層14の存在によって、ゲート電極用パッド部11の下方に位置するp型ウエル層1(1OM)内を変位電流が流れる際の電圧降下による当該p型ウエル層1(1OM)の電圧分布が抑制乃至は低減されることがわかる。
本実施の形態に係るSiC半導体装置の一例として、n型チャネルSiC―IGBTについて、その構造およびその評価を、以下に記載する。
従来法により作製されたSiC−IGBTにおいては、スイッチング速度を上げていくと、電圧降下による最外周のp型ウエル層の電圧分布が100V以上になり、ゲート絶縁膜が破壊された。しかしながら、本実施の形態により作製されたSiC−IGBTでは、同様の条件下においても、ゲート絶縁膜6が破壊されることは無く、p型半導体層14の存在によって、電圧降下による最外周のp型ウエル層1OMの電圧分布が抑えられることがわかる。この条件下でのp型ウエル層1OMとゲート電極用パッド部11間の電位差分布を、数値計算により見積もったところ、従来法で作製されるSiC−IGBTでは最大値が100V以上であったが、本実施の形態により作製されるSiC−IGBTでは最大値が50V以下であった。
以上説明した本発明に係る実施の形態1および2においては、最外周のp型ウエル層1(1OMに相当)の上面上に、全面的または部分的にp型半導体層14が配設されているという説明を行ったが、部分的に配設する例としては、櫛歯状に配設しても良い。以下、図20〜図26を用いて、p型半導体層14を櫛歯状に配設する例を説明する。
本実施の形態に係るSiC半導体装置の一例として、n型チャネルSiC―MOSFETについて、その構造およびその製造方法並びにその評価を、以下に記載する。
従来法により作製されたSiC−MOSFETにおいては、スイッチング速度を上げていくと、ゲートパッド部下方乃至はゲートフィンガー部下方に位置するp型ウエル層1の電圧分布が大きくなり、ゲート絶縁膜が破壊された。しかしながら、本実施の形態の製造方法により作製されたSiC−MOSFETでは、同様の条件下においても、ゲート絶縁膜6が破壊されることは無く、p型半導体層14の存在によって、ゲート電極用パッド部11の下方に位置するp型ウエル層1(1OM)内を変位電流が流れる際の電圧降下による当該p型ウエル層1(1OM)の電圧分布が抑制乃至は低減されることがわかる。
以上、本発明の実施の形態を詳細に開示し記述したが、以上の記述は本発明の適用可能な局面を例示したものであって、本発明はこれに限定されるものではない。すなわち、記述した局面に対する様々な修正や変形例を、この発明の範囲から逸脱することの無い範囲内で考えることが可能である。
以上説明した実施の形態3のn型チャネルSiC―MOSFETは、p型半導体層14をp型ウエル層1OMの上層部内に形成するので、同じようにp型ウエル層1OMの上層部内に形成されたp型ウエルコンタクト層3とp型半導体層14とを一体化しても良い。
以上説明した実施の形態3のn型チャネルSiC―MOSFETにおいては、最外周のp型ウエル層1(1OMに相当)の上面上に、全面的または部分的にp型半導体層14が配設されているという説明を行ったが、部分的に配設する例としては、櫛歯状に配設しても良い。以下、図35〜図39を用いて、p型半導体層14を櫛歯状に配設する例を説明する。
Claims (4)
- 炭化珪素半導体基板と、
前記炭化珪素半導体基板の主面上に配設された第1導電型のドリフト層と、
前記ドリフト層の一部に配設され、それぞれが半導体素子として動作するセルが複数形成されたセル領域と、
前記ドリフト層の前記セル領域とは別の領域の上層部に配設される第2導電型のウエル層と、
前記ウエル層の上方に配設された絶縁膜と、
前記絶縁膜上および前記セル領域の上方に配設されたゲート電極と、
前記ウエル層の上方に形成され、前記ゲート電極と電気的に接続されたゲートパッドと、
前記ウエル層と電気的に接続されたソース電極と、を備え、
前記ウエル層は、1×1019cm−3以上1×1021cm−3以下の第2導電型の不純物濃度を有する不純物領域を含むことを特徴とする炭化珪素半導体装置。 - 前記ウエル層の、前記不純物領域は、厚さ100nm以上である、請求項1に記載の炭化珪素半導体装置。
- 前記ドリフト層上に、第1導電型のチャネルエピタキシャル層を備える、請求項1または請求項2に記載の炭化珪素半導体装置。
- 前記ウエル層の第2導電型の不純物はAlである、請求項1から請求項3のいずれか1項に記載の炭化珪素半導体装置。
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