JP2012526398A - 生産性が高い多孔質半導体層形成装置 - Google Patents
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Abstract
Description
Claims (22)
- 複数枚の半導体ウェハ上に多孔質半導体層を形成する装置であって、
電流供給用の第1及び第2電極と、
複数枚の半導体ウェハ、並びに各半導体ウェハの縁を囲みその場に固定するウェハ縁封止材を有し、鉛直線に対し任意角で傾斜させうるウェハ積層体と、
本装置に対する電解質供給用の電解質供給路と、
半導体ウェハ同士の間隙毎にあり、各半導体ウェハの少なくとも表面への電解質供給及びそこからのガス排出に使用される都合複数個の電解質流路乃至分室と、
を備える装置。 - 請求項1記載の装置であって、半導体ウェハのうち複数枚がシリコンウェハである装置。
- 請求項1記載の装置であって、半導体ウェハのうち複数枚が正方形又は略正方形の装置。
- 請求項1記載の装置であって、半導体ウェハのうち複数枚が略円形の装置。
- 請求項1記載の装置であって、第1及び第2電極を用い電流及び電圧の極性を所定期間経過後1サイクル以上に亘り交番又は変化させる装置。
- 請求項5記載の装置であって、その第1及び第2電極を用い複数通りの所定値で電流を供給することで、その多孔度が異なる複数個の層を発生させる装置。
- 請求項6記載の装置であって、その所定値として離散値を使用することで、その多孔度が不連続な複数個の層を発生させる装置。
- 請求項6記載の装置であって、その所定値として連続値を使用することで、その多孔度に傾斜の付いた層を発生させる装置。
- 請求項1記載の装置であって、そのウェハ縁封止材が形状適合性を有し、ある範囲内のウェハ直径及びウェハ厚に対応可能な装置。
- 複数枚の半導体ウェハ上に多孔質半導体層を形成する装置であって、
電流供給用の第1及び第2電極と、
各複数枚の半導体ウェハが並ぶ半導体ウェハ配列複数個、並びに各半導体ウェハの縁を囲みその場に固定するウェハ縁封止材を有し、鉛直線に対し任意角で傾斜させうるウェハ配列積層体と、
本装置に対する電解質供給用の電解質供給路と、
半導体ウェハ配列同士の間隙毎にあり、各半導体ウェハの少なくとも表面への電解質供給及びそこからのガス排出に使用される都合複数個の電解質流路乃至分室と、
を備える装置。 - 請求項10記載の装置であって、各半導体ウェハ配列内の各半導体ウェハが正方形又は略正方形の装置。
- 請求項10記載の装置であって、各半導体ウェハ配列内の各半導体ウェハが略円形の装置。
- 請求項10記載の装置であって、その第1及び第2電極を用い電流及び電圧の極性を所定期間経過後1サイクル以上に亘り交番又は変化させる装置。
- 請求項13記載の装置であって、その第1及び第2電極を用い複数通りの所定値で電流を供給することで、その多孔度が異なる複数個の層を発生させる装置。
- 請求項14記載の装置であって、その所定値として離散値を使用することで、その多孔度が不連続な複数個の層を発生させる装置。
- 請求項14記載の装置であって、その所定値として連続値を使用することで、その多孔度に傾斜の付いた層を発生させる装置。
- 請求項10記載の装置であって、そのウェハ縁封止材が形状適合性を有し、ある範囲内のウェハ直径及びウェハ厚に対応可能な装置。
- 複数枚の半導体ウェハ上に多孔質半導体層を形成する方法であって、
第1長方形配列が形成されるよう第1群半導体ウェハを配置するステップと、
第1長方形配列とほぼ同寸法の第2長方形配列が形成されるよう第2群半導体ウェハを配置するステップと、
第1長方形配列を第2長方形配列の上方に配置するステップと、
各群半導体ウェハそれぞれの少なくとも表面に電解質を供給するステップと、
その電解質中に第1及び第2電極を配置するステップと、
第1及び第2電極に電流を供給するステップと、
を有する方法。 - 請求項18記載の方法であって、各群半導体ウェハそれぞれの少なくとも表面への電解質流入及びそこからのガス排出をポンプで実行するステップを有する方法。
- 請求項18記載の方法であって、水平線に対し鋭角をなすよう各群半導体ウェハを配置するステップを有する方法。
- 請求項18記載の方法であって、各群半導体ウェハを直立させるステップを有する方法。
- リユーザブル半導体テンプレートの両面に薄い結晶半導体層を形成する方法であって、
その多孔度が異なる都合複数個の多孔質半導体層をリユーザブル半導体テンプレートの複数面に形成するステップと、
水素ベーキング及び半導体成長処理を施すことでリユーザブル半導体テンプレートの多孔質半導体層形成面それぞれに半導体層を成長させるステップと、
成長した半導体層をユーザブル半導体テンプレートの多孔質半導体層形成面から分離させるステップと、
再使用に備えリユーザブル半導体テンプレートを洗浄するステップと、
を有する方法。
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US17553509P | 2009-05-05 | 2009-05-05 | |
US61/175,535 | 2009-05-05 | ||
US12/774,667 US8999058B2 (en) | 2009-05-05 | 2010-05-05 | High-productivity porous semiconductor manufacturing equipment |
PCT/US2010/033792 WO2010129719A1 (en) | 2009-05-05 | 2010-05-05 | High-productivity porous semiconductor manufacturing equipment |
US12/774,667 | 2010-05-05 |
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JP5872456B2 JP5872456B2 (ja) | 2016-03-01 |
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US (2) | US8999058B2 (ja) |
EP (1) | EP2427914A4 (ja) |
JP (1) | JP5872456B2 (ja) |
CN (1) | CN102460716B (ja) |
MY (1) | MY165969A (ja) |
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EP2427914A1 (en) | 2012-03-14 |
US9869031B2 (en) | 2018-01-16 |
MY165969A (en) | 2018-05-18 |
US8999058B2 (en) | 2015-04-07 |
US20150315719A1 (en) | 2015-11-05 |
CN102460716A (zh) | 2012-05-16 |
WO2010129719A1 (en) | 2010-11-11 |
US20110030610A1 (en) | 2011-02-10 |
CN102460716B (zh) | 2015-03-25 |
EP2427914A4 (en) | 2013-06-05 |
JP5872456B2 (ja) | 2016-03-01 |
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