JP2012257211A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2012257211A JP2012257211A JP2012108073A JP2012108073A JP2012257211A JP 2012257211 A JP2012257211 A JP 2012257211A JP 2012108073 A JP2012108073 A JP 2012108073A JP 2012108073 A JP2012108073 A JP 2012108073A JP 2012257211 A JP2012257211 A JP 2012257211A
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- JP
- Japan
- Prior art keywords
- transistor
- wiring
- signal
- potential
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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Abstract
【解決手段】開示する発明の一態様の半導体装置は、第1の電位を第1の配線に供給する機能を有する第1のトランジスタと、第2の電位を第1の配線に供給する機能を有する第2のトランジスタと、第1のトランジスタのゲートに第1のトランジスタがオンをオンにするための第3の電位を供給した後、第3の電位の供給を止める機能を有する第3のトランジスタと、第2の電位を第1のトランジスタのゲートに供給する機能を有する第4のトランジスタと、第1の信号にオフセットを施した第2の信号を生成する機能を有する第1の回路と、を有し、第4のトランジスタのゲートには、第2の信号が入力され、第2の信号の最小値は、第2の電位未満の値である。
【選択図】図1
Description
本実施の形態では、入力信号にオフセットを施した信号を生成し、該信号によって駆動する半導体装置の一例について説明する。
本実施の形態では、本発明の一態様である半導体装置をシフトレジスタ回路が有するフリップフロップ回路に用いる場合について説明する。なお、本実施の形態では、実施の形態1と異なる部分について説明する。
本実施の形態では、実施の形態2において説明した半導体装置をフリップフロップ回路として用いたシフトレジスタ回路について説明する。なお、本実施の形態では、実施の形態1、2と異なる部分について説明する。
本実施の形態では、実施の形態3のシフトレジスタ回路を駆動回路として用いた表示装置について説明する。
本実施の形態では、実施の形態1の半導体装置、実施の形態2の半導体装置、実施の形態3のシフトレジスタ回路及び実施の形態4の表示装置に用いることができるトランジスタについて説明する。
以下では、酸化物半導体について詳述する。
(a―A)2+(b―B)2+(c―C)2≦r2
を満たすことをいい、rは、例えば、0.05とすればよい。他の酸化物でも同様である。
チャネルが酸化物半導体層に形成されるトランジスタについて図17(A)〜(D)を参照して説明する。なお、図17(A)〜(D)は、トランジスタの構造例を示す断面模式図である。
In、Sn、Znを主成分とする酸化物半導体をチャネル形成領域とするトランジスタは、該酸化物半導体を形成する際に基板を加熱して成膜すること、或いは酸化物半導体層を形成した後に熱処理を行うことで良好な特性を得ることができる。なお、主成分とは組成比で5atomic%以上含まれる元素をいう。
本実施の形態においては、上記実施の形態で説明した半導体装置、シフトレジスタ回路又は表示装置等を具備する電子機器の例について説明する。
12 配線
13 配線
14 配線
15 配線
16 配線
17 配線
21 配線
22 配線
23 配線
24 配線
25 配線
31 配線
31_i 配線
31_i−1 配線
32 配線
33 配線
34 配線
35 配線
36 配線
37 配線
38 配線
100 回路
101 容量素子
102 トランジスタ
103 容量素子
110 回路
111 トランジスタ
112 トランジスタ
113 トランジスタ
114 トランジスタ
115 トランジスタ
116 トランジスタ
120 回路
121 トランジスタ
122 トランジスタ
123 トランジスタ
124 トランジスタ
125 トランジスタ
126 トランジスタ
200 フリップフロップ回路
200_1 フリップフロップ回路
200_2 フリップフロップ回路
200_3 フリップフロップ回路
600 被素子形成層
601 導電層
602 絶縁層
603 酸化物半導体層
606 絶縁層
608 導電層
100A 回路
100B 回路
101A 容量素子
101B 容量素子
102A トランジスタ
102B トランジスタ
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4018 FPC
4018a FPC
4018b FPC
604a 領域
604b 領域
605a 導電層
605b 導電層
9630 筐体
9631 表示部
9632 操作キー
9633 スピーカ
9635 操作キー
9636 接続端子
9638 マイクロフォン
9651 太陽電池
9652 バッテリー
9653 ウインドウ型表示部
9672 記録媒体読込部
9676 シャッターボタン
9677 受像部
9680 外部接続ポート
9681 ポインティングデバイス
IN 信号
INO 信号
IN1 信号
IN1O 信号
IN2 信号
IN2O 信号
IN3 信号
SE 信号
OUT 信号
OUTA 信号
OUTB 信号
OUT1 信号
OUT2 信号
OUTN 信号
VH 電位
VDD 電位
VL1 電位
VL2 電位
N1 ノード
T0 期間
T1 期間
Ta 期間
Tb 期間
Tc 期間
Td 期間
CK 信号
CK1 信号
CK2 信号
SP 信号
M1 トランジスタ
M2 トランジスタ
M3 トランジスタ
M4 トランジスタ
C1 容量素子
Claims (3)
- 第1の電位を第1の配線に供給する機能を有する第1のトランジスタと、
第2の電位を前記第1の配線に供給する機能を有する第2のトランジスタと、
前記第1のトランジスタのゲートに前記第1のトランジスタがオンになるための第3の電位を供給した後、前記第3の電位の供給を止める機能を有する第3のトランジスタと、
前記第2の電位を前記第1のトランジスタのゲートに供給する機能を有する第4のトランジスタと、
第1の信号にオフセットを施した第2の信号を生成する機能を有する第1の回路と、を有し、
前記第4のトランジスタのゲートには、前記第2の信号が入力され、
前記第2の信号のロウレベルの電位は、前記第2の電位未満の電位であることを特徴とする半導体装置。 - 第1の電位を第1の配線に供給する機能を有する第1のトランジスタと、
第2の電位を前記第1の配線に供給する機能を有する第2のトランジスタと、
前記第1のトランジスタのゲートに前記第1のトランジスタがオンになるための第3の電位を供給した後、前記第3の電位の供給を止める機能を有する第3のトランジスタと、
前記第2の電位を前記第1のトランジスタのゲートに供給する機能を有する第4のトランジスタと、
一方の電極に第1の信号が入力される容量素子と、
前記容量素子の他方の電極に第4の電位を供給する機能を有する第5のトランジスタと、を有し、
前記第4のトランジスタのゲートは、前記容量素子の他方の電極と接続され、
前記第4の電位は、前記第2の電位未満の電位であることを特徴とする半導体装置。 - 請求項1又は請求項2において、
前記第2のトランジスタのゲートには、前記第1の信号が入力されることを特徴とする半導体装置。
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