JP2012222366A - チップパッケージとその製造方法 - Google Patents
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Abstract
【解決手段】本発明の実施例は、チップパッケージの製造方法を提供する。複数のスクライブラインにより隔てられる複数のデバイス領域を有する半導体ウェハを提供する工程と、パッケージ基板を半導体ウェハに接合し、スペーサ層をパッケージ基板と半導体ウェハの間に設置して、スペーサ層は、それぞれデバイス領域を露出する複数のキャビティを区画し、半導体ウェハの外縁に隣接する複数の貫通孔を有する工程と、貫通孔中に、接着材料を充填し、スペーサ層は粘性を有し、材料は接着材料と異なる工程と、スクライブラインに沿って半導体ウェハ、パッケージ基板とスペーサ層をダイスして、互いに分離した複数のチップパッケージを形成する工程と、を含む。
【選択図】図5
Description
よって、チップパッケージの信頼度を改善する必要がある。
図1A〜図1Cは、本発明の実施形態によるチップパッケージの製造工程の断面図で、図2は、図1Bの平面図である。図1Bは、図2中のI-I’線に沿った断面図で、簡潔にするため、図2では、パッケージ基板を省略している。
当然わかることであるが、本実施例のチップパッケージの製造工程は、図1A〜図1Cの製造工程に類似し、両者の差異は、本実施形態では、貫通孔Tと接着材料140とが、さらにスペーサ部分134内にも設けられていることである。
注意すべきことは、本実施例のチップパッケージの製造工程は、図3A〜図3Bの製造工程に類似し、両者の差異は、本実施形態のスペーサ層130は複数の内環構造136を有することである。
注意すべきことは、本実施形態のチップパッケージの製造工程は、図3A〜図3Bの製造工程に類似し、両者の差異は、貫通孔Tの配列方式が異なることである。
当然わかることであるが、本実施例のチップパッケージの製造工程は、図9A〜図9Bの製造工程に類似し、両者の差異は、貫通孔Tの配列方式が異なることである。
本発明では好ましい実施例を前述の通り開示したが、これらは決して本発明に限定するものではなく、当該技術を熟知する者なら誰でも、本発明の精神と領域を脱しない範囲内で各種の変動や潤色を加えることができ、従って本発明の保護範囲は、特許請求の範囲で指定した内容を基準とする。
110 半導体ウェハ
110a (ダイス後の)半導体基板
112 デバイス領域
114 中心領域
116 周辺領域
120 パッケージ基板
120a (ダイス後の)パッケージ基板
130 スペーサ層
130a、130b、130c、130d、130e (ダイス後の)スペーサ層
132 外環部
134 スペーサ部分
136 内環構造
138 側壁
140 接着材料
140a 接着材料構造
140b、140c 環状接着材料構造
A トレンチ
B 外環トレンチ
C キャビティ
D 環状トレンチ
H 空洞貫通孔
P 外縁
R 凹部
S スクライブライン
T 貫通孔
Claims (8)
- チップパッケージであって、
デバイス領域を有する半導体基板と、
前記半導体基板上に設置されるパッケージ基板と、
前記半導体基板と前記パッケージ基板の間に設置され、かつ、前記デバイス領域を露出させるキャビティを区画するスペーサ層と、
前記スペーサ層中に埋め込まれるとともに、前記キャビティ外に位置する互いに独立した複数の接着材料構造と、を含み、
前記スペーサ層の材料は前記複数の接着材料構造の材料と異なることを特徴とするチップパッケージ。 - 前記スペーサ層は、前記キャビティから離れた面に側壁を有し、前記側壁は、前記半導体基板から前記パッケージ基板にまで延伸する複数の凹部を有し、かつ、前記複数の接着材料構造は、それぞれ、前記複数の凹部中を充填することを特徴とする請求項1に記載のチップパッケージ。
- 前記複数の接着材料構造のそれぞれは、前記キャビティから離れた面に第二側壁を有し、前記第二側壁は前記スペーサ層の前記側壁と同一面となっていることを特徴とする請求項2に記載のチップパッケージ。
- 前記スペーサ層は複数の貫通孔を有し、前記複数の接着材料構造のそれぞれは、前記複数の貫通孔を充填することを特徴とする請求項1に記載のチップパッケージ。
- 前記スペーサ層は、さらに、前記キャビティ中に内環構造を有し、前記内環構造は複数の貫通孔を有し、
前記チップパッケージは、さらに、それぞれ、前記貫通孔中に充填される互いに独立した複数の第二接着材料構造を有し、前記スペーサ層の材料は、前記第二接着材料構造の材料と異なることを特徴とする請求項1に記載のチップパッケージ。 - 前記スペーサ層は、前記半導体基板と前記パッケージ基板とに物理的に接触しており、前記接着材料構造のそれぞれは、前記半導体基板から前記パッケージ基板にまで延出していることを特徴とする請求項1に記載のチップパッケージ。
- さらに、前記スペーサ層の前記側壁を囲みかつ被覆し、かつ、前記キャビティ外に位置する連続した環状接着材料構造を含むことを特徴とする請求項1に記載のチップパッケージ。
- 前記スペーサ層は、前記スペーサ層を貫通し、かつ、前記キャビティを環繞する環状トレンチを有し、
前記チップパッケージは、さらに、前記環状トレンチ中に充填される連続した環状接着材料構造を含むことを特徴とする請求項1に記載のチップパッケージ。
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Application Number | Priority Date | Filing Date | Title |
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CN201110092927.9A CN102738013B (zh) | 2011-04-13 | 2011-04-13 | 晶片封装体及其制作方法 |
CN201110092927.9 | 2011-04-13 |
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JP2012222366A true JP2012222366A (ja) | 2012-11-12 |
JP5384690B2 JP5384690B2 (ja) | 2014-01-08 |
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JP2021111787A (ja) * | 2020-01-06 | 2021-08-02 | 精材科技股▲ふん▼有限公司 | チップパッケージ及びその製造方法 |
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TWI485818B (zh) * | 2011-06-16 | 2015-05-21 | Xintec Inc | 晶片封裝體及其形成方法 |
CN104037135B (zh) | 2013-03-07 | 2017-09-22 | 精材科技股份有限公司 | 晶片封装体及其形成方法 |
CN103400808B (zh) * | 2013-08-23 | 2016-04-13 | 苏州晶方半导体科技股份有限公司 | 影像传感器的晶圆级封装结构及封装方法 |
WO2015094184A1 (en) * | 2013-12-17 | 2015-06-25 | Intel Corporation | Package mems switch and method |
US20150371956A1 (en) * | 2014-06-19 | 2015-12-24 | Globalfoundries Inc. | Crackstops for bulk semiconductor wafers |
CN104362243B (zh) * | 2014-10-24 | 2017-11-03 | 深圳市华星光电技术有限公司 | 基板的封装方法及封装结构 |
TWI731260B (zh) * | 2018-08-30 | 2021-06-21 | 奕力科技(開曼)股份有限公司 | 半導體基板結構及其製造方法 |
KR20220001292A (ko) | 2020-06-29 | 2022-01-05 | 삼성전자주식회사 | 반도체 패키지 |
CN111710618B (zh) * | 2020-07-15 | 2021-10-12 | 广芯微电子(广州)股份有限公司 | 一种晶圆钝化层缺陷的检测方法 |
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US11521938B2 (en) | 2020-01-06 | 2022-12-06 | Xintec Inc. | Chip package including substrate inclined sidewall and redistribution line |
US11749618B2 (en) | 2020-01-06 | 2023-09-05 | Xintec Inc. | Chip package including substrate having through hole and redistribution line |
US11784134B2 (en) | 2020-01-06 | 2023-10-10 | Xintec Inc. | Chip package and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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JP5384690B2 (ja) | 2014-01-08 |
TW201241908A (en) | 2012-10-16 |
CN102738013B (zh) | 2016-04-20 |
CN102738013A (zh) | 2012-10-17 |
TWI512811B (zh) | 2015-12-11 |
US20120261809A1 (en) | 2012-10-18 |
US9136241B2 (en) | 2015-09-15 |
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