JP2011530167A - ホウ素閉じ込めを強化した埋め込みSi/Ge材質を有するトランジスタ - Google Patents

ホウ素閉じ込めを強化した埋め込みSi/Ge材質を有するトランジスタ Download PDF

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JP2011530167A
JP2011530167A JP2011521127A JP2011521127A JP2011530167A JP 2011530167 A JP2011530167 A JP 2011530167A JP 2011521127 A JP2011521127 A JP 2011521127A JP 2011521127 A JP2011521127 A JP 2011521127A JP 2011530167 A JP2011530167 A JP 2011530167A
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diffusion
drain
region
transistor
species
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JP2011521127A
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Japanese (ja)
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JP2011530167A5 (enExample
Inventor
ホエンチェル ジャン
ヴィアトル マチェイ
パパジョルジュ ヴァシリオス
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2011530167A publication Critical patent/JP2011530167A/ja
Publication of JP2011530167A5 publication Critical patent/JP2011530167A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01Manufacture or treatment
    • H10D62/021Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • H10D62/822Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2011521127A 2008-07-31 2009-07-31 ホウ素閉じ込めを強化した埋め込みSi/Ge材質を有するトランジスタ Pending JP2011530167A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008035806A DE102008035806B4 (de) 2008-07-31 2008-07-31 Herstellungsverfahren für ein Halbleiterbauelement bzw. einen Transistor mit eingebettetem Si/GE-Material mit einem verbesserten Boreinschluss sowie Transistor
DE102008035806.1 2008-07-31
US12/503,340 2009-07-15
US12/503,340 US20100025743A1 (en) 2008-07-31 2009-07-15 Transistor with embedded si/ge material having enhanced boron confinement
PCT/US2009/004425 WO2010014251A2 (en) 2008-07-31 2009-07-31 Transistor with embedded si/ge material having enhanced boron confinement

Publications (2)

Publication Number Publication Date
JP2011530167A true JP2011530167A (ja) 2011-12-15
JP2011530167A5 JP2011530167A5 (enExample) 2012-09-06

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JP2011521127A Pending JP2011530167A (ja) 2008-07-31 2009-07-31 ホウ素閉じ込めを強化した埋め込みSi/Ge材質を有するトランジスタ

Country Status (8)

Country Link
US (1) US20100025743A1 (enExample)
JP (1) JP2011530167A (enExample)
KR (1) KR20110046501A (enExample)
CN (1) CN102105965A (enExample)
DE (1) DE102008035806B4 (enExample)
GB (1) GB2474170B (enExample)
TW (1) TW201017773A (enExample)
WO (1) WO2010014251A2 (enExample)

Cited By (1)

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JP2020031170A (ja) * 2018-08-24 2020-02-27 キオクシア株式会社 半導体装置

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US20110012177A1 (en) * 2009-07-20 2011-01-20 International Business Machines Corporation Nanostructure For Changing Electric Mobility
US8368125B2 (en) 2009-07-20 2013-02-05 International Business Machines Corporation Multiple orientation nanowires with gate stack stressors
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
US9263342B2 (en) * 2012-03-02 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a strained region
US8674447B2 (en) 2012-04-27 2014-03-18 International Business Machines Corporation Transistor with improved sigma-shaped embedded stressor and method of formation
US9165944B2 (en) 2013-10-07 2015-10-20 Globalfoundries Inc. Semiconductor device including SOI butted junction to reduce short-channel penalty
US10153371B2 (en) 2014-02-07 2018-12-11 Stmicroelectronics, Inc. Semiconductor device with fins including sidewall recesses
US9190516B2 (en) * 2014-02-21 2015-11-17 Globalfoundries Inc. Method for a uniform compressive strain layer and device thereof
US9190418B2 (en) 2014-03-18 2015-11-17 Globalfoundries U.S. 2 Llc Junction butting in SOI transistor with embedded source/drain
US9466718B2 (en) 2014-03-31 2016-10-11 Stmicroelectronics, Inc. Semiconductor device with fin and related methods
US10008568B2 (en) 2015-03-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9741853B2 (en) * 2015-10-29 2017-08-22 Globalfoundries Inc. Stress memorization techniques for transistor devices

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JP2002057118A (ja) * 2000-08-09 2002-02-22 Toshiba Corp 半導体装置とその製造方法
JP2006013428A (ja) * 2004-05-26 2006-01-12 Fujitsu Ltd 半導体装置の製造方法
JP2006013082A (ja) * 2004-06-24 2006-01-12 Fujitsu Ltd 半導体装置とその製造方法、及び半導体装置の評価方法
JP2006059843A (ja) * 2004-08-17 2006-03-02 Toshiba Corp 半導体装置とその製造方法
US20090026552A1 (en) * 2007-07-27 2009-01-29 Da Zhang Method for forming a transistor having gate dielectric protection and structure

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JPH10308361A (ja) * 1997-05-07 1998-11-17 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5877056A (en) * 1998-01-08 1999-03-02 Texas Instruments-Acer Incorporated Ultra-short channel recessed gate MOSFET with a buried contact
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JP2002057118A (ja) * 2000-08-09 2002-02-22 Toshiba Corp 半導体装置とその製造方法
JP2006013428A (ja) * 2004-05-26 2006-01-12 Fujitsu Ltd 半導体装置の製造方法
JP2006013082A (ja) * 2004-06-24 2006-01-12 Fujitsu Ltd 半導体装置とその製造方法、及び半導体装置の評価方法
JP2006059843A (ja) * 2004-08-17 2006-03-02 Toshiba Corp 半導体装置とその製造方法
US20090026552A1 (en) * 2007-07-27 2009-01-29 Da Zhang Method for forming a transistor having gate dielectric protection and structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020031170A (ja) * 2018-08-24 2020-02-27 キオクシア株式会社 半導体装置
JP7150524B2 (ja) 2018-08-24 2022-10-11 キオクシア株式会社 半導体装置

Also Published As

Publication number Publication date
DE102008035806B4 (de) 2010-06-10
WO2010014251A3 (en) 2010-04-08
GB2474170A (en) 2011-04-06
GB2474170B (en) 2012-08-22
DE102008035806A1 (de) 2010-02-04
KR20110046501A (ko) 2011-05-04
CN102105965A (zh) 2011-06-22
TW201017773A (en) 2010-05-01
GB201100855D0 (en) 2011-03-02
US20100025743A1 (en) 2010-02-04
WO2010014251A2 (en) 2010-02-04

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