JP2011530167A5 - - Google Patents

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Publication number
JP2011530167A5
JP2011530167A5 JP2011521127A JP2011521127A JP2011530167A5 JP 2011530167 A5 JP2011530167 A5 JP 2011530167A5 JP 2011521127 A JP2011521127 A JP 2011521127A JP 2011521127 A JP2011521127 A JP 2011521127A JP 2011530167 A5 JP2011530167 A5 JP 2011530167A5
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JP
Japan
Prior art keywords
drain
region
diffusion
forming
semiconductor region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011521127A
Other languages
English (en)
Japanese (ja)
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JP2011530167A (ja
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Publication date
Priority claimed from DE102008035806A external-priority patent/DE102008035806B4/de
Application filed filed Critical
Publication of JP2011530167A publication Critical patent/JP2011530167A/ja
Publication of JP2011530167A5 publication Critical patent/JP2011530167A5/ja
Pending legal-status Critical Current

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JP2011521127A 2008-07-31 2009-07-31 ホウ素閉じ込めを強化した埋め込みＳｉ／Ｇｅ材質を有するトランジスタ Pending JP2011530167A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008035806A DE102008035806B4 (de) 2008-07-31 2008-07-31 Herstellungsverfahren für ein Halbleiterbauelement bzw. einen Transistor mit eingebettetem Si/GE-Material mit einem verbesserten Boreinschluss sowie Transistor
DE102008035806.1 2008-07-31
US12/503,340 2009-07-15
US12/503,340 US20100025743A1 (en) 2008-07-31 2009-07-15 Transistor with embedded si/ge material having enhanced boron confinement
PCT/US2009/004425 WO2010014251A2 (en) 2008-07-31 2009-07-31 Transistor with embedded si/ge material having enhanced boron confinement

Publications (2)

Publication Number Publication Date
JP2011530167A JP2011530167A (ja) 2011-12-15
JP2011530167A5 true JP2011530167A5 (enExample) 2012-09-06

Family

ID=41461560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011521127A Pending JP2011530167A (ja) 2008-07-31 2009-07-31 ホウ素閉じ込めを強化した埋め込みＳｉ／Ｇｅ材質を有するトランジスタ

Country Status (8)

Country Link
US (1) US20100025743A1 (enExample)
JP (1) JP2011530167A (enExample)
KR (1) KR20110046501A (enExample)
CN (1) CN102105965A (enExample)
DE (1) DE102008035806B4 (enExample)
GB (1) GB2474170B (enExample)
TW (1) TW201017773A (enExample)
WO (1) WO2010014251A2 (enExample)

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US20110012177A1 (en) * 2009-07-20 2011-01-20 International Business Machines Corporation Nanostructure For Changing Electric Mobility
US8368125B2 (en) 2009-07-20 2013-02-05 International Business Machines Corporation Multiple orientation nanowires with gate stack stressors
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
US9263342B2 (en) * 2012-03-02 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a strained region
US8674447B2 (en) 2012-04-27 2014-03-18 International Business Machines Corporation Transistor with improved sigma-shaped embedded stressor and method of formation
US9165944B2 (en) 2013-10-07 2015-10-20 Globalfoundries Inc. Semiconductor device including SOI butted junction to reduce short-channel penalty
US10153371B2 (en) 2014-02-07 2018-12-11 Stmicroelectronics, Inc. Semiconductor device with fins including sidewall recesses
US9190516B2 (en) * 2014-02-21 2015-11-17 Globalfoundries Inc. Method for a uniform compressive strain layer and device thereof
US9190418B2 (en) 2014-03-18 2015-11-17 Globalfoundries U.S. 2 Llc Junction butting in SOI transistor with embedded source/drain
US9466718B2 (en) 2014-03-31 2016-10-11 Stmicroelectronics, Inc. Semiconductor device with fin and related methods
US10008568B2 (en) 2015-03-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9741853B2 (en) * 2015-10-29 2017-08-22 Globalfoundries Inc. Stress memorization techniques for transistor devices
JP7150524B2 (ja) * 2018-08-24 2022-10-11 キオクシア株式会社 半導体装置

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JPH10308361A (ja) * 1997-05-07 1998-11-17 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5877056A (en) * 1998-01-08 1999-03-02 Texas Instruments-Acer Incorporated Ultra-short channel recessed gate MOSFET with a buried contact
US6580639B1 (en) * 1999-08-10 2003-06-17 Advanced Micro Devices, Inc. Method of reducing program disturbs in NAND type flash memory devices
JP2002057118A (ja) * 2000-08-09 2002-02-22 Toshiba Corp 半導体装置とその製造方法
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
KR100588786B1 (ko) * 2003-09-18 2006-06-12 동부일렉트로닉스 주식회사 반도체 소자 제조방법
JP4375619B2 (ja) * 2004-05-26 2009-12-02 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4837902B2 (ja) * 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
JP2006059843A (ja) * 2004-08-17 2006-03-02 Toshiba Corp 半導体装置とその製造方法
US7314804B2 (en) * 2005-01-04 2008-01-01 Intel Corporation Plasma implantation of impurities in junction region recesses
US7407850B2 (en) * 2005-03-29 2008-08-05 Texas Instruments Incorporated N+ poly on high-k dielectric for semiconductor devices
US7892905B2 (en) * 2005-08-02 2011-02-22 Globalfoundries Singapore Pte. Ltd. Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing
US7612421B2 (en) * 2005-10-11 2009-11-03 Atmel Corporation Electronic device with dopant diffusion barrier and tunable work function and methods of making same
DE102005052055B3 (de) * 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
US7608515B2 (en) * 2006-02-14 2009-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for stressed semiconductor devices
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DE102006019835B4 (de) * 2006-04-28 2011-05-12 Advanced Micro Devices, Inc., Sunnyvale Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist
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US7625801B2 (en) * 2006-09-19 2009-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation with a pre-amorphous implant
DE102006046363B4 (de) * 2006-09-29 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Verringern von Kristalldefekten in Transistoren mit wieder aufgewachsenen flachen Übergängen durch geeignetes Auswählen von Kristallorientierungen
DE102007030053B4 (de) * 2007-06-29 2011-07-21 Advanced Micro Devices, Inc., Calif. Reduzieren der pn-Übergangskapazität in einem Transistor durch Absenken von Drain- und Source-Gebieten
US7927989B2 (en) * 2007-07-27 2011-04-19 Freescale Semiconductor, Inc. Method for forming a transistor having gate dielectric protection and structure

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