JP2011517104A - 基板によるチップの自己組立 - Google Patents
基板によるチップの自己組立 Download PDFInfo
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- JP2011517104A JP2011517104A JP2011503417A JP2011503417A JP2011517104A JP 2011517104 A JP2011517104 A JP 2011517104A JP 2011503417 A JP2011503417 A JP 2011503417A JP 2011503417 A JP2011503417 A JP 2011503417A JP 2011517104 A JP2011517104 A JP 2011517104A
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Abstract
Description
a) 上記で説明されたように、本発明による基板を準備するステップと、
b) 基板の疎水性領域と他方の親水性領域との間の湿潤性の差を利用する、準備された貼付け領域上でのチップのセルフアライメントのステップと、
c) 準備した領域上で位置合わせされたチップの、分子結合または熱圧着による組立のステップとを含むことができる。
− 基板または層2の表面2’は、均質または不均質であり、これを位置合わせおよび結合の目的で準備し、自己組立領域を用いて構成部品またはチップ3の位置合わせを実行して、次いでこの領域上の構成部品またはチップ3を結合によって組立させるために1つまたは複数の処理を受けていてよく、
− 基板の表面2’は、構成部品またはチップの結合の促進および/または領域12とその全周との間の湿潤性コントラストの強化を可能にする追加の層を備えることができる。
2 支持基板
2’ 表面
3 支持層
4 ビア
4−2 ビア
4’ パッド
5 相互接続パッド
5’ 相互接続パッド
5” 機能的結合
6 ビア
6−2 ビア
6’ パッド
7 層
7’ 層
9 層
9’ 層
12 貼付け領域
12’ 貼付け領域
13 滴下
14 接続パッド
15 表層
16 接続パッド
20 非晶質炭素層
20−1 接続
20−2 層
20’ 細長片
21’ 細長片
120 疎水性領域
120’ 疎水性領域
121 導体
201 層の一部分
202 層
300 構成部品
301 接触ピックアップ
Claims (20)
- 1つまたは複数の構成部品またはチップ(3、300)および基板(2)を組み立てる方法であって、
a) 前記基板(2)の表面(2’)上に、前記構成部品または前記チップ(3、300)の自己組立のための少なくとも1つの親水性貼付け領域(12、12’)および前記親水性貼付け領域の境界を定める疎水性領域(20)を形成するステップと、
b) 親水性の液体を滴下(13)することにより、前記貼付け領域(12、12’)上で前記構成部品または前記チップ(3)の位置合わせおよび組立が実行され、分子結合または熱圧着によって前記組立が実行されるステップとを含む方法。 - 少なくとも1つの親水性貼付け領域に、構成部品またはチップの結合または結合の支援のための層(8)を堆積するステップを含む請求項1に記載の方法。
- 前記貼付け領域(12)に酸化物層(15)を形成するステップをさらに含む請求項1または2に記載の方法。
- 前記基板(2)の前記表面(2’)が、最初に均質であるか、または最初に不均質である請求項1から3のいずれか一項に記載の方法。
- 前記基板(2)の前記表面(2’)が最初は不均質であり、少なくとも1つのパッド(4、6、4’、6’)および/または1つのビアおよび/または1つの接点が、前記基板(2)の前記表面(2’)と同一平面であり、電気的接続および/または光学的接続および/または熱的接続を保証し、前記パッド(4、6、4’、6’)および/またはビアおよび/または接点の少なくとも1つが、前記貼付け領域(12)内に局所化され得る請求項1から3のいずれか一項に記載の方法。
- 前記基板が、1つまたは複数の電気的および/または光学的および/または熱的な接続層(7、9、7’、9’)をさらに備える請求項4または5に記載の方法。
- 前記疎水性領域が、少なくとも部分的に1つの非晶質炭素領域を備える請求項1から6のいずれか一項に記載の方法。
- 前記疎水性の非晶質炭素領域が、薄膜(20)の形で生成される請求項7に記載の方法。
- 前記貼付け領域(12)が、前記疎水性の非晶質炭素領域(20)のエッチングによって境界を定められる請求項7または8に記載の方法。
- 前記非晶質炭素が、1つまたは複数の構成部品またはチップの組立の後に少なくとも部分的に除去される請求項7から9のいずれか一項に記載の方法。
- 前記非晶質炭素が、構成部品の少なくとも1つのパッドと基板表面との間に非晶質炭素の接続(20−1)を残しておくように部分的に除去される請求項10に記載の方法。
- 前記非晶質炭素の少なくとも部分的な除去の後、誘電材料または非晶質炭素の層(20−2)を堆積することにより、前記基板(2)上に組み立てられていない構成部品またはチップ(3)の前記面の高さに、あるいはこの面の上に、新しい平坦面を形成するステップを含む請求項10または11に記載の方法。
- 基板の前記表面を形成する前記新しい平坦面が、この面上に、少なくとも1つの親水性貼付け領域(12、12’)および前記親水性貼付け領域の境界を定める疎水性領域(20)の形成をさらに備える請求項12に記載の方法。
- 基板の表面を形成する前記新しい平坦面が、この新しい表面上に構成部品を組み立てる方法の実行をさらに含む請求項13に記載の方法。
- 前記疎水性領域が、例えばCu、Ag、Au、Al、Wの中から選択された金属で作製された1つの領域を少なくとも部分的に備える請求項1から14のいずれか一項に記載の方法。
- 前記金属が、前記基板の前記表面上に形成された1つまたは複数のアンテナあるいは前記基板の前記表面上に形成された1つまたは複数の導体である請求項15に記載の方法。
- 構成部品またはチップ(3)の位置合わせの前に、研磨および/または酸素プラズマによる処理ならびに/あるいはUVおよびオゾンでの処理を含み得る、この構成部品および/またはこのチップが組み立てられることになる前記表面の準備のステップを含む請求項1から16のいずれか一項に記載の方法。
- 前記構成部品および/または前記チップが、1つまたは複数の、パッド(5、14、16)および/またはビアおよび/または接点を備える請求項1から17のいずれか一項に記載の方法。
- 前記構成部品および/または前記チップが、低温溶解材料で作製された1つまたは複数の層(5’)を備える方法であって、前記材料を低温で溶解するステップをさらに含む請求項1から18のいずれか一項に記載の方法。
- 低温溶解材料製の接続(5”)が、前記構成部品の少なくとも1つのパッドと前記基板の前記表面との間に作製される請求項19に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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FR0852370A FR2929864B1 (fr) | 2008-04-09 | 2008-04-09 | Auto-assemblage de puces sur un substrat |
FR0852370 | 2008-04-09 | ||
PCT/EP2009/054115 WO2009124921A1 (fr) | 2008-04-09 | 2009-04-07 | Auto-assemblage de puces sur un substrat |
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JP2011517104A true JP2011517104A (ja) | 2011-05-26 |
JP5656825B2 JP5656825B2 (ja) | 2015-01-21 |
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US (1) | US8642391B2 (ja) |
EP (1) | EP2260508A1 (ja) |
JP (1) | JP5656825B2 (ja) |
FR (1) | FR2929864B1 (ja) |
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WO2017159401A1 (ja) * | 2016-03-17 | 2017-09-21 | 東京エレクトロン株式会社 | 液体を用いて基板に対するチップ部品のアライメントを行う方法 |
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JPWO2017159401A1 (ja) * | 2016-03-17 | 2018-12-27 | 東京エレクトロン株式会社 | 液体を用いて基板に対するチップ部品のアライメントを行う方法 |
KR102349884B1 (ko) | 2016-03-17 | 2022-01-12 | 도쿄엘렉트론가부시키가이샤 | 액체를 사용해서 기판에 대한 칩 부품의 얼라인먼트를 행하는 방법 |
Also Published As
Publication number | Publication date |
---|---|
US20110033976A1 (en) | 2011-02-10 |
US8642391B2 (en) | 2014-02-04 |
WO2009124921A1 (fr) | 2009-10-15 |
FR2929864A1 (fr) | 2009-10-16 |
JP5656825B2 (ja) | 2015-01-21 |
EP2260508A1 (fr) | 2010-12-15 |
FR2929864B1 (fr) | 2020-02-07 |
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