JP2011515839A - 半導体パッケージ用複合機能テープ及びこれを用いた半導体素子の製造方法 - Google Patents
半導体パッケージ用複合機能テープ及びこれを用いた半導体素子の製造方法 Download PDFInfo
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- JP2011515839A JP2011515839A JP2010550605A JP2010550605A JP2011515839A JP 2011515839 A JP2011515839 A JP 2011515839A JP 2010550605 A JP2010550605 A JP 2010550605A JP 2010550605 A JP2010550605 A JP 2010550605A JP 2011515839 A JP2011515839 A JP 2011515839A
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- Prior art keywords
- adhesive layer
- tape
- composite functional
- dicing
- semiconductor
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Classifications
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L24/27—Manufacturing methods
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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Abstract
【選択図】図2
Description
従来のパッケージング技術においては、多層チップ積層パッケージ(multi−chip package)(MCP)方法が主に用いられてきた。これは複数のチップを接着剤により互いに上下に積層し、チップをワイヤボンディングを用いて互いに電気的に連結する構造である。その結果、ワイヤボンディングのスペース分だけ、パッケージ全体の大きさが積層されたチップの体積より大きくなり、不必要な空間が存在した。
MCP方法およびWSP方法は、いずれも複数のチップを接着剤により接着して上下に積層する方式で、量的な側面から半導体デバイスの容量を増やす方法である。この中でMCP方法は、ワイヤボンディングによりチップとチップを電気的に連結するので、各チップは開放端の回路形成面を有し、その反対面(すなわち研削された面(ground side))に接着剤を塗布してチップを互いに連結するようになっている。
ところが、WSP方法は、ワイヤボンディングではなく、チップとチップを貫通電極により直接連結するので、チップの回路形成面に接着剤を塗布してチップを連結しなければならない。
本実施形態の複合機能テープ10の基材フィルム100について説明する。
本実施形態の複合機能テープ10を構成する紫外線硬化型粘着層100について説明する。
本実施形態に係る複合機能テープ10は、基材フィルム100上に粘着層110をコーティングし、粘着層110上に第1の(絶縁)接着層105が積層されている。
次に、複合機能テープ10の第2の(絶縁)接着層120について説明する。
次は、本発明の一実施形態による複合機能テープの保護フィルム6について説明する。
1.粘着層A−1製造
還流冷却器、温度計、ドロッピングパネルを備えた2L容量の4口フラスコに、エチルアセテート220g、トルエン150gを入れた。
アクリル樹脂WS−023(水酸基価あるいは酸価20mgKOH/g、Tg −5℃、平均分子量500,000、水酸基あるいはカルボキシル基含有量20、ナガセケムテックス社)260g、クレゾールノボラック型エポキシ樹脂YDCN−500−4P(分子量10,000以下、Kukdo Chemical社)120g、クレゾールノボラック型硬化剤MEH−7800SS(明和プラスチック産業社)40g、イミダゾール硬化促進剤2P4MZ(四国化学社)0.1g、メルカプトシランカップリング剤KBM−803(信越化学社)0.5g、エポキシシランカップリング剤KBM−303(信越化学社)0.5g及び無定形シリカ充填剤OX−50(Degussa社)20g、内在型粘着バインダーCA−100を8g、0.1gのIC−184(Ciba−Geigy社)を混合し、混合物を500rpmで2時間程度1次分散させた後、ミリングした。
アクリル樹脂SG−80H(重量平均分子量350,000、Tg7.5℃、ナガセケムテックス社)150g、クレゾールノボラック型エポキシ樹脂YDCN−500−90P(分子量10,000以下、Kukdo Chemical社)150g、クレゾールノボラック系硬化剤MEH−7800SS(明和プラスチック産業社)20g、イミダゾール硬化促進剤2P4MZ(四国化学社)0.8g、エポキシシランカップリング剤KBM−303(信越化学社)0.4g及び無定形シリカ充填剤OX−50(Degussa社)40gを混合し、混合物を500rpmで2時間程度1次分散させた後、ミリングした。
4.接着フィルムD−1製造
製造した粘着層A−1、第1の絶縁接着層B−1、第2の絶縁接着層C−1をラミネータを用いて順に積層させ、接着フィルムD−1を製造した。
1.粘着層a−1製造
アクリル粘着バインダーAT−4842(Tg −50℃、重量平均分子量600,000、Samwon Chemical社)100gに6官能ウレタンアクリレートU−324A(新中村社)80gを混合し、1gのポリイソシアネート硬化剤L−45(日本ポリウレタン社)および1.8gのIC−184(Ciba−Geigy社)を混合物に添加し、紫外線硬化型粘着組成物を製造した。製造した紫外線硬化型粘着組成物を38ミクロンのPET離型フィルムSRD−T38(Saehan Media社)の片面にアプリケータを用いて10ミクロンの厚さにコーティングし、80℃で2分間乾燥させた。さらに、100ミクロンのPOフィルムOD−100(Riken Technos社)に60℃の温度で積層後、40℃のオーブンで3日間エージングし、粘着層a−1を製造した。
比較例2は、第1の接着層の製造において、紫外線硬化剤(光開始剤)であるIC−184を添加していないことを除いて、実施例1と同様にして製造した。
1.第2の絶縁接着層c−1製造
アクリル樹脂KLS−1045(重量平均分子量750,000、Tg 30℃、藤倉社)150g、クレゾールノボラック型エポキシ樹脂YDCN−500−90P(分子量10,000以下、Kukdo Chemical社)150g、クレゾールノボラック系硬化剤MEH−7800SS(明和プラスチック産業社)20g、イミダゾール硬化促進剤2P4MZ(四国化学社)0.8g、エポキシシランカップリング剤KBM−303(信越化学社)0.4g及び無定形シリカ充填剤OX−50(Degussa社)40gを混合し、混合物を500rpmで2時間程度1次分散させた後、ミリングを実施した。
第2の絶縁接着層c−1を除いては、粘着層A−1および第1の接着フィルムB−1は、実施例1と同様の方法により製造し、製造した第2の絶縁接着層c−1、粘着層A−1および第1の接着層B−1を順にラミネータを用いて積層して接着フィルムd−3を製造した。
1.単一接着層c−2製造
アクリル樹脂WS−023(水酸基価あるいは酸価20mgKOH/g、Tg−5℃、平均分子量500,000、水酸基あるいはカルボキシル基含有量20、ナガセケムテックス社)150g、クレゾールノボラック型エポキシ樹脂YDCN−500−90P(分子量10,000以下、Kukdo Chemical社)150g、クレゾールノボラック硬化剤MEH−7800SS(明和プラスチック産業社)20g、イミダゾール硬化促進剤2P4MZ(四国化学社)0.8g、エポキシシランカップリング剤KBM−303(信越化学社)0.4g及び無定形シリカ充填剤OX−50(Degussa社)40gを混合し、混合物を500rpmで2時間程度1次分散させた後、ミリングした。
(1)ウエハの裏面研削性(BG)
実施例1及び比較例1〜4によって得られた接着フィルムを裏面研磨装置を用いて720ミクロンのウエハにマウントし、基材フィルムの裏面は80ミクロンの深さまで裏面研削した。試験結果は下記の通り判断した。
ウエハの損傷及びマイクロクラックの発生がある(×)
(2)粘着層および第1の絶縁接着層間の180°平均剥離力測定(UV硬化の前後)
180°剥離力試験は、JIS Z0237規格に基づいて実施した。
実施例及び比較例によって得られた接着フィルムから、保護フィルムを除去した後に、各接着フィルムを60℃で8インチウエハの一面にAaron社のMounter AR−08WMを用いてマウントした。
第1の絶縁接着層の破れ、脱離、伸長がある(×)
(4)マウント時のボイド、チッピング、チップクラック
実施例及び比較例を通じて得られた接着フィルムを、Aaron社のMounter AR−08WMを用いて、バンプが形成された8インチ80μm厚さのウエハの表面に60℃で熱圧着させた後、Nikon社の光学顕微鏡ME600Lを用いて表面のボイドの状態を観察した。
ボイド、チッピング、チップクラックがある(×)
(5)貯蔵弾性率
実施例及び比較例で得られた接着フィルム中、第2の絶縁接着層を厚さ200μm、幅7mm×長さ14mmに切断した後、DMA Q800(TA Instrument社)を用いて−10℃〜150℃に昇温速度4℃/minで温度を上げながら貯蔵弾性率を測定した。本試験では60℃のデータを採用した。
二酸化膜でコーティングがされている厚さ525μmのウエハを5mm×5mmの大きさに切った後、第1の絶縁接着層及び第2の絶縁接着層のみ60℃の条件でウエハに積層し、接着部分のみ残して切り落とした。
Claims (11)
- 基材フィルムの一面に形成された紫外線硬化型粘着層、前記粘着層上に形成される第1の接着層及び第2の接着層を備える複合機能テープであって、
複数の素子を有する半導体基板の素子形成面の反対面を研削する工程および研削された半導体基板面に紫外線硬化型粘着層が形成されたダイシングテープを用いて半導体基板をそれぞれのチップにダイシングする工程を行う間、前記複合機能テープは複数の素子形成面に接着され、前記複合機能テープの第1の接着層および第2の接着層は、前記ダイシングする工程により分離されたそれぞれのチップをピックアップしてダイアタッチする間、それぞれのチップに接着されていることを特徴とする半導体パッケージ用複合機能テープ。 - 基材フィルムの一面に形成された紫外線硬化型粘着層、前記粘着層上に形成される第1の接着層及び第2の接着層を備える複合機能テープであって、
複数の素子を有する半導体基板の素子形成面の反対面を研削する工程と、前記半導体基板をそれぞれのチップにダイシングする工程を行う間、前記複合機能テープは複数の素子を有する半導体基板の素子形成面に接着され前記ダイシングする工程により分離されたそれぞれのチップをピックアップしてダイアタッチする間、複合機能テープの前記第1の接着層と第2の接着層はそれぞれのチップに接着していることを特徴とする半導体パッケージ用複合機能テープ。 - 前記第1の接着層は、前記粘着層への紫外線照射後の粘着層および第2の接着層との剥離性を改善するために、粘着層と第2の接着層との間に介在し、紫外線硬化型質を含でいることを特徴とする請求項1又は2に記載の半導体パッケージ用複合機能テープ。
- 前記第1の接着層は、紫外線照射後の前記粘着層に対する180°平均剥離力が0.1N/25mm以下であることを特徴とする請求項1又は2に記載の半導体パッケージ用複合機能テープ。
- 前記第1の接着層および第2の接着層は、熱硬化型であることを特徴とする請求項1又は2に記載の半導体パッケージ用複合機能テープ。
- 前記第2の接着層は、60℃での貯蔵弾性率が0.1〜10MPaであることを特徴とする請求項1又は2に記載の半導体パッケージ用複合機能テープ。
- 基材フィルムの一面上の紫外線硬化型粘着層、前記粘着層上の第1の接着層及び第2の接着層を備える複合機能テープをバンプが形成された半導体基板に接着する工程と、
前記半導体基板の裏面を研削する工程と、
前記半導体基板の研削された面にダイシングテープを接着する工程と、
前記半導体基板をそれぞれのチップにダイシングする工程と、
ダイシングテープを除去して前記チップを前記第1の接着層と第2の接着層と結合した状態でピックアップする工程と、
前記第1の接着層及び第2の接着層が接着した前記チップをダイアタッチする工程と、
を含む半導体素子の製造方法。 - 基材フィルムの一面上の紫外線硬化型粘着層、前記粘着層上の第1の接着層及び第2の接着層を備える複合機能テープをバンプが形成された半導体基板に接着する工程と、
前記半導体基板の裏面を研削する工程と、
前記半導体基板をそれぞれのチップにダイシングする工程と、
前記第1の接着層および第2の接着層が接着された前記チップをピックアップする工程と、
前記チップを前記第1の接着層及び第2の接着層を用いてダイアタッチする工程と、
を含む半導体素子の製造方法。 - 前記ダイシングする工程後、ピックアップする工程前に、前記テープに紫外線を照射する工程をさらに含むことを特徴とする請求項7又は8に記載の半導体素子の製造方法。
- 前記ピックアップする工程前に前記ダイシングテープをエクスパンドし、ダイシングされた前記それぞれのチップの間隔を広げる工程をさらに含むことを特徴とする請求項7に記載の半導体素子の製造方法。
- 前記ピックアップする工程前に前記複合機能テープをエクスパンドし、ダイシングされた前記それぞれのチップの間隔を広げる工程をさらに含むことを特徴とする請求項8に記載の半導体素子の製造方法。
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PCT/KR2009/001264 WO2009113831A2 (ko) | 2008-03-14 | 2009-03-13 | 반도체 패키징용 복합기능 테이프 및 이를 이용한 반도체 소자의 제조방법 |
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US20100330780A1 (en) | 2010-12-30 |
TWI405272B (zh) | 2013-08-11 |
TW201001565A (en) | 2010-01-01 |
CN101971311A (zh) | 2011-02-09 |
KR20090098563A (ko) | 2009-09-17 |
CN101971311B (zh) | 2012-04-25 |
JP5436461B2 (ja) | 2014-03-05 |
KR100963675B1 (ko) | 2010-06-15 |
WO2009113831A3 (ko) | 2009-12-10 |
US8309219B2 (en) | 2012-11-13 |
WO2009113831A2 (ko) | 2009-09-17 |
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