JP2011507358A5 - - Google Patents

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JP2011507358A5
JP2011507358A5 JP2010537216A JP2010537216A JP2011507358A5 JP 2011507358 A5 JP2011507358 A5 JP 2011507358A5 JP 2010537216 A JP2010537216 A JP 2010537216A JP 2010537216 A JP2010537216 A JP 2010537216A JP 2011507358 A5 JP2011507358 A5 JP 2011507358A5
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clock signal
detecting
response
bit
data
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JP2010537216A
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JP2011507358A (ja
JP5523333B2 (ja
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Priority claimed from US12/168,091 external-priority patent/US8781053B2/en
Priority claimed from US12/325,074 external-priority patent/US8467486B2/en
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Publication of JP2011507358A5 publication Critical patent/JP2011507358A5/ja
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JP2010537216A 2007-12-14 2008-12-04 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法 Expired - Fee Related JP5523333B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US1378407P 2007-12-14 2007-12-14
US61/013,784 2007-12-14
US1990708P 2008-01-09 2008-01-09
US61/019,907 2008-01-09
US3960508P 2008-03-26 2008-03-26
US61/039,605 2008-03-26
US12/168,091 2008-07-04
US12/168,091 US8781053B2 (en) 2007-12-14 2008-07-04 Clock reproducing and timing method in a system having a plurality of devices
US12/325,074 US8467486B2 (en) 2007-12-14 2008-11-28 Memory controller with flexible data alignment to clock
US12/325,074 2008-11-28
PCT/CA2008/002108 WO2009076748A1 (en) 2007-12-14 2008-12-04 Clock reproducing and timing method in a system having a plurality of devices and memory controller with flexible data alignment

Related Child Applications (2)

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JP2011251459A Division JP5562922B2 (ja) 2007-12-14 2011-11-17 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法
JP2011272153A Division JP5432976B2 (ja) 2007-12-14 2011-12-13 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法

Publications (3)

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JP2011507358A JP2011507358A (ja) 2011-03-03
JP2011507358A5 true JP2011507358A5 (enExample) 2012-01-12
JP5523333B2 JP5523333B2 (ja) 2014-06-18

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JP2010537216A Expired - Fee Related JP5523333B2 (ja) 2007-12-14 2008-12-04 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法
JP2011251459A Expired - Fee Related JP5562922B2 (ja) 2007-12-14 2011-11-17 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法
JP2011272153A Expired - Fee Related JP5432976B2 (ja) 2007-12-14 2011-12-13 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法

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JP2011251459A Expired - Fee Related JP5562922B2 (ja) 2007-12-14 2011-11-17 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法
JP2011272153A Expired - Fee Related JP5432976B2 (ja) 2007-12-14 2011-12-13 複数のデバイスおよび柔軟なデータ整列を用いるメモリコントローラを有するシステムにおけるクロック再生およびタイミング方法

Country Status (7)

Country Link
US (3) US8467486B2 (enExample)
EP (1) EP2220766A4 (enExample)
JP (3) JP5523333B2 (enExample)
KR (2) KR101647849B1 (enExample)
CN (2) CN102623039B (enExample)
TW (1) TWI519077B (enExample)
WO (1) WO2009076748A1 (enExample)

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