WO2005033812A1 - シーケンス制御装置 - Google Patents
シーケンス制御装置 Download PDFInfo
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- WO2005033812A1 WO2005033812A1 PCT/JP2003/012778 JP0312778W WO2005033812A1 WO 2005033812 A1 WO2005033812 A1 WO 2005033812A1 JP 0312778 W JP0312778 W JP 0312778W WO 2005033812 A1 WO2005033812 A1 WO 2005033812A1
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- WIPO (PCT)
- Prior art keywords
- identification code
- start signal
- code assignment
- control device
- assignment
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1113—Address setting
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21034—Address I-O
Definitions
- the present invention relates to a sequence control device including a control device and a plurality of controlled devices.
- Sequence 1 to set the number (device number).
- a distributed control system is often constructed by configuring a sequence control device for controlling the control target equipment with one control device and a plurality of controlled devices. At this time, the number of paths connected to the controlled device is often several tens.
- Patent Document 1 in an electronic exchange system, device numbers are automatically set to a plurality of devices constituting the electronic exchange system.
- a reference device and a plurality of devices are serially connected by two signal lines, respectively, and the reference device has two basic signals A and B having a predetermined delay difference.
- the first device detects the delay difference between the basic signals A and B, sets the device number of the own device (first device) based on the detected delay difference, and receives the received basic signals A and B.
- the basic signals A and B to which a further predetermined delay difference is given To the second device via two signal lines.
- the second device detects the delay difference between the received basic signals A and B to which the further delay difference is added, and sets the device number of the own device (the second device) based on the detected delay difference.
- a predetermined delay difference is further provided to the received basic signals A and B, and the basic signals A and B to which the delay difference has been added are transmitted to the third device via two signal lines.
- the third, fourth,... Devices perform similar processing.
- the device number of the reference device is “1”, and the delay difference for two clocks is determined to correspond to the numerical value “1 J.”
- the basic signals A and B sent from the reference device 1 have a delay difference of four clocks.
- the first device receives the basic signals A and B, sets its own device number to “2”, and adds a further delay difference to A and B to the basic signal.
- basic signals A and B having a delay difference of 6 clocks are sent to the second device.
- the second device that receives the basic signals A and B with a delay difference of 6 clocks sets the device number of its own device to “3” and adds a further delay difference to A and B to the basic signal.
- basic signals A and B with a delay difference of 8 clocks are sent to the third device.
- Such an error detection unit for the basic signal can be omitted by making it common with the data transmission unit.However, when adding a controlled device to the sequence control unit, wait until the end of data transmission to identify the unit. There is a problem that the identification code assignment process must be performed by performing the code assignment process or by interrupting the data transmission, and the identification code assignment process cannot be performed during the data transmission.
- the present invention has been made in view of the above, and an object of the present invention is to provide a low-cost sequence control device without erroneously assigning an identification code due to the influence of noise.
- Patent Document 1 Japanese Patent Application Laid-Open No. Sho 644-68862 Disclosure of the Invention
- the control device includes a first transmission unit that outputs a first identification code application start signal that simultaneously notifies all controlled devices that the application of the identification code is to be started, A second identification code application start signal for notifying the controlled device connected adjacent to the own device that the application of the identification code is started and an identification code application for notifying the end of the application of the identification code.
- a second transmission unit that outputs an end signal, wherein each of the controlled devices is an identification code for detecting the first and second identification code assignment start signals and the identification code assignment end signal.
- an identification code is assigned based on the first identification code assigned to the own device.
- Identification code assigning means And a third transmitting means for notifying the controlled device of the subsequent stage of the separate code addition start signal and the identification code addition end signal.
- each of the controlled devices is simultaneously notified by the first identification code assignment start signal that the first transmitting means of the control device starts the operation of assigning the identification code
- the second transmission means of the control device is The transmitting means notifies only the controlled device adjacent to the control device of the second identification code assignment start signal.
- FIG. 1 is a block diagram showing a configuration of a sequence control device according to the present embodiment of the present invention
- FIG. 2 is a circuit diagram showing a detailed configuration of a controlled device shown in FIG.
- FIG. 3 is an example of a timing chart in which the sequence control device assigns two identification codes to a controlled device adjacent to the control device.
- FIG. 4 is a timing chart in which the sequence control device is adjacent to the controlled device. This is an example of a timing chart in which one identification code is assigned to each of them.
- FIG. 1 is a block diagram showing a configuration of a sequence control device according to the present embodiment of the present invention.
- the sequence control device according to the present embodiment of the present invention includes a control device 10 and n (n is a natural number) controlled devices 21 to 2 n.
- the controlled device 21 is the first controlled device from the control device 10
- the controlled device 22 is the second controlled device from the control device 10,...,
- the control device 10 transmits a first identification code assignment start signal for notifying the controlled devices 21 to 2n of the start of the identification code assignment via a data transmission communication path. In addition, the control device 10 notifies the first controlled device 21 adjacent to the own device of the start of the individual identification code assignment via a transmission path different from the data transmission communication path. A second identification code assignment start signal and an identification code assignment end signal for notifying the end of the assignment of the identification code are output.
- the control device 10 includes a timing generation section 120, a transmission section 100 (first transmission means in the claims), and a clock section 110 (clock in the claims). Means) and a delay unit 130 (second transmitting means in the claims).
- the timing generation section 120 generates an identification code assignment signal (identification code assignment start signal and identification code assignment end signal) for controlling the timing of assigning an identification code to the controlled devices 21 to 2n.
- the timing generation section 120 outputs an identification code assignment start signal to the transmission section 101, the clock section 110, and the delay section 130 via the transmission path 122. Further, when the timing generation section 120 receives from the clock section 110 via the transmission path 111 a notification indicating that the identification code addition time has elapsed, the timing generation section 120 via the transmission path 121 An identification code addition end signal is output to delay section 130.
- the transmission unit 100 transmits the identification code assignment start signal input from the identification code assignment timing generation unit 120 via the transmission path 121 to the controlled devices 21 to 2 via the communication path 101. Send to n. Specifically, for example, the transmission delay between units in data transmission is set to be within an error range, and the transmission method is determined so that modulation and demodulation codes are always performed at a fixed timing. Then, the transmitting unit 100 generates a frame in which each of the receiving units 200 of the controlled devices 21 to 2 n has given a code that can be recognized as a specific frame, and generates one of the data of the data transfer. Transmits the first identification code addition start signal as a part.
- the transmission unit 100 when transmitting the first identification code assignment start signal as a part of data, the transmission unit 100 outputs the first identification code assignment start signal to the controlled device 21 adjacent to the first identification code assignment start signal.
- the time relationship with the second identification code assignment start signal is adjusted. Specifically, the second identification code starts to be supplied to the controlled device 21 before the timing at which the controlled device 21 to 2 n acquires the first identification code addition start signal from a part of the data received.
- the data including the first identification code assignment start signal is delayed by a predetermined time from the timing of the second identification code assignment start signal output by the delay unit 130, and is transmitted through the communication path. Output to 101.
- the delay unit 130 adjusts the timing of the identification code assignment signal input via the transmission path 122. Specifically, a part of the data received by the controlled devices 21 to 2 ⁇ ⁇ the second identification code assignment start signal to the controlled device 21 after the timing of acquiring the first identification code assignment start signal. In this case, the delay unit 130 delays the identification code addition start signal by a predetermined time. Then, it outputs to the controlled device 21 a second identification code assignment start signal obtained by delaying the identification code assignment start signal by a predetermined time. The second identification code assignment start signal was output to the controlled device 21 shortly after the controlled device 21 to 2 ⁇ obtained the first identification code assignment start signal from a part of the received data.
- the delay unit 130 passes the input identification code assignment start signal and identification code assignment end signal through and outputs them to the controlled device 21. That is, the delay unit 130, together with the transmission unit 100, starts the first identification code assignment start signal for the controlled devices 21 to 2 ⁇ and the second identification code assignment start output to the controlled device 21. Adjust the timing with the signal.
- the second identification code assignment start signal output to the controlled device 21 is input to the level detection unit 240 via the identification code assignment timing input 243 of the controlled device 21.
- the clock unit 110 measures the time required to assign an identification code to the controlled devices 21 to 2 ⁇ . More specifically, the measurement starts when an identification code addition start signal is input from the timing generation section 120 via the transmission path 122. When the time required for assigning the identification code to the controlled devices 21 to 2 ⁇ elapses, the end of the identification code assignment for notifying that the identification code assignment time has elapsed via the transmission path 111 is determined. Output to generator 120. Each of the controlled devices 21 to 2n assigns an identification code when receiving the first identification code assignment start signal and the second identification code assignment start signal for its own device.
- the controlled devices 2l to 2n When the controlled devices 2l to 2n receive the second identification code assignment start signal for the own device, the controlled devices 2l to 2n delay the second identification code assignment start signal by a time corresponding to the number of identification codes for the own device. Then, it outputs the delayed second identification code addition start signal to a controlled device adjacent to the control device 10 farther from the own device than the own device (hereinafter, referred to as a subsequent controlled device).
- the controlled devices 21 to 2n receive the identification code assignment end signal, they output an identification code assignment end signal to the controlled device at the subsequent stage. In other words, the controlled devices 21 to 2n assign an identification code to their own devices, and sequentially transmit a second identification code assignment start signal and an identification code assignment end signal to a subsequent controlled device.
- the controlled devices 21 to 2 n all have the same function. Here, a detailed configuration will be described using the controlled device 21 as an example.
- the controlled device 21 includes a receiving section 200 (identification code adding signal detecting means in the claims), a clock section 210, and a delay section 230 (in the claims). (A third transmitting means), a level detecting section 240 (identification code adding time detecting means in the claims), and an ID adding section 250 (identification code adding in the claims) Means).
- the receiving unit 200 receives the data transmitted from the transmitting unit 100 of the control device 10 via the communication path 101, and acquires a first identification code assignment start signal. Specifically, a first identification code assignment start signal is obtained by receiving a frame that has been given a code that can be recognized as a certain unique frame transmitted by the transmission unit 100 of the control device 10. The receiving unit 200 outputs a start timing acquisition signal indicating that the first identification code assignment start signal has been acquired to the clock unit 210 and the level detection unit 240 via the transmission path 201. You.
- the clock unit 210 When a start time acquisition signal is input via the transmission path 201, the clock unit 210 initializes the force value and starts counting up from zero. Then, the count value 211 from the identification code application start signal is output to the ID application section 250.
- the upper limit of the count-up of the clock section 210 is the value of the identification code given by the sequence controller. When the count value exceeds the upper limit value, the clock unit 110 outputs excess information notifying that overflow has occurred to the level detection unit 240.
- the clock unit 210 outputs the count-up interval to the level detection unit 240 and the delay unit 230 as the count-up timing 212.
- the count-up interval is set to be equal to or longer than the error detection width of data transmission.
- a coding technique such as a cyclic code has been used for error detection of data transmission.
- error detection using a cyclic code there is a maximum value at which a continuous error can be detected for each coding method, and an error of a bit continuous beyond a certain value cannot be detected.
- the maximum time for error detection can be calculated by multiplying the maximum number of bits that can detect consecutive errors by the time required for 1-bit transmission.
- the maximum time during which the error can be detected is defined as an error detection width.
- the counter up-timing 2 12 is used for the data transmission of the data transmission by a simple method when the control device 10 of the sequence control device of the present invention assigns an identification code to the controlled devices 21 to 2 n. If a data error occurs within the time guaranteed by the error detection, it is used to interrupt the assignment of the identification code.
- the level detection unit 240 includes a start timing acquisition signal input via the transmission path 201, and a second identification code start and identification input from the identification code assignment timing input 243 of the own device. From the sign assignment end signal, an identification sign assignment state 1 timing 2 41 and an identification sign assignment state 2 timing 2 42 are generated. The identification code assignment status 1 timing 2 41 notifies the end of the assignment of the identification code, and the identification code assignment status 2 timing 2 42 is the number of the first identification code of the identification code assigned to the own device. Notification of the timing for determining The level detection unit 240 outputs the identification code assignment state 1 timing 2 41 to the delay unit 230 and the identification code assignment state 2 timing 2 42 to the ID assignment unit 250 and the delay unit 230. I do.
- the level detection unit 240 detects a level change due to noise between the time when the start time acquisition signal and the second identification code assignment start signal of the own device are received and the identification code assignment end signal is detected.
- the assignment of the identification code is completed according to the identification code assignment state 1 timing 2 41 (interruption) To the delay unit 230.
- the delay unit 230 outputs the identification code assignment state 2 timing 2 42 which is delayed according to the value of the identification code assigned to the own device in units of the count-up timing 212, and outputs the identification code assignment timing 2 3 1 Output to The identification code assignment state 2 after the delay 2 timing 2 42 is transmitted to the subsequent controlled device and the ID assigning section 250 (the signal transmitted to the subsequent controlled device is transmitted to the subsequent controlled device). This is the second identification code assignment start signal for). Also, when the end of the assignment of the identification code is notified from the level detection circuit 240 by the identification code assignment state 1 timing 2 41, the delay unit 230 immediately proceeds to the identification code assignment state 2 timing 2 4 The delay processing of step 2 is interrupted, and the end of the identification code is immediately output to the identification code addition timing output 2 31.
- the ID assigning unit 250 latches the count value 211 in accordance with the identification code assignment state 2 timing 242 and completes the identification code assignment in accordance with the identification code assignment state 1 timing 241.
- FIG. 2 is an example of a circuit diagram showing a detailed configuration of the controlled device 21 shown in FIG.
- the receiving unit 200 receives the data transmitted from the transmitting unit 100 of the control device 10 via the communication path 101, and acquires a first identification code assignment start signal.
- the receiving unit 200 sends a start timing acquisition signal indicating that the first identification code assignment start signal has been acquired via the transmission path 201 to the CLR terminal of the counter 21 3 and the one-shot circuit 24 Output to 4 clock terminal.
- the clock unit 210 includes a transmitter 214 and a counter 213.
- the oscillator 214 outputs pulses (system clock) at fixed time intervals to the clock terminal of the counter 211.
- the counter 2 13 When the start timing acquisition signal is input, the counter 2 13 initializes the count value 2 11 (sets the count value to “0”) and counts the number of system clocks generated by the oscillator 2 14. Count.
- the counter 21.3 outputs a predetermined upper bit in the binary number of the count value to the data terminal of the flip-flop 251, as the count value 211.
- the counter 2 1 3 counts the count value output as the count value 2 1 1
- the output one digit lower than the predetermined high-order bit in the binary number is counted up timing 2 12 as flip-flops 2 46, 2 32 2-1 to 2 32-m (0 ⁇ m, m is an integer), 2 33 Output to 3 clock pin.
- a pulse having a cycle equal to the interval at which the count value 2 11 counts up is set as the count-up timing 2 12, and the flip-flop 2 4 6, 2 3 2-l to 2 3 2-m (0 ⁇ m, m Are integers) and output to the 2 3 3 clock terminals.
- the upper limit of the count value of the counter 2 13 is equal to the value of the identification code given by the sequence controller.If the count value exceeds the upper limit, the count value of the counter 2 13 has overflowed. Is output to the CLR 2 terminal of the one-shot circuit 2'44.
- the level detection unit 240 includes a pinion circuit 244, an OR gate 245 as a logical sum, and a flip-flop 246.
- the one-shot circuit 244 holds the start timing acquisition signal input via the transmission path 201 as start information, and when the identification code assignment end signal is input, the excess information is output from the counter 213. If it has been input, or the identification code addition end signal input from its own device identification code addition timing input 24, the start information is deleted.
- the one-shot circuit 244 outputs the start information to the OR gate 245 in negative logic. In other words, the one-shot circuit 244 keeps the output at "L" while holding the woman's table information.
- the OR gate 245 includes a start information input from the one-shot circuit 244, a self-apparatus second identification code addition start signal and an identification code notified via the identification code addition timing input 243. Based on the assignment end signal and the identification code assignment state 1 timing 2 41 1 is set to flip-flop 2 4 6, 2 3 2-1 to 2 3 2-m, 2 3 3 SET terminal and flip-flop 2 4 Output to 6 clock terminal. Specifically, in the OR gate 245, the one-shot circuit 244 holds the start information, and the second identification code start signal of its own device (in this case, negative logic "L" is input).
- Timing 2 41 is set to “L”, the one-shot circuit 244 erases the start information, or when the identification code addition end signal is input ( In this case, "H” is input.) Identification code assignment state 1 Timing 2 41 is set to "H”.
- the flip-flop 246 delays the identification code assignment state 1 timing 241 by the count-up timing 221. If the end of the identification code addition signal does not come from the OR gate 245 before this time elapses, it is determined that the ID assignment is normal, and that the identification code assignment has transitioned to the next state.
- the clock is output to the clock terminal of flip-flop 251, and the clock terminal of flip-flop 2 322-1. In this case, the flip-flop 246 sets the identification code assignment state 2 timing 242 to "L" to notify that the state has transitioned.
- the delay unit 230 includes a delay circuit 232 and a flip-flop 233.
- the delay circuit 2 32 has a number of flip-flops 2 3 2— :! 22 32 —m, and the flip-flop 2 is delayed by the number of power-up timings 2 12 corresponding to the number of identification codes for assigning the identification code assignment state 2 timing 2 42 as the identification code of the own device. 3 Output to 3 data input.
- the controlled devices 2l to 2n determine the number of identification codes required for their own device in advance, and determine the number of flip-flops of the delay circuit according to the number of required identification codes. For example, if the required number of identification codes is 1, the number of flip-flops in the delay circuit 2 32 is 0, and the delay circuit 2 32 is not required. Further, when the number of necessary identification codes is 3, the number of flip-flops of the delay circuit 2 32 is 2, and the delay circuit 2 32 includes flip-flops 2 3 2-1 and 2 3 2-2.
- the flip-flop 233 which is a half-cycle delay circuit, delays the output of the delay circuit 232 by a half cycle of the power-up timing 221 and shifts the identification code addition timing 231 to the register 252. Output to the LOAD terminal and the controlled device at the subsequent stage.
- the identification code assignment timing 2 31 is a timing for assigning the identification code of the own device and a second identification code assignment start signal of the subsequent controlled device.
- the ID assignment unit 250 includes a flip-flop 251, which is an ID assignment flip-flop, and a register 252, which is an ID assignment register.
- Flip-flop The register 2 1 1 latches the count value 2 1 1 of the counter 2 1 3 according to the identification code addition state 2 timing 2 42 output at the timing when the identification code addition is recognized to be normal, and 5 Output to 2.
- the count value latched by the flip-flop 25 1 is the leading identification code given to the controlled device.
- the register 252 obtains an identification code assignment end signal from the identification code assignment timing output 231 of the controlled device, and holds the count value latched by the flip-flop 251 at the end of the identification code assignment.
- the count value held by the register 255 is the leading identification code assigned to the own device, but the number of identification codes required by the own device is predetermined as described above. Therefore, all IDs can be given by retaining the leading identification code. For example, if the number of flip-flops in the delay circuit 232 is two, the number of flip-flops in the delay circuit 232 is the number obtained by subtracting 1 from the number of necessary identification codes. The number of codes is three. Therefore, if "3" is held in register 25, ID can be calculated as "3", "4", or "5".
- the timing generation unit 120 of the control device 10 outputs an identification code assignment start signal to the transmission unit 100, the clock unit 110, and the delay unit 130 via the transmission path 122. .
- the clock unit 110 starts measuring the time required to assign an identification code to the controlled device 2:!
- the transmitting section 100 generates a frame including the first identification code addition start signal, and transmits the generated frame to the communication path 101 as a part of data for data transfer.
- the delay unit 130 adjusts the timing of the identification code addition start signal, and outputs a second identification code addition start signal to the controlled device 21 in contact with the P.
- the second identification code assignment start signal is input to the level detection unit 240 of the controlled device 21 via the transmission path 243 of the controlled device 21.
- the receiving unit 200 of the controlled device 21 sends the control device 10 via the communication path 101
- the data transmitted from the communication unit 100 is received, and a first identification code assignment start signal is obtained.
- the receiving unit 200 of the controlled device 21 receives, via the transmission path 201 of the controlled device 21, a start timing acquisition signal indicating that the first identification code assignment start signal has been acquired, by the controlled device 2. 1 to the clock section 210 and the level detection section 240 of the controlled device 21.
- the clock unit 210 of the controlled device 21 initializes the count value when the start timing acquisition signal is input, and starts counting up from zero.
- the controlled devices 22 to 2n receive the data transmitted from the transmission unit 100 of the control device 10 via the communication path 101 similarly to the controlled device 21 and count up. Start.
- the level detection unit 240 of the controlled device 21 receives the identification code application state 2 at the count-up timing 2 1 2 immediately after the start time acquisition signal is input and the second identification code application start is input. Generate timing 2 4 2. More specifically, after the count value 2 11 of the clock unit 2 10 of the controlled device 21 has counted up, it is delayed by a half cycle of the count-up interval to generate the identification code assignment state 2 timing 2 42. You.
- the level detection unit 240 of the controlled device 21 outputs the identification code assignment state 2 timing 242 to the delay unit 230 and the ID assignment unit 250 of the controlled device 21.
- the ID assigning unit 250 of the controlled device 21 temporarily holds the count value 2 1 1 of the clock unit 210 of the controlled device 21. .
- the controlled device 22 to 2n has not input the start of the second identification code application to each controlled device. Therefore, since the level detection units 240 of the controlled devices 22 to 2n do not generate the identification code addition state 2 timing 212, the ID addition unit 250 does not perform temporary holding. That is, only the clock unit 210 of each of the controlled devices 22 to 2 n performs the counting operation.
- the delay unit 2 30 of the controlled device 21 has a count-up timing 2 1, which is a number obtained by subtracting 1 from the number of identification codes for giving the identification code assignment state 2 timing 2 42 to the own device. Delay by 2 cycles.
- the delay unit 230 of the controlled device 21 further delays the identification code assignment state 2 timing 2 42 after the delay by a half cycle of the count-up timing 2 1 2 to reduce the identification code assignment timing 2 31. Generate. Delayed part 2 of controlled device 2 1
- the ID addition unit 250 of the controlled device 21 holds the count value held by one block as the identification code.
- the delay unit 230 of the controlled device 21 causes the ID assigning unit 250 of the controlled device 21 to reduce the count value 211 by one.
- the identification code assignment timing 2 31 is generated by delaying the timing 2 42 that is held when the timing 2 42 is counted up by a half cycle of the count-up timing 2 12. Therefore, after the ID assigning unit 250 of the controlled device 21 temporarily holds the count value 211, a half cycle of the power-up timing 211 is assigned an identification code to the controlled device 21. At the same time, the operation of assigning the identification code of the controlled device 22 is started.
- the delay unit 230 of the controlled device 21 sends the count value 211 to the ID assigning unit 250 of the controlled device 21.
- the identification code assignment timing 2 31 is generated by delaying the temporarily held identification code assignment state 2 timing 2 42 by 1.5 cycles of the count-up timing 2 1 2. Therefore, the ID code is assigned to the controlled device 21 after 1.5 cycles of the power-up timing 2 112 after the ID assigning unit 250 of the controlled device 21 temporarily holds the count value 211. Is given, and the operation of giving the identification code of the controlled device 22 is started. It is assumed that the number of identification codes assigned by each of the controlled devices 2 l to 2 n is set in advance before the operation of assigning identification codes.
- the controlled device 2 1 has its own count value 2 1 1 subtracted 1 from the number of identification codes given by its own device from the value of the force value 2 1 1 held by its own ID assigning unit 250. At the timing of counting up by the number, It outputs a second identification code assignment start signal to controlled device 22.
- the controlled device 2 1 When the self-count value 2 11 changes from “0” to “1”, a second identification code assignment start signal is output to the controlled device 22.
- the controlled device 2 1 Outputs the second identification code assignment start signal to the controlled device 22 when the self-count value 2 1 1 changes from “1” to “2”.
- the clock unit of the controlled device 22 Since the controlled device 22 has already obtained the identification code adding time from the data transmitted by the transmitting unit 100 of the control device 10 via the communication path 101, the clock unit of the controlled device 22 has At 210, the force increase from the mouth starts at the same time as the clock section 210 of the controlled device 21. Therefore, when the second identification code assignment start signal is input from the controlled device 2.1 to the level detection section 240 of the controlled device 22, the count value 2 1 1 of the controlled device 22 becomes the controlled value. This is a value obtained by adding the number of the identification code assigned to the controlled device 21 to the value indicating the leading identification code assigned to the device 21.
- the level detection unit 2 40 0 of the controlled device 22 The count value 2 1 1 when the second identification code addition start signal is input to “2” is “2”.
- the controlled device 22 2 performs the same operation as the above-described controlled device 21, assigns an identification code to its own device, and outputs a second identification code assignment start signal to the next controlled device. I do.
- the n controlled devices 2 l to 2 n perform the same operation as the above-described controlled device 21 in the order in which they are connected near the control device 10, and give their own devices an identification code.
- the clock unit 110 of the control device 10 is controlled by the controlled device 2 :! from when the identification code assignment start signal is input from the timing generation unit 120. Measurement of the time required to assign an identification code to ⁇ 2n has begun. Assigning an identification code to the controlled devices 2 1 to 2 n When the time required for the elapse of the time elapses, the clock unit 110 outputs, to the timing generation unit 120 via the transmission path 111, the end of the identification code addition notifying that the identification code addition time has elapsed.
- the timing generation section 120 When the end of the identification code addition is notified, the timing generation section 120 outputs an identification code addition end signal to the delay section 130 via the transmission path 122.
- the delay section 130 passes the identification code addition end signal through and outputs the signal to the controlled apparatus 21.
- the identification code assignment end signal output from the delay unit 130 is input to the level detection unit 240 via the identification code assignment timing input 243 of the controlled device 21.
- the level detection unit 240 of the controlled device 21 Upon detecting the identification code addition end signal, the level detection unit 240 of the controlled device 21 outputs the identification code addition end signal to the delay unit 230 of the own device immediately and detects the start information based on the start information acquisition signal. to erase. Upon detecting the identification code addition end signal, the delay unit 230 of the controlled device 21 outputs an identification code addition end signal to the identification code addition timing input 24 3 of the controlled device 22 immediately after detecting the identification code addition end signal.
- the controlled devices 22 to 2 n repeat the same operation as that of the controlled device 21 when receiving the identification code assignment end signal from the identification code assignment timing input 24 3 of the own device, and assign the identification code.
- An end signal is sequentially transmitted, and an identification code assignment end signal is transmitted to all controlled devices.
- the second identification code assignment start signal for the subsequent controlled device is a signal obtained by delaying the identification code assignment state 2 timing 242, so that the controlled device has the second identification code for the subsequent controlled device. It does not output the identification code addition start signal.
- Receiving section 200 receives the data transmitted from transmitting section 100 of control device 10 and acquires a first identification code addition start signal.
- the receiving unit 200 sends a start timing acquisition signal indicating that the identification code assignment start signal has been acquired via the transmission path 201 to the CLR terminal of the counter 211 and the clock terminal of the one-shot circuit 244. Output. 'When the start time acquisition signal is input to the CLR pin, the counter 2 13 sets the count value 2 11 to "0" and then starts counting the number of system clocks generated by the oscillator 2 14 I do.
- the one-shot circuit 244 holds the start time acquisition signal as start information when the signal is input. Then, while holding the start information, the one-shot circuit 244 sets the output to "L” and outputs the output to the OR gate 245.
- the OR gate 245 is provided when the one-shot circuit 244 holds the start information, and when the one-shot circuit 244 receives the second identification code assignment start signal (in this case, negative logic “L” is input) of the own device.
- Identification code assignment state 1 Timing 2 4 1 is set to "L”.
- the flip-flop 246 latches the identification code assignment state 1 timing 241 with a half cycle delay from the change point of the count value 211 and outputs it as the identification code assignment state 2 timing 242.
- the flip-flop 25 1 latches and temporarily holds the count value 2 11 of the counter 2 13 according to the identification code assignment state 2 timing 2 42.
- the delay circuit 2 32 composed of 2 2 3 2-m is a power-up timing 2 1 2 corresponding to the number of identification codes for giving the identification giving state 2 timing 2 42 as the identification code of the own device. Delay by the number of.
- the flip-flop 2 43 delays the delayed identification assignment state 2 timing 2 42 by a further half cycle of the count-up timing 2 12, and shifts the identification code assignment timing 2 3 1 to the register 25 2 and the subsequent stage. Output to the controlled device.
- the register 25 2 holds the count value held in the flip-flop 25 1 by the identification code provision timing 2 31. That is, the top identification code assigned to the own device is held. Then, based on the held leading identification code, The identification code of the own device is given.
- the one-shot circuit 2 4 4 To delete That is, the output of the one-shot circuit 244 is set to "H".
- the flip-flops 2 4 6, 2 3 2-1 to 2 3 2-m, 2 3 3 suspend the delay operation by the identification code assignment state 1 timing 2 41, and enter the initial state. As a result, the assignment of the identification code is interrupted. Then, the flip-flop 233 immediately outputs the end of the identification code assignment to the identification code assignment timing input 243 of the subsequent controlled device.
- FIG. 3 is an example of a timing chart of the controlled device 21 when the sequence control device assigns identification codes “0” and “1” to the controlled device 21
- FIG. 5 is an example of a timing chart of the controlled device 22 when the control device 10 assigns identification codes “0” and “1” to the controlled device 21 and identification code “2” to the controlled device 22.
- the timing at which the identification code assignment timing input 24 3 changes from “H” to “L” is the second identification code assignment start signal.
- Device 22 is different from 2.
- “0” is assigned to the controlled device 21 as the first identification code
- “2” is assigned to the controlled device 22 as the first identification code.
- the timing at which the identification code assignment timing input 2 43 changes from “ ⁇ ” to “L” is the second identification code assignment start signal, and the timing at which “L” changes to “ ⁇ ” is the identification code assignment.
- An end signal is shown. That is, the identification code assignment timing input 243 indicates “L” in a period from the second identification code assignment start signal to the own apparatus to the identification code assignment end signal.
- a period in which the transmission path 201 is “ ⁇ ” is a start time acquisition signal indicating that the receiver 200 has detected the first identification code addition start signal.
- the one-shot circuit 244 changes the output to “L”. That is, the one-shot circuit 244 indicates that the output is set to “L” to hold the start information, and the output is set to “ ⁇ ” to erase the start information.
- the identification code assignment state 1 timing 2 41 is determined by the time from when the one-shot circuit 244 holds the start information and acquires the second identification code assignment start signal until the end of the identification code assignment is acquired.
- the device identification code application period is indicated by "L".
- the identification code assignment state 2 timing 2 42 becomes “L” after the count value 2 1 1 indicates the first identification code assigned to the own device, and is delayed by a half cycle of the count-up timing 2 1 2 .
- the identification code assignment state 2 timing 2 42 changes from “ ⁇ ” to “L”
- the flip-flop 25 1 latches and temporarily holds the first identification code assigned to its own device.
- the point at which the identification code assignment timing output 2 3 1 changes from “ ⁇ ” power to “L” is the second identification code assignment start signal for the subsequent controlled device, and changes from “L” to “ ⁇ ”. The point is the identification code assignment end signal for the subsequent controlled device.
- the control device 10 periodically transmits information such as control data to the controlled devices 21 to 2n-1 to which the identification code has already been assigned via the communication path 101.
- the control device 10 transmits the data of the data to be transferred only once during communication with the controlled devices 21 to 2n-1. It transmits a first identification code assignment start signal as a unit. Further, the control device 10 outputs a second identification code assignment start signal to the adjacent controlled device 21.
- the controlled devices 21 to 2n-1 perform the operation of assigning the identification code again.
- the controlled devices 21 to 2n-1 sequentially transmit the second identification code assignment start signal to the subsequent controlled device, and assign the identification code to the added controlled device n. That is, the operation of assigning the identification code is, for example, the case where the sequence control device is powered on and the identification code is assigned to the controlled devices 21 to 2 n even when the controlled device n is newly added. The operation is the same. .
- control device 10 restarts the steady data transmission via the communication path 101, and the controlled device is also controlled while the identification code is assigned. 2 Transmit data to 1-2n.
- the control device transmits the first identification code assignment start signal to all the controlled devices only once at the same time. Therefore, the timing of the steady data transmission and the timing of the first identification code assignment start signal need only be adjusted once, and a controlled device can be easily added.
- the first transmission means of the control device simultaneously notifies each controlled device by the first identification code application start signal that the operation of applying the identification code is started,
- the second transmitting means of the control device notifies the control device adjacent to the control device of the second identification code assignment start signal only to the controlled device.
- the identification code assignment means of the controlled device After the identification code assignment signal detecting means of the controlled device has detected the first and second identification code assignment start signals, the identification code assignment means of the controlled device sets the signal based on the first identification code assigned to its own device. And the third transmitting means of the controlled device outputs a second identification code assignment start signal and an identification code. The application end signal is sequentially notified to the controlled device at the subsequent stage.
- the connector connection terminal of the controlled device has a total of the input of the first and second identification code assignment start signals and the output of the second identification code assignment start signal to the adjacent controlled device. One. That is, the connector connection terminal that outputs the first identification code assignment start signal can be omitted.
- c can reduce the cost of the sequence control apparatus can be omitted the controlled device 5 0 0 units 5 if a sequence control equipment terminal, starts a first identification code granted start signal a second identification code grant
- the first identification code assignment start signal can be extracted from the periodic timing in the communication data.
- the controlled device when the controlled device detects the noise after detecting the first and second identification code assignment start signals, the controlled device uses the detected noise as the identification code assignment end signal from the control device more than the own device. Since the notification is sent to the controlled device adjacent to the far side, an error detection function equal to or higher than the error detection in data transmission can be easily realized.
- the controlled device sets the count-up timing larger than the noise interval, so that the second identification code assignment start signal is adjacent to the control device farther than the own device due to noise level change. Since the operation of assigning the identification code is terminated before notifying the controlled device, it is possible to prevent erroneous assignment of the identification code, and to detect errors such as cyclic codes applied to data communication. It is not necessary to have the circuit dedicated to assigning the identification code, and the identification code can be provided at low cost in a noise environment.
- a part of data transmission notifies the first identification code addition start signal.
- the means for notifying each controlled device of the first identification code assignment start signal is not limited to this. It is only necessary to notify each controlled device of the first identification code assignment start signal at the same time. W
- a controlled device may be provided with a switch, and the switch of each controlled device may be simultaneously depressed using a rod-shaped substance to notify the first identification code assignment start signal.
- transmission of the start of the second identification code assignment to the controlled device at the subsequent stage is similar to the notification of the first identification code assignment start signal. May be depressed at the same time.
- the identification code can be obtained without forming a logic circuit. Can be provided.
- sequence control device is useful for assigning an identification code to a controlled device, and in particular, a sequence control device for setting different numbers of identification codes to a plurality of controlled devices at the time of initial setting. Suitable for.
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Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/012778 WO2005033812A1 (ja) | 2003-10-06 | 2003-10-06 | シーケンス制御装置 |
JP2005509324A JP4353943B2 (ja) | 2003-10-06 | 2003-10-06 | シーケンス制御装置 |
DE10393614T DE10393614B4 (de) | 2003-10-06 | 2003-10-06 | Folgeregeleinheit |
US10/530,360 US7009913B2 (en) | 2003-10-06 | 2003-10-06 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2003/012778 WO2005033812A1 (ja) | 2003-10-06 | 2003-10-06 | シーケンス制御装置 |
Publications (1)
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WO2005033812A1 true WO2005033812A1 (ja) | 2005-04-14 |
Family
ID=34401465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/012778 WO2005033812A1 (ja) | 2003-10-06 | 2003-10-06 | シーケンス制御装置 |
Country Status (4)
Country | Link |
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US (1) | US7009913B2 (ja) |
JP (1) | JP4353943B2 (ja) |
DE (1) | DE10393614B4 (ja) |
WO (1) | WO2005033812A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010003038A (ja) * | 2008-06-19 | 2010-01-07 | Koyo Electronics Ind Co Ltd | シリアル接続内での各ユニットのid自動割付方式 |
CN101937191A (zh) * | 2009-06-26 | 2011-01-05 | 富士电机控股株式会社 | 安全装置和功率转换器 |
Families Citing this family (9)
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JP4591961B2 (ja) * | 2005-07-27 | 2010-12-01 | パナソニック株式会社 | 1線式データ通信方式における通信装置 |
US8134451B1 (en) * | 2007-05-31 | 2012-03-13 | Impinj, Inc. | RFID tag chips and tags capable of backscattering more codes and methods |
US8390431B1 (en) | 2007-05-31 | 2013-03-05 | Impinj, Inc. | RFID tags that backscatter more codes |
US8781053B2 (en) * | 2007-12-14 | 2014-07-15 | Conversant Intellectual Property Management Incorporated | Clock reproducing and timing method in a system having a plurality of devices |
US8467486B2 (en) * | 2007-12-14 | 2013-06-18 | Mosaid Technologies Incorporated | Memory controller with flexible data alignment to clock |
DE102014200321A1 (de) * | 2014-01-10 | 2015-07-16 | Robert Bosch Gmbh | Verfahren zum Starten eines Batteriemanagementsystems |
JP6247247B2 (ja) * | 2015-04-10 | 2017-12-13 | ファナック株式会社 | 制御システム |
GB2568724B (en) * | 2017-11-24 | 2021-08-18 | Ge Aviat Systems Ltd | Method and apparatus for initializing a controller module |
US10826782B2 (en) | 2018-10-30 | 2020-11-03 | Ge Aviation Systems Limited | Method and apparatus for initializing a controller module |
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JPS6468862A (en) * | 1987-09-09 | 1989-03-14 | Nec Corp | Device number setting system |
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US4669070A (en) * | 1979-09-18 | 1987-05-26 | Rca Corporation | Signal format for optical tape record/playback system |
JPH01102669A (ja) | 1987-10-15 | 1989-04-20 | Fujitsu Ltd | 装置番号設定方式 |
GB2288954B (en) * | 1994-04-15 | 1998-10-14 | Vlsi Technology Inc | Method and apparatus for providing programmable serial communications |
US5734329A (en) * | 1995-07-13 | 1998-03-31 | Dell Usa L.P. | Method and apparatus for superimposing self-clocking multifunctional communications on a static digital signal line |
US5751220A (en) * | 1995-07-14 | 1998-05-12 | Sensormatic Electronics Corporation | Synchronized network of electronic devices including back-up master units |
US5914957A (en) * | 1996-12-19 | 1999-06-22 | Otis Elevator Company | Automatic node configuration with identical nodes |
US5883894A (en) * | 1996-12-30 | 1999-03-16 | 3Com Corporation | Shared auto-negotiation logic for multiple port network devices |
EP0872978A1 (en) * | 1997-04-18 | 1998-10-21 | Alcatel | Communication system, master station and slave station |
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2003
- 2003-10-06 JP JP2005509324A patent/JP4353943B2/ja not_active Expired - Fee Related
- 2003-10-06 US US10/530,360 patent/US7009913B2/en not_active Expired - Fee Related
- 2003-10-06 DE DE10393614T patent/DE10393614B4/de not_active Expired - Fee Related
- 2003-10-06 WO PCT/JP2003/012778 patent/WO2005033812A1/ja active Application Filing
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JPS6468862A (en) * | 1987-09-09 | 1989-03-14 | Nec Corp | Device number setting system |
JP2000506660A (ja) * | 1997-09-13 | 2000-05-30 | リンダウェル、ドルニエ、ゲゼルシャフト、ミット、ベシュレンクテル、ハフツング | 機械、特に動力織機の制御装置および制御方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2010003038A (ja) * | 2008-06-19 | 2010-01-07 | Koyo Electronics Ind Co Ltd | シリアル接続内での各ユニットのid自動割付方式 |
CN101937191A (zh) * | 2009-06-26 | 2011-01-05 | 富士电机控股株式会社 | 安全装置和功率转换器 |
JP2011008642A (ja) * | 2009-06-26 | 2011-01-13 | Fuji Electric Holdings Co Ltd | 安全装置および電力変換器 |
Also Published As
Publication number | Publication date |
---|---|
JP4353943B2 (ja) | 2009-10-28 |
US20050270907A1 (en) | 2005-12-08 |
JPWO2005033812A1 (ja) | 2006-12-14 |
US7009913B2 (en) | 2006-03-07 |
DE10393614B4 (de) | 2012-04-05 |
DE10393614T5 (de) | 2005-09-29 |
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