JP2011155149A - 配線基板及びその製造方法並びに半導体パッケージ - Google Patents

配線基板及びその製造方法並びに半導体パッケージ Download PDF

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Publication number
JP2011155149A
JP2011155149A JP2010015937A JP2010015937A JP2011155149A JP 2011155149 A JP2011155149 A JP 2011155149A JP 2010015937 A JP2010015937 A JP 2010015937A JP 2010015937 A JP2010015937 A JP 2010015937A JP 2011155149 A JP2011155149 A JP 2011155149A
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Japan
Prior art keywords
layer
metal layer
substrate
wiring
ceramic
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Pending
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JP2010015937A
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English (en)
Japanese (ja)
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JP2011155149A5 (enExample
Inventor
Sunao Arai
直 荒井
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2010015937A priority Critical patent/JP2011155149A/ja
Priority to US12/954,953 priority patent/US20110180930A1/en
Publication of JP2011155149A publication Critical patent/JP2011155149A/ja
Publication of JP2011155149A5 publication Critical patent/JP2011155149A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
JP2010015937A 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ Pending JP2011155149A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010015937A JP2011155149A (ja) 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ
US12/954,953 US20110180930A1 (en) 2010-01-27 2010-11-29 Wiring board, manufacturing method of the wiring board, and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010015937A JP2011155149A (ja) 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ

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JP2011155149A true JP2011155149A (ja) 2011-08-11
JP2011155149A5 JP2011155149A5 (enExample) 2013-03-07

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015029951A1 (ja) 2013-08-26 2015-03-05 日立金属株式会社 実装基板用ウエハ、多層セラミックス基板、実装基板、チップモジュール、及び実装基板用ウエハの製造方法
JP2019114617A (ja) * 2017-12-22 2019-07-11 京セラ株式会社 配線基板
WO2020138278A1 (ja) * 2018-12-26 2020-07-02 京セラ株式会社 電子部品の接合方法および接合構造体
US11664302B2 (en) * 2018-11-30 2023-05-30 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835217B2 (en) * 2010-12-22 2014-09-16 Intel Corporation Device packaging with substrates having embedded lines and metal defined pads
US9791470B2 (en) * 2013-12-27 2017-10-17 Intel Corporation Magnet placement for integrated sensor packages
US10251270B2 (en) * 2016-09-15 2019-04-02 Innovium, Inc. Dual-drill printed circuit board via
US12205877B2 (en) 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
CN115547846A (zh) * 2019-02-21 2022-12-30 奥特斯科技(重庆)有限公司 部件承载件及其制造方法和电气装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831835A (ja) * 1994-07-20 1996-02-02 Fujitsu Ltd 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
JP2002299486A (ja) * 2001-03-29 2002-10-11 Kyocera Corp 光半導体素子収納用パッケージ
JP2002335082A (ja) * 2001-05-07 2002-11-22 Sony Corp 多層プリント配線基板及び多層プリント配線基板の製造方法
JP2004273980A (ja) * 2003-03-12 2004-09-30 Canon Inc 基板間配線電極接合の方法及び構造体
JP2006012687A (ja) * 2004-06-28 2006-01-12 Tdk Corp 低温焼成基板材料及びそれを用いた多層配線基板
JP2007123371A (ja) * 2005-10-26 2007-05-17 Kyocera Corp 多数個取り電子装置およびその製造方法
JP2008160019A (ja) * 2006-12-26 2008-07-10 Shinko Electric Ind Co Ltd 電子部品
US20080265399A1 (en) * 2007-04-27 2008-10-30 Clinton Chao Low-cost and ultra-fine integrated circuit packaging technique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3407716B2 (ja) * 2000-06-08 2003-05-19 株式会社村田製作所 複合積層電子部品
US20020074637A1 (en) * 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831835A (ja) * 1994-07-20 1996-02-02 Fujitsu Ltd 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
JP2002299486A (ja) * 2001-03-29 2002-10-11 Kyocera Corp 光半導体素子収納用パッケージ
JP2002335082A (ja) * 2001-05-07 2002-11-22 Sony Corp 多層プリント配線基板及び多層プリント配線基板の製造方法
JP2004273980A (ja) * 2003-03-12 2004-09-30 Canon Inc 基板間配線電極接合の方法及び構造体
JP2006012687A (ja) * 2004-06-28 2006-01-12 Tdk Corp 低温焼成基板材料及びそれを用いた多層配線基板
JP2007123371A (ja) * 2005-10-26 2007-05-17 Kyocera Corp 多数個取り電子装置およびその製造方法
JP2008160019A (ja) * 2006-12-26 2008-07-10 Shinko Electric Ind Co Ltd 電子部品
US20080265399A1 (en) * 2007-04-27 2008-10-30 Clinton Chao Low-cost and ultra-fine integrated circuit packaging technique

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015029951A1 (ja) 2013-08-26 2015-03-05 日立金属株式会社 実装基板用ウエハ、多層セラミックス基板、実装基板、チップモジュール、及び実装基板用ウエハの製造方法
JP2019114617A (ja) * 2017-12-22 2019-07-11 京セラ株式会社 配線基板
JP7002321B2 (ja) 2017-12-22 2022-01-20 京セラ株式会社 配線基板
US11664302B2 (en) * 2018-11-30 2023-05-30 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer
WO2020138278A1 (ja) * 2018-12-26 2020-07-02 京セラ株式会社 電子部品の接合方法および接合構造体
JPWO2020138278A1 (ja) * 2018-12-26 2021-11-04 京セラ株式会社 電子部品の接合方法および接合構造体
JP7223772B2 (ja) 2018-12-26 2023-02-16 京セラ株式会社 電子部品の接合方法および接合構造体

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