JP2011086941A - 半導体装置の配線構造物及び配線構造物の製造方法 - Google Patents

半導体装置の配線構造物及び配線構造物の製造方法 Download PDF

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Publication number
JP2011086941A
JP2011086941A JP2010230439A JP2010230439A JP2011086941A JP 2011086941 A JP2011086941 A JP 2011086941A JP 2010230439 A JP2010230439 A JP 2010230439A JP 2010230439 A JP2010230439 A JP 2010230439A JP 2011086941 A JP2011086941 A JP 2011086941A
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JP
Japan
Prior art keywords
contact plug
semiconductor device
wiring structure
conductive line
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010230439A
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English (en)
Japanese (ja)
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JP2011086941A5 (enExample
Inventor
Eun-Ok Lee
殷沃 李
Daiyo Kin
大容 金
Gil-Heyun Choi
吉鉉 崔
Heiki Kin
秉煕 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2011086941A publication Critical patent/JP2011086941A/ja
Publication of JP2011086941A5 publication Critical patent/JP2011086941A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2010230439A 2009-10-16 2010-10-13 半導体装置の配線構造物及び配線構造物の製造方法 Pending JP2011086941A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090098742A KR101602251B1 (ko) 2009-10-16 2009-10-16 배선 구조물 및 이의 형성 방법
US12/836,081 US8501606B2 (en) 2009-10-16 2010-07-14 Methods of forming wiring structures

Publications (2)

Publication Number Publication Date
JP2011086941A true JP2011086941A (ja) 2011-04-28
JP2011086941A5 JP2011086941A5 (enExample) 2013-11-28

Family

ID=43879627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010230439A Pending JP2011086941A (ja) 2009-10-16 2010-10-13 半導体装置の配線構造物及び配線構造物の製造方法

Country Status (4)

Country Link
US (1) US8501606B2 (enExample)
JP (1) JP2011086941A (enExample)
KR (1) KR101602251B1 (enExample)
TW (1) TWI529855B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120073394A (ko) * 2010-12-27 2012-07-05 삼성전자주식회사 반도체 소자 및 이의 제조방법
JP2013074189A (ja) * 2011-09-28 2013-04-22 Elpida Memory Inc 半導体装置及びその製造方法
JP6076038B2 (ja) 2011-11-11 2017-02-08 株式会社半導体エネルギー研究所 表示装置の作製方法
KR101887144B1 (ko) * 2012-03-15 2018-08-09 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
KR101979752B1 (ko) * 2012-05-03 2019-05-17 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101924020B1 (ko) * 2012-10-18 2018-12-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
JP2015122471A (ja) * 2013-11-20 2015-07-02 マイクロン テクノロジー， インク． 半導体装置およびその製造方法
KR20160018270A (ko) * 2014-08-08 2016-02-17 삼성전자주식회사 자기 메모리 소자
CN110890328B (zh) * 2018-09-11 2022-03-18 长鑫存储技术有限公司 半导体存储器的形成方法
TWI696270B (zh) * 2019-04-15 2020-06-11 力晶積成電子製造股份有限公司 記憶體結構及其製造方法
KR102762967B1 (ko) * 2020-04-21 2025-02-05 삼성전자주식회사 콘택 플러그들을 갖는 반도체 소자들
CN113921472B (zh) * 2020-07-08 2024-07-19 长鑫存储技术有限公司 半导体结构及其制作方法
US20230292497A1 (en) * 2022-03-11 2023-09-14 Nanya Technology Corporation Manufacturing method of semiconductor structure
CN118234220A (zh) * 2022-12-20 2024-06-21 长江存储科技有限责任公司 存储器件及其形成方法
KR20240141475A (ko) * 2023-03-20 2024-09-27 삼성전자주식회사 반도체 메모리 소자 및 이의 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01300543A (ja) * 1988-05-27 1989-12-05 Fujitsu Ltd 半導体装置の製造方法
JPH0355829A (ja) * 1989-07-25 1991-03-11 Mitsubishi Electric Corp 半導体装置の製造方法
JP2008205477A (ja) * 2007-02-21 2008-09-04 Samsung Electronics Co Ltd 互いに段差を有するゲートパターン、そして、このパターン間に位置する接続線を有する半導体集積回路装置及びその形成方法
JP2008288597A (ja) * 2007-05-18 2008-11-27 Samsung Electronics Co Ltd 半導体素子及びその製造方法並びにｄｒａｍの製造方法

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JPH06318680A (ja) 1993-05-10 1994-11-15 Nec Corp 半導体記憶装置およびその製造方法
JP2000150651A (ja) * 1998-11-04 2000-05-30 Nec Corp 半導体装置及びプラグ構造の製造方法
US6117723A (en) 1999-06-10 2000-09-12 Taiwan Semiconductor Manufacturing Company Salicide integration process for embedded DRAM devices
JP4860022B2 (ja) 2000-01-25 2012-01-25 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
JP2001257325A (ja) 2000-03-08 2001-09-21 Nec Corp 半導体記憶装置及びその製造方法
US6461959B1 (en) 2001-06-21 2002-10-08 United Microelectronics Corp. Method of fabrication of a contact plug in an embedded memory
KR100629270B1 (ko) * 2005-02-23 2006-09-29 삼성전자주식회사 낸드형 플래시 메모리 소자 및 그 제조방법
KR100666377B1 (ko) * 2005-08-02 2007-01-09 삼성전자주식회사 패드 구조물, 이의 형성 방법, 이를 포함하는 반도체 장치및 그 제조 방법
KR100724575B1 (ko) 2006-06-28 2007-06-04 삼성전자주식회사 매립 게이트전극을 갖는 반도체소자 및 그 형성방법
KR100732773B1 (ko) * 2006-06-29 2007-06-27 주식회사 하이닉스반도체 절연층들간의 들뜸을 방지한 반도체 소자 제조 방법
JP2008078381A (ja) 2006-09-21 2008-04-03 Elpida Memory Inc 半導体装置及びその製造方法
KR100843715B1 (ko) 2007-05-16 2008-07-04 삼성전자주식회사 반도체소자의 콘택 구조체 및 그 형성방법
KR20090035146A (ko) * 2007-10-05 2009-04-09 주식회사 하이닉스반도체 메모리 소자의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01300543A (ja) * 1988-05-27 1989-12-05 Fujitsu Ltd 半導体装置の製造方法
JPH0355829A (ja) * 1989-07-25 1991-03-11 Mitsubishi Electric Corp 半導体装置の製造方法
JP2008205477A (ja) * 2007-02-21 2008-09-04 Samsung Electronics Co Ltd 互いに段差を有するゲートパターン、そして、このパターン間に位置する接続線を有する半導体集積回路装置及びその形成方法
JP2008288597A (ja) * 2007-05-18 2008-11-27 Samsung Electronics Co Ltd 半導体素子及びその製造方法並びにｄｒａｍの製造方法

Also Published As

Publication number Publication date
TW201123356A (en) 2011-07-01
KR20110041760A (ko) 2011-04-22
TWI529855B (zh) 2016-04-11
US8501606B2 (en) 2013-08-06
KR101602251B1 (ko) 2016-03-11
US20110092060A1 (en) 2011-04-21

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