JP2010519738A5 - - Google Patents

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Publication number
JP2010519738A5
JP2010519738A5 JP2009549722A JP2009549722A JP2010519738A5 JP 2010519738 A5 JP2010519738 A5 JP 2010519738A5 JP 2009549722 A JP2009549722 A JP 2009549722A JP 2009549722 A JP2009549722 A JP 2009549722A JP 2010519738 A5 JP2010519738 A5 JP 2010519738A5
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JP
Japan
Prior art keywords
seed layer
resist
exposed
metal layer
wafer
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JP2009549722A
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English (en)
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JP5476127B2 (ja
JP2010519738A (ja
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Publication date
Priority claimed from US11/675,268 external-priority patent/US7598163B2/en
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Publication of JP2010519738A publication Critical patent/JP2010519738A/ja
Publication of JP2010519738A5 publication Critical patent/JP2010519738A5/ja
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Publication of JP5476127B2 publication Critical patent/JP5476127B2/ja
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Claims (15)

  1. ウェハ上にシード層を成層する工程と、
    前記シード層の上部にパターン付きレジストを形成する工程であって、前記パターン付きレジストは、前記シード層の少なくとも一部分を露出する1つ以上の開口を有し、前記パターン付きレジストは、バイアの少なくとも一部に覆いかぶさる、工程と、
    前記シード層の前記露出した少なくとも一部分を金属層でめっきする工程であって、前記金属層は、前記シード層の上面の上方に延在する、工程と、
    前記レジストを除去する工程と、
    前記レジストを除去する工程によって露出した前記シード層の少なくとも一部分を除去する工程と、
    を備える方法。
  2. 前記シード層の前記露出した少なくとも一部分をめっきする前記工程は、前記シード層の前記露出した少なくとも一部分に無電解めっきプロセスを行う工程を備える、請求項1記載の方法。
  3. 前記シード層の前記露出した少なくとも一部分を金属層でめっきする前記工程は、前記シード層の前記露出した少なくとも一部分に電気めっきプロセスを行う工程を備える、請求項1記載の方法。
  4. 前記シード層の少なくとも一部分を除去する前記工程は、前記金属層の高さが少なくとも前記シード層の厚さ分減少するまで、前記シード層の前記露出した少なくとも一部分と前記金属層とを同時にエッチングする工程を備える、請求項1記載の方法。
  5. 前記パターン付きレジストは、前記ウェハの表面に沿って集積回路経路の少なくとも一部分を画成するように構成された少なくとも1つの開口を画成する、請求項1記載の方法。
  6. 前記パターン付きレジストは、ポスト状のスタンドオフを画成するように構成された少なくとも1つの開口を画成する、請求項1記載の方法。
  7. 前記ウェハにバイアが形成され、前記シード層は前記バイア内に成層され、前記レジスト内の前記開口は少なくとも部分的に前記バイア上に配置される、請求項1記載の方法。
  8. 前記パターン付きレジストは、前記バイアの前記開口の少なくとも一部分を覆うように構成された固体レジストである、請求項7記載の方法。
  9. 前記金属層の一部分が、前記バイアの前記開口を超えて延在し、かつ、配線パターンを与えるように構成される、請求項7記載の方法。
  10. 前記レジストを除去する前記工程は、前記金属層の側部を露出する工程を備える、請求項1記載の方法。
  11. 前記シード層の前記露出した一部分の少なくとも一部分を除去する前記工程は、前記金属層の高さが少なくとも前記シード層の厚さ分減少するまで、前記金属層を同時にエッチングする工程を備える、請求項1記載の方法。
  12. 前記シード層が前記ウェハ上に成層される前に、前記ウェハ上に絶縁体を成層する工程を更に備える、請求項1記載の方法。
  13. 前記レジストは固体レジストである、請求項1記載の方法。
  14. 前記シード層の前記少なくとも1つの露出した部分は、前記バイア内に配置される、請求項1記載の方法。
  15. 請求項1乃至14のいずれか1項に記載の方法を用いて形成されるデバイス。
JP2009549722A 2007-02-15 2008-02-14 ポスト−シード成層工程 Active JP5476127B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/675,268 US7598163B2 (en) 2007-02-15 2007-02-15 Post-seed deposition process
US11/675,268 2007-02-15
PCT/US2008/053982 WO2008101093A1 (en) 2007-02-15 2008-02-14 Post-seed deposition process

Publications (3)

Publication Number Publication Date
JP2010519738A JP2010519738A (ja) 2010-06-03
JP2010519738A5 true JP2010519738A5 (ja) 2010-10-28
JP5476127B2 JP5476127B2 (ja) 2014-04-23

Family

ID=39512688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009549722A Active JP5476127B2 (ja) 2007-02-15 2008-02-14 ポスト−シード成層工程

Country Status (6)

Country Link
US (1) US7598163B2 (ja)
EP (1) EP2111635A1 (ja)
JP (1) JP5476127B2 (ja)
KR (1) KR101118798B1 (ja)
CN (1) CN101632166B (ja)
WO (1) WO2008101093A1 (ja)

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