JP2010283816A5 - - Google Patents

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Publication number
JP2010283816A5
JP2010283816A5 JP2010122836A JP2010122836A JP2010283816A5 JP 2010283816 A5 JP2010283816 A5 JP 2010283816A5 JP 2010122836 A JP2010122836 A JP 2010122836A JP 2010122836 A JP2010122836 A JP 2010122836A JP 2010283816 A5 JP2010283816 A5 JP 2010283816A5
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JP
Japan
Prior art keywords
clock signal
output
flip
input
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010122836A
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English (en)
Japanese (ja)
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JP2010283816A (ja
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Publication date
Priority claimed from US12/475,414 external-priority patent/US8355478B1/en
Application filed filed Critical
Publication of JP2010283816A publication Critical patent/JP2010283816A/ja
Publication of JP2010283816A5 publication Critical patent/JP2010283816A5/ja
Pending legal-status Critical Current

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JP2010122836A 2009-05-29 2010-05-28 クロックを並列データに整列させるための回路 Pending JP2010283816A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/475,414 US8355478B1 (en) 2009-05-29 2009-05-29 Circuit for aligning clock to parallel data

Publications (2)

Publication Number Publication Date
JP2010283816A JP2010283816A (ja) 2010-12-16
JP2010283816A5 true JP2010283816A5 (fr) 2013-05-23

Family

ID=42543456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010122836A Pending JP2010283816A (ja) 2009-05-29 2010-05-28 クロックを並列データに整列させるための回路

Country Status (4)

Country Link
US (1) US8355478B1 (fr)
EP (1) EP2256932A1 (fr)
JP (1) JP2010283816A (fr)
TW (1) TWI477130B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102248279B1 (ko) * 2014-06-13 2021-05-07 삼성전자주식회사 불휘발성 메모리 및 메모리 컨트롤러를 포함하는 스토리지 장치, 그리고 불휘발성 메모리 및 메모리 컨트롤러 사이의 통신을 중개하는 리타이밍 회로의 동작 방법
US9825632B1 (en) * 2016-08-04 2017-11-21 Xilinx, Inc. Circuit for and method of preventing multi-bit upsets induced by single event transients
US10432209B1 (en) * 2018-10-10 2019-10-01 Globalfoundries Inc. Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods

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