JP2010283303A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2010283303A JP2010283303A JP2009137654A JP2009137654A JP2010283303A JP 2010283303 A JP2010283303 A JP 2010283303A JP 2009137654 A JP2009137654 A JP 2009137654A JP 2009137654 A JP2009137654 A JP 2009137654A JP 2010283303 A JP2010283303 A JP 2010283303A
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Abstract
【解決手段】半導体チップが固定されたタブと、複数のインナリードと、前記インナリードと一体に形成された複数のアウタリード2bと、前記半導体チップの電極パッドと前記インナリードとを接続する複数のワイヤと、前記半導体チップを封止する封止体とを有し、前記封止体から突出する複数のアウタリード2bのそれぞれの表面に、鉛フリーめっきから成る外装めっき8が形成されており、この外装めっき8は、所望の条件で形成された第1鉛フリーめっき8aと、第1鉛フリーめっき8aの組成と同系列の組成から成る第2鉛フリーめっき8bとを有し、第1鉛フリーめっき8aと第2鉛フリーめっき8bとが積層され、アウタリード2b上にめっき形成条件の異なる2種類の鉛フリーめっきが積層されている。
【選択図】図4
Description
図1は本発明の実施の形態1の半導体装置の製造方法によって組み立てられる半導体装置の構造の一例を示す平面図、図2は図1に示すA−A線に沿って切断した構造を示す断面図、図3は図2に示すA部におけるめっき構造の一例を示す部分断面図、図4は図3に示すB部における外装めっきの詳細構造の一例を示す拡大部分断面図、図5は図3に示すB部における第1変形例の外装めっきの詳細構造を示す拡大部分断面図、図6は図3に示すB部における第2変形例の外装めっきの詳細構造を示す拡大部分断面図である。
図18は本実施の形態2の半導体装置の組み立ての鉛フリーめっき形成工程で用いられるめっき装置の構造の一例を示すブロック構成図、図19は図18に示すめっき装置における給電方法の一例を示す概略図、図20は図19に示す給電方法で用いられる搬送ベルトの構造の一例を示す構成概略図、図21は本実施の形態2の半導体装置の組み立ての鉛フリーめっき形成工程で用いられる変形例のめっき装置の構造を示すブロック構成図である。
2 マトリクスフレーム(リードフレーム)
2a インナリード
2b アウタリード
2c タブ(ダイパッド)
2d デバイス領域
2e 枠部
2f スプロケットホール
2g 長孔
2h 主面
2i ワイヤ接合部
2j 切断面
3 封止体
4 半導体チップ
4a 主面
4b 裏面
4c 電極パッド(表面電極)
5 ワイヤ
6 めっき装置
6a ローダ
6b 電解バリ取り部
6c 水圧バリ取り部
6d 化学研摩部
6e 酸活性部
6f めっき形成部
6g めっき槽
6h 第1のステージ(第1のめっき処理部)
6i 第1の整流器
6j 第2のステージ(第2のめっき処理部)
6k 第2の整流器
6m 第3のステージ(第2のめっき処理部)
6n 第3の整流器
6p 第4のステージ(第2のめっき処理部)
6q 第4の整流器
6r 第5のステージ(第2のめっき処理部)
6s 第5の整流器
6t 水洗部
6u 乾燥部
6v アンローダ
6w めっき用治具
6x 給電レール
6y 非導電性レール
6z 治具接点
6za アノード
6zb バー部材
6zc 整流器
7 ダイボンディング材
8 外装めっき
8a 第1鉛フリーめっき
8b 第2鉛フリーめっき
8c 界面
9 銀めっき
9a 下地銅めっき
10 フレーム搬送方向
11 めっき装置
11a 搬送ベルト
11b 把持部
11c めっき形成部
11d 第1のめっき槽(第1のめっき処理部)
11e 第1の整流器
11f 第2のめっき槽(第2のめっき処理部)
11g 第2の整流器
11h 第3のめっき槽(第2のめっき処理部)
11i 第3の整流器
11j 第4のめっき槽(第1のめっき処理部)
11k 第4の整流器
12 めっき装置
Claims (19)
- 複数の表面電極が設けられた半導体チップと、
前記半導体チップが搭載されたダイパッドと、
前記半導体チップの周囲に配置された複数のインナリードと、
前記半導体チップの前記複数の表面電極と前記複数のインナリードとをそれぞれ電気的に接続する複数のワイヤと、
前記半導体チップ、前記複数のインナリード及び前記複数のワイヤを封止する封止体と、
前記複数のインナリードそれぞれと一体で繋がり、前記封止体から露出する複数のアウタリードと、
前記複数のアウタリードそれぞれの表面に形成された外装めっきと、
を有し、
前記外装めっきは、所望の条件で形成された第1鉛フリーめっきと、前記第1鉛フリーめっきの組成と同系列の組成から成る第2鉛フリーめっきとを有し、前記第1鉛フリーめっきと前記第2鉛フリーめっきとが積層されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記複数のアウタリードそれぞれは、鉄−ニッケル合金から成ることを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記外装めっきは、錫−銅めっきであることを特徴とする半導体装置。
- 請求項3記載の半導体装置において、前記複数のインナリードそれぞれのワイヤ接合部に銀めっきが形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1鉛フリーめっきは、前記第2鉛フリーめっきを形成する際に印加する電流密度より高い電流密度が印加されて形成されためっきであることを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記第1鉛フリーめっきは、前記外装めっきの厚さ方向におけるリード側に配置されていることを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記第1鉛フリーめっきは、前記外装めっきの厚さ方向に対して前記第2鉛フリーめっきによって挟まれて配置されていることを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記第1鉛フリーめっきは、前記外装めっきの厚さ方向における表面側に配置されていることを特徴とする半導体装置。
- (a)半導体チップを覆う封止体が形成されたリードフレームを準備する工程と、
(b)それぞれ別々に整流器が接続された第1のめっき処理部と第2のめっき処理部を備えためっき装置に前記リードフレームを配置して前記リードフレームの前記封止体から露出する複数のアウタリードに鉛フリーめっき処理を行う工程と、
を有し、
前記(b)工程において、前記第1のめっき処理部で第1の鉛フリーめっき液に前記リードフレームを浸した状態で第1の電流密度を印加して前記複数のアウタリードに第1の鉛フリーめっき処理を施し、その後、前記第2のめっき処理部で、前記第1の鉛フリーめっき液と組成が同系列の第2の鉛フリーめっき液に前記リードフレームを浸した状態で前記第1の電流密度と異なった第2の電流密度を印加して前記複数のアウタリードに第2の鉛フリーめっき処理を施すことを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、前記(b)工程の前に、前記リードフレームを化学研摩することを特徴とする半導体装置の製造方法。
- 請求項10記載の半導体装置の製造方法において、前記化学研摩の後、前記(b)工程の前に、前記第1の鉛フリーめっき液を形成する際に用いられる酸と同じ酸で前記リードフレームを洗うことを特徴とする半導体装置の製造方法。
- 請求項11記載の半導体装置の製造方法において、前記第1のめっき処理部で用いる前記第1の鉛フリーめっき液と、前記第2めっき処理部で用いる前記第2の鉛フリーめっき液は同じであることを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記第2のめっき処理部で印加する前記第2の電流密度は、前記第1のめっき処理部で印加する前記第1の電流密度より低いことを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記第1のめっき処理部と前記第2のめっき処理部は、同一のめっき槽に配置されていることを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記第1のめっき処理部と前記第2のめっき処理部は、それぞれ異なっためっき槽に配置されていることを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記リードフレームは、鉄−ニッケル合金から成ることを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、鉛フリーめっきは、錫−銅めっきであることを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記リードフレームに設けられた複数のインナリードのワイヤ接合部に銀めっきが形成されていることを特徴とする半導体装置の製造方法。
- (a)ダイパッドと、前記ダイパッドの周囲に配置された複数のインナリードと、前記複数のインナリードそれぞれと一体で繋がる複数のアウタリードとを有する薄板状のリードフレームを準備する工程と、
(b)前記ダイパッドに半導体チップを搭載する工程と、
(c)前記半導体チップの複数の電極パッドと前記複数のインナリードとをそれぞれワイヤで電気的に接続する工程と、
(d)前記半導体チップと前記複数のインナリードと複数の前記ワイヤとを封止体によって封止する工程と、
(e)それぞれ別々に整流器が接続された第1のめっき処理部と第2のめっき処理部を備えためっき装置に、前記封止体が形成された前記リードフレームを配置して前記封止体から露出する前記複数のアウタリードに鉛フリーめっき処理を行う工程と、
(f)前記複数のアウタリードを前記リードフレームから切断分離して個片化する工程と、
を有し、
前記(e)工程において、前記第1のめっき処理部で第1の鉛フリーめっき液に前記リードフレームを浸した状態で第1の電流密度を印加して前記複数のアウタリードに第1の鉛フリーめっき処理を施し、その後、前記第2のめっき処理部で、前記第1の鉛フリーめっき液と組成が同系列の第2の鉛フリーめっき液に前記リードフレームを浸した状態で前記第1の電流密度と異なった第2の電流密度を印加して前記複数のアウタリードに第2の鉛フリーめっき処理を施すことを特徴とする半導体装置の製造方法。
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CN2010101985905A CN101908515A (zh) | 2009-06-08 | 2010-06-07 | 半导体器件及其制备方法 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11330340A (ja) * | 1998-05-21 | 1999-11-30 | Hitachi Ltd | 半導体装置およびその実装構造体 |
JP2000174191A (ja) * | 1998-12-07 | 2000-06-23 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2006100402A (ja) * | 2004-09-28 | 2006-04-13 | Fujitsu Ltd | 積層無鉛めっきを用いた半導体装置及びその製造方法 |
JP2009019215A (ja) * | 2007-07-10 | 2009-01-29 | Kyushu Nogeden:Kk | 電子部品の外部リード及び外部リードのメッキ方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3417395B2 (ja) * | 2000-09-21 | 2003-06-16 | 松下電器産業株式会社 | 半導体装置用リードフレーム及びその製造方法及びそれを用いた半導体装置 |
JP2002299540A (ja) * | 2001-04-04 | 2002-10-11 | Hitachi Ltd | 半導体装置およびその製造方法 |
EP1281789B1 (en) * | 2001-07-31 | 2006-05-31 | Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) | A plated copper alloy material and process for production thereof |
US7772043B2 (en) * | 2001-12-12 | 2010-08-10 | Sanyo Electric Co., Ltd. | Plating apparatus, plating method and manufacturing method for semiconductor device |
JP2004204308A (ja) * | 2002-12-25 | 2004-07-22 | Nec Semiconductors Kyushu Ltd | 鉛フリー錫合金めっき方法 |
JP4434669B2 (ja) * | 2003-09-11 | 2010-03-17 | Necエレクトロニクス株式会社 | 電子部品 |
JP2007081235A (ja) * | 2005-09-15 | 2007-03-29 | Renesas Technology Corp | 半導体装置の製造方法 |
US20070117475A1 (en) * | 2005-11-23 | 2007-05-24 | Regents Of The University Of California | Prevention of Sn whisker growth for high reliability electronic devices |
JP2007254860A (ja) * | 2006-03-24 | 2007-10-04 | Fujitsu Ltd | めっき膜及びその形成方法 |
JP2008098478A (ja) * | 2006-10-13 | 2008-04-24 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP4895827B2 (ja) * | 2007-01-04 | 2012-03-14 | トヨタ自動車株式会社 | めっき部材およびその製造方法 |
JP2009108339A (ja) * | 2007-10-26 | 2009-05-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP5191915B2 (ja) * | 2009-01-30 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2009
- 2009-06-08 JP JP2009137654A patent/JP2010283303A/ja active Pending
-
2010
- 2010-05-13 US US12/779,527 patent/US20100308448A1/en not_active Abandoned
- 2010-05-20 TW TW099116176A patent/TW201108363A/zh unknown
- 2010-05-28 KR KR1020100049928A patent/KR20100131922A/ko not_active Application Discontinuation
- 2010-06-07 CN CN2010101985905A patent/CN101908515A/zh active Pending
-
2012
- 2012-12-28 US US13/730,200 patent/US20130115737A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11330340A (ja) * | 1998-05-21 | 1999-11-30 | Hitachi Ltd | 半導体装置およびその実装構造体 |
JP2000174191A (ja) * | 1998-12-07 | 2000-06-23 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2006100402A (ja) * | 2004-09-28 | 2006-04-13 | Fujitsu Ltd | 積層無鉛めっきを用いた半導体装置及びその製造方法 |
JP2009019215A (ja) * | 2007-07-10 | 2009-01-29 | Kyushu Nogeden:Kk | 電子部品の外部リード及び外部リードのメッキ方法 |
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CN101908515A (zh) | 2010-12-08 |
US20130115737A1 (en) | 2013-05-09 |
TW201108363A (en) | 2011-03-01 |
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