CN104078437A - 引线框架及半导体装置 - Google Patents
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Abstract
本发明提供引线框架及半导体装置,其包含具有良好的接合性的外引线。引线框架(10)的外引线(18)包含镀层(23),该镀层(23)覆盖框架基材(11)的下表面(11a)及两个侧面(11b,11c)。框架基材(11)的上表面(11d)没有被镀层(23)覆盖。
Description
技术领域
本发明涉及引线框架及半导体装置。
背景技术
通常,引线框架用于将半导体元件安装到基板上。半导体装置通过在已将半导体元件安装到引线框架的焊垫部上的状态下用树脂材料密封半导体元件和引线框架而制造。例如,用于表面安装型半导体装置的引线框架包含:焊垫部,其安装有半导体元件;以及外引线,其作为半导体装置的外部连接端子而发挥功能。外引线焊接在被形成在基板等上的垫片(安装对象)上(例如,日本特开2003-78097号公报、日本特开平10-74879号公报)。
发明内容
本发明的目的为,提供引线框架及半导体装置,其包含具有良好的接合性的外引线。
本发明的一个方面为引线框架。引线框架,其中,具备:框架基材,其包含多个连接引线、和将所述多个连接引线相互连接的框架堤坝,各个连接引线包含比所述框架堤坝靠内侧的内引线、和比所述框架堤坝靠外侧的外引线;以及镀层,其覆盖各个外引线的上表面及下表面中的任意一方、和各个外引线的两个侧面,所述框架基材在各个外引线的所述上表面及下表面中的另一方上从所述镀层露出。
本发明的另一个方面为半导体装置。半导体装置,其中,具备:半导体元件;密封树脂,其对所述半导体元件进行密封;以及多个连接引线,其从所述密封树脂向外导出,各个连接引线包含顶端部,该顶端部作为连接到连接对象上的接合部而发挥功能,并且各个接合部的下表面及两个侧面被镀层覆盖,各个接合部的上表面从所述镀层露出以框架基材露出。
本发明的另一个方面为引线框架。引线框架,其中,具备:外引线,其包含以与接合对象接合的方式构成的下表面、处在所述下表面的相反侧的上表面、和所述下表面和上表面之间的侧面;以及镀层,其覆盖除了所述外引线的所述上表面以外的、所述外引线的所述下表面及所述侧面,所述镀层包含与所述外引线的所述上表面齐平的上端面。
根据本发明,可以得到包含具有良好的接合性的外引线的引线框架及半导体装置。
附图说明
图1A是引线框架的局部俯视图。
图1B是图1A的引线框架的局部放大剖视图。
图1C是图1A的引线框架的局部放大剖视图。
图2A是半导体装置的概要剖视图。
图2B是用于说明图2A的半导体装置的外引线的示意图。
图2C是用于说明图2A的半导体装置的外引线的示意图。
图3A是用于说明引线框架的制造方法的剖视图。
图3B是用于说明引线框架的制造方法的剖视图。
图3C是用于说明引线框架的制造方法的剖视图。
图3D是用于说明引线框架的制造方法的剖视图。
图3E是用于说明引线框架的制造方法的剖视图。
图4A是用于说明实施方式的外引线被连接在焊垫上时的焊锡形状的示意图。
图4B是用于说明实施方式的外引线被连接在焊垫上时的焊锡形状的示意图。
图5A是用于说明比较例的外引线被连接在焊垫上时的焊锡形状的示意图。
图5B是用于说明比较例的外引线被连接在焊垫上时的焊锡形状的示意图。
图6是其他例子的半导体装置的概要剖视图。
具体实施方式
以下,对实施方式进行说明。附图可能有将成为特征的部分扩大示出的情况,以便易于理解其特征。构成元件的尺寸比可能有与实际的电子部件、或与其他设计图中的电子部件不同的情况。在剖视图中,可能有省略了一部分的构成元件的剖面线的情况,以便易于理解构成元件的截面结构。
如图1A所示,实施方式的引线框架10包含框架基材11,该框架基材11作为QFP(Quad Flat Package:四侧引脚扁平封装)的基板被使用。框架基材11例如可以是铜(Cu)部件、Cu合金部件、铁-镍(Fe-Ni)二元合金部件、或Fe-Ni多元合金部件等。框架基材11可以通过对金属板或合金板进行例如冲压加工或浸蚀加工来获得。
框架基材11包含焊垫12,在该焊垫12上安装有半导体元件31。焊垫12例如可以是矩形平板。焊垫12被支撑条14支承,支撑条14被连接在向框架基材11的长度方向延伸的一对导轨部13上。在焊垫12的周围上设置有多个框架堤坝(也可以称为连接杆)15及多个连接引线16。多个连接引线16通过框架堤坝15相互连接。各个连接引线16包含:内引线17,其以从对应的框架堤坝15向焊垫12的方式向内延伸;以及外引线18,其从该对应的框架堤坝15向外延伸。各个外引线18的顶端被连接在导轨部13上、或跨在一对导轨部13上的内框架19上。在图示出的例子中,一对内框架19向与导轨部13的长度方向正交的方向延伸以连接一对导轨部13,并且在一对内框架19之间配置有焊垫12。焊垫12、支撑条14、框架堤坝15、及连接引线16(内引线17,外引线18)由被形成在框架基材11上的开口部划定。在图1A中,围绕内引线17的顶端的矩形的点划线表示通过密封树脂34(参照图2)而被树脂密封的树脂密封区域。焊垫12及内引线17埋设于密封树脂34内,而外引线18从密封树脂34露出。
图1B所示,焊垫12包含覆盖框架基材11的一面(例如上表面)的镀层21。镀层21例如可以是镍(Ni)镀层、或银(Ag)镀层。在镀层21上安装有半导体元件31。在图1B中,引线框架10的上表面为安装半导体元件31的安装侧的一例。引线框架10的下表面为处在安装侧的相反侧的非安装侧的一例。
在引线框架10的安装侧上的内引线17的顶端17a上形成有内部端子22。内部端子22作为引线焊接部而发挥功能,并通过例如金属线(焊线)33而连接在焊垫12上的半导体元件31的垫部31a上。内部端子22例如可以是镀层。
如图1B及图1C所示,外引线18包含镀层23。镀层23覆盖外引线18的下表面11a及两个侧面11b,11c。外引线18的上表面11d没有被镀层23覆盖。在外引线18的上表面上露出了框架基材11(例如铜或铜合金)的上表面。在图1C示出的例子中,外引线18的截面上的镀层23的上端面可以与外引线18的上表面11d(或框架基材11的上表面)齐平。
镀层23为3层结构的镀层。外引线18的下表面及侧面被第1镀层24覆盖,第1镀层24被第2镀层25覆盖,第2镀层25被第3镀层26覆盖。在本实施方式中,第1镀层24为镍(Ni)镀层,第2镀层25为钯(pd)镀层,第3镀层26为金(Au)镀层。外引线18的上表面11d没有被第1-第3镀层24-26中的任意一层覆盖。另外,第1镀层24也可以使用镍合金镀层。第2镀层25也可以使用钯合金镀层。第3镀层26也可以使用金合金。
在图示出的例子中,内部端子22为与外引线18的镀层23同样的、包含第1-第3镀层24-26的3层结构的镀层。内部端子22可以是2层结构的镀层、或包含银(Ag)镀层的4层以上的镀层。镀层21可以是与外引线18的镀层23同样的3层结构的镀层(镍镀层,钯镀层,金镀层)。镀层21可以是2层结构的镀层、或4层以上的镀层。
以下,对图1A中示出的引线框架10的制造工序的概要进行说明。
首先,对铜或铜合金等的金属板进行压印或浸蚀而成形(框架成形)框架基材11。
接着,将液体抗蚀剂涂布至整个框架基材11上,并进行预烘烤来形成抗蚀膜(抗蚀涂敷)。该液体抗蚀剂具有通过规定的光线(例如紫外线)的照射而被固化的性质。
通过光掩膜来暴光液体抗蚀剂。显影抗蚀膜,并且除去没有被规定波长的光线照射的规定部分的抗蚀膜。由此,选择性地露出框架基材11的表面中的、形成镀层的规定部分。
在该露出的规定部分上形成镀层23。例如,在露出的框架基材11的规定部分上形成镍(Ni)镀层。镀层例如由电镀、无电镀、阴极溅镀等来形成镀层。
接着,在镍镀层上形成钯(Pd)镀层。在钯镀层上施加金(Au)镀层。之后,通过剥离上述抗蚀膜而使除了形成了镀层23的规定部分以外的框架基材11的表面露出。
通过这样的工序来完成局部电镀的引线框架10。被电镀的部分包含成为外引线18的框架基材11的下表面11a及侧面11b,11c。
以下,按照图3A-图3E对在外引线18上形成镀层23的工序进行说明。
首先,如图3A所示,在框架基材11上涂敷液体抗蚀剂,从而在整个框架基材11上形成抗蚀膜41。
接着,如图3B所示,使用保护膜42,43并用规定波长的光线将对应于保护膜42的开口部42a的、框架基材11的上表面11d上的抗蚀膜41a进行选择性地暴光。通过该暴光来固化上表面11d上的抗蚀膜41a。
如图3C所示,通过显影除去未固化的抗蚀膜。由此,露出框架基材11的下表面11a及侧面11b,11c。
接着,如图3D所示,在框架基材11的下表面11a及侧面11b,11c上形成镀层23。该镀层23包含如上所述的镍镀膜、钯镀膜、及金镀膜(参照图1C)。
如图3E所示,除去框架基材11的上表面11d上的抗蚀膜41a。例如使用剥离液来剥离抗蚀膜41a。在另外的例子中,可通过完全燃烧等的处理来除去抗蚀膜41a。由此,形成框架基材11的下表面11a及侧面11b,11c被镀层23覆盖,并且上表面11d没有被镀层23覆盖的外引线18。
以下,对包含引线框架10的半导体装置进行说明。
如图2A所示,树脂密封型半导体装置30具备引线框架10、以及半导体元件31。半导体装置30的组件结构例如为QFP(Quad Flat Package)。在焊垫12的上表面上通过粘合剂粘合有半导体元件31。粘合剂例如为银(Ag)焊膏。
半导体元件31的垫部31a通过金属线(焊线)33而连接在内引线17的内部端子22上。金属线33例如为金、铜、铝(Al)等的细线。包含半导体元件31、金属线33、焊垫12、以及内引线17的顶端部的一部分由密封树脂34密封。在该半导体装置30中,包含内引线17的基端部和外引线18的连接引线16露出于密封树脂34的外部。
半导体元件31虽未被限定,但是例如可为LSI(Large-Scale Integration:大规模集成)芯片。在图示的例中,虽然1个半导体元件31被安装于焊垫12上,但也可以按照需要安装两个或其以上的半导体元件。也可以代替半导体元件31、或与半导体元件31组合,而在焊垫12上安装任意的有源元件或无源元件。金属线33虽未被限定,但可以是例如Cu线、Au线、和铝(Al)线等。密封树脂34虽未被限定,但可以是例如环氧树脂、聚酰亚胺树脂、酚醛树脂、和丙烯酸树脂等。
如图2B所示,外引线18可以包含:第1屈曲部18a,其被形成在内引线17近侧;以及第2屈曲部18b,其被形成在比第1屈曲部18a更靠外侧。外引线18由第1及第2屈曲部18a,18b形成为所谓的鸥翼状。第1屈曲部18a被设定在例如可以是框架堤坝15(参照图1A)位置的、规定的位置上。
如图2A所示,有时会把从密封树脂24横向导出的连接引线16的部分称为肩部51。有时会把从第2屈曲部18b到外引线19的顶端的部分称为接合部52。该接合部52的安装面(下表面)通过焊锡而被安装在印刷电路板等的安装用基板的垫部上。有时会把肩部51和接合部52之间的连接引线16的部分称为脚部53。脚部53被构成为,将密封树脂34支承在离为安装对象的基板规定的高度的位置上。
如图2B所示,在脚部53上以从接合部52的下表面连续的方式形成有镀层23。如图2C所示,至少在接合部52上的、框架基材11的下表面11a及两个侧面11b,11c被镀层23覆盖。为外引线18的基材的框架基材11露出于接合部52的上表面。该露出的框架基材11的表面在经过了树脂密封等的热处理时被氧化。由此,在外引线18上的、框架基材11的上表面11d上形成有氧化铜膜等的氧化膜。
以下,对引线框架10及半导体装置30的作用进行说明。
如图4A所示,外引线18通过焊锡62而与如未予图示的基板等的垫片61的安装对象接合。在该外引线18上的、框架基材11的下表面11a及侧面11b,11c上形成有镀层23。因此,焊锡对于外引线18的下表面及侧面显示良好的润湿性。
镀层23覆盖至外引线18侧面的上端。焊锡62即使在焊锡62量较少的情况下,也易于向上延伸至外引线18的侧面的上端。其结果,焊锡62易于形成适宜的焊接圆角。这样的焊锡62提高外引线18和安装对象的连接信赖性。
外引线18的上表面(即、框架基材11的上表面11d)没有被镀层23覆盖。框架基材11的上表面11d在经过了树脂密封等的热处理时被氧化。其结果,氧化膜(氧化铜膜)被形成在上表面11d上。由于这样的氧化膜和焊锡的润湿性较差,所以上表面11d的氧化膜可以防止或降低焊锡向上延伸到外引线18的上表面。
在图4B中示出的例子中,镀层23被形成在外引线18的第2屈曲部18b和第1屈曲部18a之间的、框架基材11的倾斜下表面上。焊锡62通过该镀层23沿框架基材11的倾斜下表面而向上延伸,从而形成适宜的焊接圆角。
在图4B的例子中,在外引线18上的框架基材11的顶端面11e上没有形成镀层23。引线框架10在形成了密封树脂34后并对半导体装置30进行单片化时在外引线18的顶端被切断。所以,该顶端面11e与框架基材11的上表面11d相比受到热处理的影响的机会较少。因此,只在框架基材11的顶端面11e上几乎或完全没有形成氧化膜、或形成仅覆盖顶端面11e的一部分的局部氧化膜、或形成薄的氧化膜,以不至于降低焊锡的润湿性。在这样的情况下,在焊接工序中沿框架基材11的顶端面11e而向上延伸焊锡62,从而适宜的焊接圆角。
以下,对比较例进行说明。在图5A中示出的第1比较例的引线71中,只在基材72的下表面(安装面)上形成有镀层73。在第1比较例中,镀膜没有被形成在引线71(基材72)的侧面上。这样的露出了的基材72的侧面被在经过了由树脂密封等的热处理时形成的氧化膜(例如氧化铜)覆盖。因为氧化膜,焊锡62几乎或完全没有向上延伸到引线71(基材72)的侧面。在第1比较例中,没有形成焊接圆角。因此,第1比较例的引线71和垫片61的连接信赖性较低。
在图5B中示出的第2比较例的引线81中,镀层83被形成在基材82的下表面、侧面及上表面上。在第2比较例中,焊锡62以覆盖引线81的上表面的方式向上延伸到引线81的上表面。所以,可能会有引线81的下表面和垫片61之间、和/或引线81侧面的焊锡量不足,而不能形成适宜的焊接圆角的情况。因此,第2比较例的引线81和垫片61的连接信赖性比较低。
覆盖引线81(基材82)的整个表面的镀层83虽为例如3层结构的镀层(镍镀层(基础层)、钯镀层、金镀层),但是这会使对于通过该引线81传播的信号的高频成分的电阻值增加。因此,覆盖引线81(基材82)的整个表面的镀层83有降低引线81的信号质量的情况。
相对于此,在实施方式的连接引线16中,在接合部52的框架基材11的下表面11a及侧面11b,11c包含被镀层23覆盖的外引线18、和顶端上表面被内部端子22(镀层)覆盖的内引线17(参照图2A-图2C)。因此,对于高频成分的实施方式的连接引线16的电阻值低于被镀层83覆盖整个表面的引线81(参照图5B)的电阻值。在实施方式的连接引线16中,因镀层23的信号质量的降低较少。这样,可以兼容高品质的信号传播和连接信赖性的改善。
根据实施方式可以获得以下效果。
(1)引线框架10的外引线18包含镀层23,该镀层23覆盖框架基材11的下表面11a及两个侧面11b,11c。在外引线框18的上表面没有被镀层23覆盖。因此,在安装半导体装置30时,焊锡62通过镀层23而向上延伸到外引线18的侧面,从而形成良好的焊接圆角。所以,可以在安装半导体装置30时得到很高的连接信赖性。
在图示的例子中,在引线框架10的框架基材11上形成有被框架堤坝15相互连接的多个连接引线16。连接引线16具有:从框架堤坝15向内延伸的内引线17、和从框架堤坝15向外延伸的外引线18。外引线18包含镀层23,该镀层23覆盖框架基材11的下表面11a及两个侧面11b,11c。由于框架基材11的上表面11d没有被镀层23覆盖,因而露出了为外引线18的基材的铜或铜合金。在该例子中,外引线18的一部分作为用于将使用引线框架10制造的半导体装置30安装至安装对象上的接合部52而发挥功能。在该接合部52上的框架基材11的下表面11a及两个侧面11b,11c被镀层23覆盖。因此,在安装半导体装置30时,焊锡通过镀层而在接合部52的侧面向上延伸,从而形成良好的焊接圆角。所以,在安装半导体装置30时可以得到高连接信赖性。
(2)接合部52上的框架基材11的上表面11d没有被镀层23覆盖。该上表面11d被在经过了树脂密封等的热处理时形成的氧化膜覆盖。该氧化膜的焊锡62的润湿性较低。因此,焊锡62不会向上延伸到接合部52的上表面,所以用于接合的焊锡不会不足,并能够形成适宜的焊接圆角。
对于本领域的技术人员显而易见的是,在不偏离本发明的精神和范畴的情况下,可以以许多其他特定形式实施本发明。尤其应理解,可以以下面的形式实施本发明。
也可以适宜地变更镀层23(参照图1C)的形成方法。例如,也可以用只在框架基材11的必要部分设置开口部的保护膜夹框架基材11,而只对框架基材11的必要部分施加电镀。例如,如图1A所示,外引线18在通过被形成在框架基材11上的开口部而被划定的情况下,可通过用覆盖框架基材11的上表面的保护膜、和具有与划定外引线18的开口部相对应的开口部的保护膜夹框架基材11而不用对框架基材11的上表面施加电镀,从而对框架基材11的下表面11a及侧面11b,11c施加电镀。虽不做限定,但优选地使用针对镀层23所包含的第1-第3镀层24-26而准备的保护膜。
包含镀层23的连接引线16,也可以适用于没有焊垫的引线框架和/或半导体装置上。
半导体装置30的构成也可以适当地变更。在图6中示出的例子中,半导体装置30a包含被连接在焊垫12的下表面上的半导体元件31。内部端子被形成在内引线17的顶端下表面上。外引线18包含镀层23,该镀层23覆盖与形成有内部端子的内引线17的顶端下表面相同侧的框架基材11的面(下表面)、和框架基材11的侧面。即使在这样的半导体装置30a上,也可以形成与实施方式同样地良好的焊接圆角,并可以抑制连接信赖性的下降。由于只在必要的部分上形成镀层23,所以抑制连接引线16上的电阻值的增加,从而可以抑制信号质量的下降,而且可以实现高质量的信号传播。
也可以适当地变更局部覆盖外引线18的镀层23的层数和材质。
在上述实施方式中,外引线18的顶端也可以不被连接在导轨部13或内框架19上。
本文所记载的所有例子和条件语言意欲教导,为了有助于读者理解发明人使技术深化所提出的本发明的原理和构思,应当理解为本发明不受此处特别罗列的例子和条件的限制,并且说明书中这些例子的组织与展示本发明的优势和劣势无关。虽然已经详细描述了本发明的实施例,应当理解的是,在不偏离本发明的精神和范畴的情况下,可以对其进行各种改变、置换和替换。
Claims (13)
1.一种引线框架,其中,
具备:框架基材,其包含多个连接引线、和将所述多个连接引线相互连接的框架堤坝,各个连接引线包含比所述框架堤坝靠内侧的内引线、和比所述框架堤坝靠外侧的外引线;以及
镀层,其覆盖各个外引线的上表面及下表面中的任意一方、和各个外引线的两个侧面,
所述框架基材在各个外引线的所述上表面及下表面中的另一方上从所述镀层露出。
2.根据权利要求1所述的引线框架,其中,
所述框架基材为铜或铜合金,
在从所述镀层露出的所述框架基材的表面上形成有氧化膜。
3.根据权利要求1所述的引线框架,其中,
所述镀层对应于为了将半导体装置安装至安装对象上而被形成在各个外引线的一部分上的、通过焊锡接合在所述安装对象上的接合部形成。
4.根据权利要求1所述的引线框架,其中,
进一步具备内部端子,该内部端子在各个内引线的顶端形成在所述内引线的上表面及下表面的任意一方上,并被连接在半导体元件上,
所述镀层被形成在与形成有所述内部端子的、所述内引线的表面相反的一侧的所述外引线的表面、和所述外引线的两个侧面上。
5.根据权利要求1所述的引线框架,其中,
进一步具备内部端子,该内部端子在各个内引线的顶端形成在所述内引线的上表面及下表面的任意一方上,并被连接在半导体元件上,
所述镀层被形成在与形成有所述内部端子的、所述内引线的表面相同的一侧的所述外引线的表面、和所述外引线的两个侧面上。
6.根据权利要求1-5任意一项中所述的引线框架,其中,
所述镀层具有由第1镀层、第2镀层和第3镀层构成的3层结构,
第1镀层被形成在所述框架基材上,由Ni或Ni合金形成,
第2镀层被形成在所述第1镀层上,由Pd或Pd合金形成,
第3镀层被形成在所述第2镀层上,由Au或Au合金形成。
7.一种半导体装置,其中,
具备:半导体元件;
密封树脂,其对所述半导体元件进行密封;以及
多个连接引线,其从所述密封树脂向外导出,
各个连接引线包含顶端部,该顶端部作为连接到连接对象上的接合部而发挥功能,并且各个接合部的下表面及两个侧面被镀层覆盖,
各个接合部的上表面从所述镀层露出以使框架基材露出。
8.根据权利要求7所述的半导体装置,
所述框架基材为铜或铜合金,
在从所述镀层露出的所述框架基材的表面上形成有氧化膜。
9.根据权利要求7或8所述的引线框架,其中,
各个连接引线包含所述密封树脂的附近的外引线基端部、和所述接合部与该外引线的基端部之间的脚部,所述镀层从所述接合部的所述下表面连续地覆盖所述脚部。
10.一种引线框架,其中,
具备:外引线,其包含以与接合对象接合的方式构成的下表面、处在所述下表面的相反侧的上表面、和所述下表面和上表面之间的侧面;以及
镀层,其覆盖除了所述外引线的所述上表面以外的、所述外引线的所述下表面及所述侧面,
所述镀层包含与所述外引线的所述上表面齐平的上端面。
11.根据权利要求10所述的引线框架,其中,
所述外引线的所述上表面、所述下表面、及所述侧面分别包含所述外引线的顶端接合部的上表面、下表面及侧面,
所述镀层覆盖除了所述顶端接合部的所述上表面以外的、所述顶端接合部的所述下表面及所述侧面,
所述镀层包含与所述顶端接合部的所述上表面齐平的上端面。
12.根据权利要求10所述的引线框架,其中,
没有被所述镀层覆盖的所述外引线的所述上表面被氧化膜覆盖。
13.根据权利要求10所述的引线框架,其中,
所述镀层从所述外引线的顶端部向所述外引线的基端部连续地延伸。
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JPH0494563A (ja) * | 1990-08-10 | 1992-03-26 | Nec Corp | 表面実装型半導体装置およびその製造方法 |
JPH1074879A (ja) * | 1996-08-30 | 1998-03-17 | Mitsui High Tec Inc | 半導体装置用リードフレーム |
CN1574300A (zh) * | 2003-05-22 | 2005-02-02 | 新光电气工业株式会社 | 封装组件和半导体封装 |
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US5041901A (en) * | 1989-05-10 | 1991-08-20 | Hitachi, Ltd. | Lead frame and semiconductor device using the same |
EP0448266B1 (en) * | 1990-03-23 | 1996-06-05 | Motorola, Inc. | Surface mountable semiconductor device having self loaded solder joints |
JPH06196603A (ja) * | 1992-12-23 | 1994-07-15 | Shinko Electric Ind Co Ltd | リードフレームの製造方法 |
JP2000003988A (ja) * | 1998-06-15 | 2000-01-07 | Sony Corp | リードフレームおよび半導体装置 |
US6593643B1 (en) * | 1999-04-08 | 2003-07-15 | Shinko Electric Industries Co., Ltd. | Semiconductor device lead frame |
JP2002134360A (ja) * | 2000-10-24 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 固体電解コンデンサおよびその製造方法 |
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JPH0494563A (ja) * | 1990-08-10 | 1992-03-26 | Nec Corp | 表面実装型半導体装置およびその製造方法 |
JPH1074879A (ja) * | 1996-08-30 | 1998-03-17 | Mitsui High Tec Inc | 半導体装置用リードフレーム |
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