JP2010278425A - 半導体装置の作製方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
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- 230000001070 adhesive effect Effects 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims 1
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- RDOXTESZEPMUJZ-UHFFFAOYSA-N anisole Chemical compound COC1=CC=CC=C1 RDOXTESZEPMUJZ-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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Abstract
【解決手段】第1の基板上に互いに密着性の弱い第1の層と第2の層を形成し、第2の層上に第1の半導体素子層及び第1の絶縁層を形成し、第1の絶縁層中に第1の層に達するスルーホールを形成し、スルーホール底部に露出した第1の層を酸化させ、第1の絶縁層上及びスルーホール内部に第1の半導体素子層と電気的に接続される配線を形成し、第1の層と第2の層を分離することにより第1の基板から第1の半導体素子層及び配線を分離して配線を露出させる半導体装置の作製方法と、さらに、同様の作製工程により、分離された第2の半導体素子層と配線との間に、異方性導電接着材を設け、第1の半導体素子層と第2の半導体素子層は、異方性導電接着材及び配線によって電気的に接続されている半導体装置の作製方法に関する。
【選択図】図1
Description
本実施の形態を、図1(A)〜図1(D)、図2(A)〜図2(C)を用いて説明する。
本実施の形態を、図3(A)〜図3(B)、図8(A)〜図8(B)、図9(A)〜図9(D)を用いて説明する。
302 半導体素子層
303 平坦化膜
304 下地層
305 保護層
306 配線
307 絶縁膜
308 接着剤
309 支持基板
311 第1の層
312 第2の層
315 スルーホール
316a 配線
316b 配線
316c 配線
321 島状半導体膜
322 ゲート絶縁膜
323a サイドウォール
323b サイドウォール
324 ゲート電極
325a TFT
325b TFT
331 島状半導体膜
332 ゲート絶縁膜
333a サイドウォール
333b サイドウォール
334 ゲート電極
341 積層構造体
342 異方性導電接着剤
343 積層構造体
345 フレキシブル基板
350 基板
351 第1の層
352 第2の層
355 スルーホール
356 配線
358 接着剤
359 支持基板
360 半導体素子層
366a 配線
366b 配線
366c 配線
401 基板
402 第1の層
403 第2の層
405 絶縁層
406 スルーホール
406a スルーホール
406b スルーホール
407 配線
408 絶縁層
409 平坦化膜
411 支持基板
421 領域
421a 領域
421b 領域
427 配線
428 絶縁層
Claims (5)
- 第1の基板上に、互いに密着性の弱い第1の層と第2の層を形成し、
前記第2の層上に、第1の半導体素子層及び第1の絶縁層を形成し、
前記第1の絶縁層中に、前記第1の層に達するスルーホールを形成し、
前記スルーホール底部に露出した第1の層を酸化させ、
前記第1の絶縁層上及び前記スルーホール内部に、前記第1の半導体素子層と電気的に接続される配線を形成し、
前記第1の層と第2の層を分離することにより、前記第1の基板から、前記第2の層、前記第1の半導体素子層、前記第1の絶縁層、前記配線を分離して配線を露出させることを特徴とする半導体装置の作製方法。 - 請求項1において、
前記第1の層は、タングステン膜であり、
前記第2の層は、酸化珪素膜であることを特徴とする半導体装置の作製方法。 - 第1の基板上に、互いに密着性の弱い第1の層と第2の層を形成し、
前記第2の層上に、第1の半導体素子層及び第1の絶縁層を形成し、
前記第1の絶縁層中に、前記第1の層に達するスルーホールを形成し、
前記スルーホール底部に露出した第1の層を酸化させ、
前記第1の絶縁層上及び前記スルーホール内部に、前記第1の半導体素子層と電気的に接続される配線を形成し、
前記第1の層と第2の層を分離することにより、前記第1の基板から、前記第2の層、前記第1の半導体素子層、前記第1の絶縁層、前記配線を分離して配線を露出させ、
第2の基板上に、互いに密着性の弱い第3の層と第4の層を形成し、
前記第4の層上に、第2の半導体素子層を形成し、
前記第3の層と第4の層を分離することにより、前記第2の基板から、前記第4の層、前記第2の半導体素子層を分離し、
前記第2の半導体素子層と前記配線との間に、異方性導電接着剤を設け、
前記第1の半導体素子層と前記第2の半導体素子層は、前記異方性導電接着剤及び前記配線によって電気的に接続されていることを特徴とする半導体装置の作製方法。 - 請求項3において、
前記第1の層及び前記第3の層のそれぞれは、タングステン膜であり、
前記第2の層及び前記第4の層のそれぞれは、酸化珪素膜であることを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項4のいずれか1項において、
前記酸化工程は、過酸化水素水に浸す工程、あるいは、酸素プラズマを照射する工程であることを特徴とする半導体装置の作製方法。
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FR2996682B1 (fr) | 2012-10-10 | 2014-11-28 | Commissariat Energie Atomique | Procede ameliore d'interconnexion pour micro-imageur |
US9252047B2 (en) | 2014-01-23 | 2016-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Interconnect arrangement with stress-reducing structure and method of fabricating the same |
US9443872B2 (en) | 2014-03-07 | 2016-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP6917700B2 (ja) | 2015-12-02 | 2021-08-11 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US10586817B2 (en) * | 2016-03-24 | 2020-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method thereof, and separation apparatus |
US10181424B2 (en) * | 2016-04-12 | 2019-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Peeling method and manufacturing method of flexible device |
WO2017182909A1 (en) * | 2016-04-22 | 2017-10-26 | Semiconductor Energy Laboratory Co., Ltd. | Separation method and manufacturing method of flexible device |
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US20100273319A1 (en) | 2010-10-28 |
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