JP2010245235A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2010245235A
JP2010245235A JP2009091564A JP2009091564A JP2010245235A JP 2010245235 A JP2010245235 A JP 2010245235A JP 2009091564 A JP2009091564 A JP 2009091564A JP 2009091564 A JP2009091564 A JP 2009091564A JP 2010245235 A JP2010245235 A JP 2010245235A
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JP
Japan
Prior art keywords
insulating film
film
semiconductor device
wiring
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009091564A
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English (en)
Japanese (ja)
Other versions
JP2010245235A5 (https=
Inventor
Kotaro Nomura
晃太郎 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2009091564A priority Critical patent/JP2010245235A/ja
Priority to PCT/JP2010/000541 priority patent/WO2010113375A1/ja
Publication of JP2010245235A publication Critical patent/JP2010245235A/ja
Publication of JP2010245235A5 publication Critical patent/JP2010245235A5/ja
Priority to US13/243,011 priority patent/US20120007257A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H10P14/6905—Inorganic materials containing silicon being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/095—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by irradiating with electromagnetic or particle radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2009091564A 2009-04-03 2009-04-03 半導体装置及びその製造方法 Pending JP2010245235A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009091564A JP2010245235A (ja) 2009-04-03 2009-04-03 半導体装置及びその製造方法
PCT/JP2010/000541 WO2010113375A1 (ja) 2009-04-03 2010-01-29 半導体装置及びその製造方法
US13/243,011 US20120007257A1 (en) 2009-04-03 2011-09-23 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009091564A JP2010245235A (ja) 2009-04-03 2009-04-03 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2010245235A true JP2010245235A (ja) 2010-10-28
JP2010245235A5 JP2010245235A5 (https=) 2011-07-21

Family

ID=42827693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009091564A Pending JP2010245235A (ja) 2009-04-03 2009-04-03 半導体装置及びその製造方法

Country Status (3)

Country Link
US (1) US20120007257A1 (https=)
JP (1) JP2010245235A (https=)
WO (1) WO2010113375A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5671253B2 (ja) * 2010-05-07 2015-02-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9136160B2 (en) * 2012-06-29 2015-09-15 Institute of Microelectronics, Chinese Academy of Sciences Solid hole array and method for forming the same
US8742587B1 (en) * 2012-11-18 2014-06-03 United Microelectronics Corp. Metal interconnection structure
CN109545784A (zh) * 2017-09-22 2019-03-29 联华电子股份有限公司 半导体元件及其制作方法
US11018087B2 (en) 2018-04-25 2021-05-25 International Business Machines Corporation Metal interconnects
JP2021082703A (ja) 2019-11-19 2021-05-27 キオクシア株式会社 半導体装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004274020A (ja) * 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
JP2008288234A (ja) * 2007-05-15 2008-11-27 Toshiba Corp 半導体装置及び半導体装置の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200428586A (en) * 2003-04-08 2004-12-16 Matsushita Electric Industrial Co Ltd Electronic device and the manufacturing method thereof
JP3939711B2 (ja) * 2003-06-18 2007-07-04 富士通株式会社 半導体装置の製造方法
JP3977796B2 (ja) * 2003-10-29 2007-09-19 株式会社東芝 半導体装置
JP2005142325A (ja) * 2003-11-06 2005-06-02 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
JP4619705B2 (ja) * 2004-01-15 2011-01-26 株式会社東芝 半導体装置
US7208837B2 (en) * 2004-02-10 2007-04-24 United Microelectronics Corp. Semiconductor chip capable of implementing wire bonding over active circuits
US8004087B2 (en) * 2004-08-12 2011-08-23 Nec Corporation Semiconductor device with dual damascene wirings and method for manufacturing same
JP2007012996A (ja) * 2005-07-01 2007-01-18 Toshiba Corp 半導体装置
JP4589835B2 (ja) * 2005-07-13 2010-12-01 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
JP4523535B2 (ja) * 2005-08-30 2010-08-11 富士通株式会社 半導体装置の製造方法
JP4236201B2 (ja) * 2005-08-30 2009-03-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4567587B2 (ja) * 2005-12-12 2010-10-20 富士通株式会社 半導体装置の製造方法
JP4321570B2 (ja) * 2006-09-06 2009-08-26 ソニー株式会社 半導体装置の製造方法
JP2008288430A (ja) * 2007-05-18 2008-11-27 Toshiba Corp 半導体装置の製造方法
JP5067039B2 (ja) * 2007-06-25 2012-11-07 パナソニック株式会社 半導体装置の製造方法
JP2010182822A (ja) * 2009-02-04 2010-08-19 Renesas Electronics Corp 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004274020A (ja) * 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
JP2008288234A (ja) * 2007-05-15 2008-11-27 Toshiba Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
WO2010113375A1 (ja) 2010-10-07
US20120007257A1 (en) 2012-01-12

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