JP2009521816A - 高速回復整流器構造体の装置および方法 - Google Patents
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Abstract
Description
本出願は2005年12月27日に出願されるとともに本発明の譲受人に譲受された"Fast Recovery Rectifier Structure"と題された同時係属仮特許出願第60/754,550号の優先権を主張するものであり、その全体を本明細書に引用して援用する。
発明の分野
本発明の実施形態は整流器の分野に関する。特に本発明の実施形態は概して高速回復整流器構造体に関する。
スイッチング電源の効率における重要な要因はそのような回路で用いられるダイオードの性能である。特にそのようなダイオードの逆回復は、そのような電源のトランジスタスイッチのターンオン・ロスを低減することができる。例えば逆回復電流過渡がスイッチのターンオン時に電流の付加成分として出現し、スイッチのターンオン・ロスはそのような逆回復成分がない場合より大幅に高いという結果になる。その結果逆回復電荷(Qrr)を低減することがスイッチング電源の効率の改善に重要である。
そのためソフトリカバリ特性を維持する逆回復電荷が低減した高速回復整流器構造体が非常に望まれている。さらなる要求はより小型形状用のトレンチを用いて形成された高速回復整流器構造体で、上記の要求を満たすことである。さらに他の要求はこれが従来の半導体製造プロセスおよび機器と適合し且つ相補的であるように、上記の要求を満たすことである。
ここで本発明の好適な実施形態、高速回復整流器構造体および構造体の作製方法を詳細に参照して、それらの例を添付の図面で説明する。好適な実施形態に関連して本発明を説明するが、本発明をこれらの実施形態に限定しようとするものではないことは理解されよう。反対に本発明は添付の特許請求の範囲に規定された本発明の要旨と範囲とにある変更例、同等物および代替例をすべて網羅しようとするものである。
Claims (20)
- 第1のドーパント型がドープされた基板と、
前記基板に結合された前記第1のドーパント型がドープされた第1のエピタキシャル層と、
前記第1のエピタキシャル層に隣接する第1の金属層と、
前記第1のエピタキシャル層内に窪み、各々が前記金属層に結合された複数のトレンチと、
各々互いに離間されるとともに、各々前記複数のトレンチのうちの対応するトレンチの下に当該トレンチに隣接して形成された、各々第2のドーパント型がドープされた複数のウェルと、
対応するウェルが前記対応するトレンチから電気的に絶縁されるように、各々対応するトレンチの壁および底部上に形成された、複数の酸化物層と、
前記第1のエピタキシャル層内に形成された前記第1のドーパント型がドープされ、各々前記複数のウェルからの2つの対応するウェル間に位置するとともに、各々前記第1のエピタキシャル層より高濃度に前記第1のドーパント型にドープされた複数のチャネル領域と
を備える整流装置。 - 前記基板と前記第1のエピタキシャル層との間に位置する第2のエピタキシャル層をさらに備え、
前記第2のエピタキシャル層は、前記基板より低濃度にドープされているとともに、前記第1のエピタキシャル層より高濃度にドープされている、請求項1に記載の整流装置。 - ショットキー障壁が前記第1の金属層と前記第1のエピタキシャル層とを離間するように、前記第1の金属層の下に配置されたショットキー障壁をさらに備える請求項1に記載の整流装置。
- 複数のPiN領域をさらに備え、
前記複数のPiN領域の各々に対する前記ショットキー障壁の領域の比がおよそ1以上である、請求項3に記載の整流装置。 - 前記複数のトレンチの各々が非ドープシリコンを備える、請求項1に記載の整流装置。
- 前記第1のドーパント型はn型ドーパントである、請求項1に記載の整流装置。
- 前記複数のウェルおよび前記第1の金属層に結合され、遠隔に位置する複数のコンタクト領域をさらに備える請求項1に記載の整流装置。
- 第1のドーパント型がドープされた基板と、
前記基板に結合され前記第1のドーパント型が低濃度ドープされた第1のエピタキシャル層と、
前記第1のエピタキシャル層に隣接する第1の金属層と、
前記第1のエピタキシャル層内に窪むとともに前記金属層に結合された第1のトレンチと、
前記第1のトレンチの下に当該トレンチに隣接して形成され、第2のドーパント型がドープされた第1のウェルと、
前記第1のエピタキシャル層内に窪むとともに前記金属層に結合された第2のトレンチと、
前記第2のトレンチの下に当該トレンチに隣接して形成され、第2のドーパント型がドープされた第2のウェルと、
前記第1のエピタキシャル層内に形成されるとともに前記第1のウェルと前記第2のウェルとの間に位置する、前記第1のエピタキシャル層より高濃度に前記第1のドーパント型がドープされたチャネル領域と
を備える超高速ダイオード。 - 前記第1のウェルが前記第1のトレンチから電気的に絶縁されるように、前記第1のトレンチの壁および底部上に形成された第1の酸化物層と、
前記第2のウェルが前記第2のトレンチから電気的に絶縁されるように、前記第2のトレンチの壁および底部上に形成された第2の酸化物層と
をさらに備える、請求項8に記載の超高速ダイオード。 - 前記基板に隣接する第2の金属層をさらに備える、請求項8に記載の超高速ダイオード。
- 前記第1のドーパント型がn型ドーパントを備える、請求項8に記載の超高速ダイオード。
- 前記基板と前記第1のエピタキシャル層との間に位置する前記第1のドーパント型の第2のエピタキシャル層をさらに備え、
前記基板が前記第2のエピタキシャル層より高濃度にドープされ、前記第2のエピタキシャル層が前記第1のエピタキシャル層より高濃度にドープされているとともに、前記基板は前記第1のドーパント型がドープされている、請求項8に記載の超高速ダイオード。 - 前記基板に隣接する第2の金属層をさらに備える、請求項8に記載の超高速ダイオード。
- 前記第1のウェル、前記第2のウェル、および前記第1の金属層に結合された少なくとも1つの遠隔に位置するコンタクト領域をさらに備える、請求項8に記載の超高速ダイオード。
- 前記第1の金属層と前記第1の半導体層との間に位置するショットキー障壁をさらに備える、請求項8に記載の超高速ダイオード。
- PiN領域をさらに備え、
前記PiN領域に対する前記ショットキー障壁の領域の比がおよそ1以上である、請求項15に記載の超高速ダイオード。 - 第1のドーパント型がドープされた第2のエピタキシャル層を、前記第2のエピタキシャル層より高濃度に前記第1のドーパント型がドープされた基板上に堆積するステップと、
前記第1のドーパント型が低濃度にドープされた第1のエピタキシャル層を、前記第1のエピタキシャル層より高濃度にドープされた前記第2のエピタキシャル層上に堆積するステップと、
複数のトレンチを前記第1のエピタキシャル層内にエッチングするステップと、
前記複数のトレンチの各々の壁および底部上に複数の酸化物層を形成するステップと、
各々互いに離間されるとともに、各々対応するトレンチから電気的に絶縁された複数のウェルに、前記複数のトレンチの各々の底部付近で第2のドーパント型を注入するステップと、
第1の金属層を前記第1のエピタキシャル層上に堆積するステップと
を含む整流器構造体の作製方法。 - 前記第1のドーパント型を、前記複数のウェル間に規定される複数のチャネル領域内の前記第1のエピタキシャル層に注入するステップをさらに含み、
前記複数のチャネル領域が前記第1のエピタキシャル層より高濃度にドープされる、請求項17に記載の方法。 - ショットキー障壁が前記第1の金属層と前記第1のエピタキシャル層とを離間するように、前記第1の金属層の下にショットキー障壁を堆積するステップさらに含む、請求項17に記載の方法。
- 前記複数のウェルおよび前記第1の金属層に結合された複数の遠隔に位置するコンタクト領域を形成するステップをさらに含む、請求項17に記載の方法。
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