JP2009278082A - 薄膜トランジスタ及びその作製方法 - Google Patents
薄膜トランジスタ及びその作製方法 Download PDFInfo
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- JP2009278082A JP2009278082A JP2009101255A JP2009101255A JP2009278082A JP 2009278082 A JP2009278082 A JP 2009278082A JP 2009101255 A JP2009101255 A JP 2009101255A JP 2009101255 A JP2009101255 A JP 2009101255A JP 2009278082 A JP2009278082 A JP 2009278082A
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- semiconductor layer
- layer
- thin film
- film transistor
- insulating layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
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Abstract
【解決手段】絶縁表面を有する基板上に、ゲート電極を覆うゲート絶縁層と、該ゲート絶縁層に接し、非晶質構造の中に複数の結晶領域を含みチャネル形成領域を構成する半導体層と、ソース領域及びドレイン領域を形成する一導電型を付与する不純物半導体層と、該半導体層と該一導電型を付与する不純物半導体層との間の非晶質半導体により構成されるバッファ層とを有し、前記結晶化領域は、前記ゲート絶縁層と前記半導体層との界面から離れた位置から、前記半導体層が堆積される方向に向けて、前記一導電型を付与する不純物半導体層に達しない領域内において略放射状に成長した逆錐形状の構造を有する薄膜トランジスタとする。
【選択図】図2
Description
本実施の形態では、薄膜トランジスタの形態の一例について、図面を参照して説明する。
本実施の形態では、図1に示す薄膜トランジスタの作製方法であって、実施の形態1とは異なるものについて説明する。本実施の形態では、実施の形態1と同様に、逆錘形の形状を有する結晶粒を含む半導体層を形成する。ただし、半導体層に窒素を含ませる手段が異なる。
本実施の形態では、図1に示す薄膜トランジスタの作製方法であって、実施の形態1及び実施の形態2とは異なるものについて説明する。本実施の形態では、実施の形態1及び実施の形態2と同様に、逆錘形の形状を有する結晶粒を含む半導体層を形成する。ただし、半導体層に窒素を含ませる手段が異なる。
本実施の形態では、実施の形態1乃至実施の形態3とは異なる半導体装置の作製方法について説明する。本実施の形態では、実施の形態1と同様に、逆錘形の形状を有する結晶粒を含む半導体層を形成する。ただし、半導体層に窒素を含ませる手段が異なる。
本実施の形態では、薄膜トランジスタの形態の一例について、図面を参照して説明する。本実施の形態では、多階調マスクを用いることなく薄膜トランジスタを形成する。
本実施の形態では、表示装置の一形態として、実施の形態5で示す薄膜トランジスタを有する液晶表示装置について説明する。ここでは、VA(Vertical Alignment)型の液晶表示装置について、図17乃至図19を参照して説明する。VA型とは、液晶パネルの液晶分子の配列を制御する方式の一種をいう。VA型の液晶表示装置では、電圧が印加されていないときにパネル面に対して液晶分子が垂直方向を向く。本実施の形態では、特に画素(ピクセル)をいくつかの領域(サブピクセル)に分け、それぞれ別の方向に液晶分子を倒すよう工夫されている。これをマルチドメイン化あるいはマルチドメイン設計という。以下の説明では、マルチドメイン設計が考慮された液晶表示装置について説明する。
本実施の形態では、表示装置の一形態として、実施の形態5で示す薄膜トランジスタを有する発光表示装置について説明する。ここでは、発光表示装置が有する画素の構成の一例について説明する。図20(A)は画素の平面図を示し、図20(B)は図20(A)中の切断線A−Bに対応する断面構造を示す。
次に、表示装置が有する表示パネルの構成の一例について説明する。
上記実施の形態の薄膜トランジスタで構成される素子基板及びこれを用いた表示装置等は、アクティブマトリクス型の表示装置パネルに適用することができる。更には、これらを表示部に組み込んだ電子機器に適用することもできる。
102 ゲート電極層
104 ゲート絶縁層
105 半導体層
106 半導体層
107 バッファ層
108 バッファ層
109 ドナーとなる不純物元素を含む半導体層
110 ソース領域及びドレイン領域
111 導電層
112 配線層
114 絶縁層
116 画素電極層
120 第1の領域
121 結晶粒
122 第2の領域
131 第1のレジストマスク
132 第2のレジストマスク
141 処理室
142 ステージ
143 ガス供給部
144 シャワープレート
145 排気口
146 上部電極
147 下部電極
148 交流電源
149 温度制御部
150 ガス供給手段
151 排気手段
152 シリンダ
153 圧力調整弁
154 ストップバルブ
155 マスフローコントローラ
156 バタフライバルブ
157 コンダクタンスバルブ
158 ターボ分子ポンプ
159 ドライポンプ
160 クライオポンプ
161 プラズマCVD装置
180 グレートーンマスク
181 基板
182 遮光部
183 回折格子部
185 ハーフトーンマスク
186 基板
187 半透光部
188 遮光部
200 基板
202 ゲート電極層
204 ゲート絶縁層
205 半導体層
206 半導体層
207 バッファ層
208 バッファ層
209 ドナーとなる不純物元素を含む半導体層
210 ソース領域及びドレイン領域
211 導電層
212 配線層
214 絶縁層
216 画素電極層
231 第1のレジストマスク
232 第2のレジストマスク
250 基板
251 対向基板
252 ゲート電極
253 ゲート電極
254 配線
255 配線
256 配線
257 絶縁層
258 平坦化膜
259 開口部
260 画素電極
261 スリット
262 画素電極
263 開口部
264 薄膜トランジスタ
265 薄膜トランジスタ
266 遮光膜
267 着色膜
268 平坦化膜
269 対向電極
270 スリット
271 配向膜
272 配向膜
273 液晶層
280 容量素子
281a 薄膜トランジスタ
281b 薄膜トランジスタ
282 発光素子
283a 走査線
283b ゲート電極
284a 信号線
284b 配線
285a 電源線
285b 配線
286 絶縁層
287 平坦化膜
288 陰極
289 EL層
290 陽極
291 隔壁
292 保護絶縁膜
301 基板
302 画素部
303 信号線駆動回路
304 走査線駆動回路
305 FPC
306 保護回路
311 基板
312 画素部
313 信号線駆動回路
314 走査線駆動回路
315 FPC
316 保護回路
321 基板
322 画素部
323a アナログスイッチ
323b シフトレジスタ
324 走査線駆動回路
325 FPC
326 保護回路
331 筐体
332 表示パネル
333 主画面
334 モデム
335 受信機
336 リモコン操作機
337 表示部
338 サブ画面
339 スピーカ部
341 携帯電話機
342 表示部
343 操作部
351 本体
352 表示部
361 照明部
362 傘
363 可変アーム
364 支柱
365 台
366 電源
371 画素部
372 信号線駆動回路
373 走査線駆動回路
374 チューナ
375 映像信号増幅回路
376 映像信号処理回路
377 コントロール回路
378 信号分割回路
379 音声信号増幅回路
380 音声信号処理回路
381 制御回路
382 入力部
383 スピーカ
385 筐体
386 表示部
387 スピーカ
388 マイクロフォン
389 操作キー
390 ポインティングディバイス
391 表面カメラ用レンズ
392 外部接続端子ジャック
393 イヤホン端子
394 筐体
395 キーボード
396 外部メモリスロット
397 裏面カメラ
398 ライト
400 絶縁層
401 半導体層
403 破線
404 バッファ層
405 第1の部分
407 第2の部分
409 第3の部分
411 破線
413 ゲート絶縁層
415 半導体層
417 バッファ層
419 ドナーとなる不純物元素を含む半導体層
421 導電層
423 破線
Claims (19)
- ゲート電極と、
前記ゲート電極を覆うゲート絶縁層と、
前記ゲート絶縁層に接し、非晶質構造の中に複数の結晶領域を含みチャネル形成領域を構成する半導体層と、
ソース領域及びドレイン領域を形成する、一導電型を付与する不純物元素を含む半導体層と、
前記半導体層と前記一導電型を付与する不純物元素を含む半導体層との間にバッファ層と、を有し、
前記結晶領域は、前記ゲート絶縁層と前記半導体層との界面から離れた位置から、前記半導体層が堆積される方向に向かって略放射状に成長した逆錐形状の構造を有することを特徴とする薄膜トランジスタ。 - 請求項1において、
前記半導体層は、二次イオン質量分析法によって計測される酸素濃度が、5×1018cm−3以下であり、窒素濃度が1×1020cm−3乃至1×1021cm−3であることを特徴とする薄膜トランジスタ。 - 請求項2において、
前記窒素濃度は、前記ゲート絶縁層と前記半導体層との界面近傍において、二次イオン質量分析法によって計測されるピーク濃度が3×1020cm−3乃至1×1021cm−3であり、該界面近傍から前記半導体層が堆積される方向に向けて窒素濃度が減少していることを特徴とする薄膜トランジスタ。 - 請求項3において、
前記半導体層において、窒素濃度が1×1020cm−3以上3×1020cm−3以下の領域に、前記結晶領域の成長端が位置していることを特徴とする薄膜トランジスタ。 - 請求項1乃至請求項4のいずれか一において、
前記結晶領域は単結晶であることを特徴とする薄膜トランジスタ。 - 請求項5において、
前記単結晶は双晶を含むことを特徴とする薄膜トランジスタ。 - ゲート電極と、
ゲート電極を覆うゲート絶縁層と、
前記ゲート絶縁層に接し、非晶質構造の中に複数の結晶領域を含む第1半導体層と、
前記第1半導体層上に積層して設けられ、非晶質構造を有する第2半導体層と、
前記第2半導体層上に積層して設けられ、ソース領域及びドレイン領域を形成する、一導電型を付与する不純物元素を含む半導体層と、を有し、
前記結晶領域は、前記ゲート絶縁層と前記第1半導体層との界面から離れた位置から、前記第2半導体層に向かって略放射状に成長した逆錐形状の構造を有することを特徴とする薄膜トランジスタ。 - 請求項7において、
前記半導体層は、二次イオン質量分析法によって計測される酸素濃度が、5×1018cm−3以下であり、窒素濃度が1×1020cm−3乃至1×1021cm−3であることを特徴とする薄膜トランジスタ。 - 請求項8において、
前記窒素濃度は、前記ゲート絶縁層と前記半導体層との界面近傍において、二次イオン質量分析法によって計測されるピーク濃度が3×1020cm−3乃至1×1021cm−3であり、該界面近傍から前記半導体層の厚さ方向に向けて窒素濃度が減少していることを特徴とする薄膜トランジスタ。 - 請求項9において、
前記半導体層において、窒素濃度が1×1020cm−3以上3×1020cm−3以下の領域に、前記結晶領域の成長端が位置していることを特徴とする薄膜トランジスタ。 - 請求項7乃至請求項10のいずれか一において、
前記結晶領域は単結晶であることを特徴とする薄膜トランジスタ。 - 請求項11において、
前記単結晶は双晶を含むことを特徴とする薄膜トランジスタ。 - ゲート電極を形成し、
前記ゲート電極を覆ってゲート絶縁層を形成し、
前記ゲート絶縁層上に、非晶質構造の中に複数の結晶領域を含む半導体層を形成し、
前記半導体層上に、非晶質半導体により構成されるバッファ層を形成し、
前記バッファ層上にソース領域及びドレイン領域を形成する、一導電型を付与する不純物元素を含む半導体層を形成し、
前記一導電型を付与する不純物元素を含む半導体層上に、ソース電極及びドレイン電極を形成し、
前記非晶質構造の中に複数の結晶領域を含む半導体層は、半導体材料ガスと希釈ガスとを微結晶半導体の生成が可能な混合比で反応室内に導入し、
前記反応室においてグロー放電プラズマを生成し、堆積初期段階において結晶核の生成を妨害する不純物元素を含ませて被膜の堆積を開始し、該被膜が5nm以上20nm以下まで堆積された後に結晶核を生成させて形成することを特徴とする薄膜トランジスタの作製方法。 - 請求項13において、
前記半導体材料ガスと前記希釈ガスとを前記反応室に導入する前に、前記結晶核の生成を妨害する不純物元素を含むガスを一時的に前記反応室内に導入し、その後排気する処理を行うことを特徴とする薄膜トランジスタの作製方法。 - 請求項13において、
前記ゲート絶縁層として、前記結晶核の生成を妨害する不純物元素を含む絶縁層を形成することを特徴とする薄膜トランジスタの作製方法。 - 請求項13において、
前記結晶核の生成を妨害する不純物元素を含む膜を、前記反応室内に予め被着させておくことを特徴とする薄膜トランジスタの作製方法。 - 請求項13乃至請求項16のいずれか一において、
前記半導体材料ガスが、水素化シリコンガス、フッ化シリコンガス又は塩化シリコンガスであり、
前記希釈ガスが、水素ガスであることを特徴とする薄膜トランジスタの作製方法。 - 請求項13乃至請求項17のいずれか一において、
前記結晶核の生成を妨害する不純物元素が窒素であることを特徴とする薄膜トランジスタの作製方法。 - 請求項13乃至請求項18のいずれか一において、
前記ソース電極及びドレイン電極の形成に際して、前記ソース電極及びドレイン電極から露出する前記一導電型を付与する不純物元素を含む半導体層及び前記バッファ層の一部をドライエッチングにより除去し、
前記ドライエッチングにより露出させた前記半導体層の表面をプラズマ処理することを特徴とする薄膜トランジスタの作製方法。
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KR101635625B1 (ko) | 2016-07-01 |
CN102007585B (zh) | 2013-05-29 |
US20100096631A1 (en) | 2010-04-22 |
US8138032B2 (en) | 2012-03-20 |
TWI521713B (zh) | 2016-02-11 |
JP5464894B2 (ja) | 2014-04-09 |
TW201001714A (en) | 2010-01-01 |
CN102007585A (zh) | 2011-04-06 |
WO2009128553A1 (en) | 2009-10-22 |
KR20100135885A (ko) | 2010-12-27 |
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