JP5498762B2 - 薄膜トランジスタの作製方法 - Google Patents
薄膜トランジスタの作製方法 Download PDFInfo
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- JP5498762B2 JP5498762B2 JP2009257696A JP2009257696A JP5498762B2 JP 5498762 B2 JP5498762 B2 JP 5498762B2 JP 2009257696 A JP2009257696 A JP 2009257696A JP 2009257696 A JP2009257696 A JP 2009257696A JP 5498762 B2 JP5498762 B2 JP 5498762B2
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- film transistor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Description
本実施の形態では、薄膜トランジスタの作製方法について、図1乃至図9を用いて示す。薄膜トランジスタは、p型よりもn型の方が、キャリアの移動度が高い。また、同一の基板上に形成する薄膜トランジスタを全て同じ極性に統一すると、工程数を抑えることができ、好ましい。そのため、本実施の形態では、n型の薄膜トランジスタの作製方法について説明する。
本実施の形態では、ゲート絶縁層105、第1の半導体層106、第2の半導体層107、及び不純物半導体層109の形成に用いることが可能なプラズマCVD装置の一形態について詳細に説明する。これらの層はCVD法等を用いて形成する。
本実施の形態では、実施の形態1に適用可能な第2の半導体層107の形成工程について説明する。
本実施の形態では、実施の形態1に適用可能な第2の半導体層107の形成工程について説明する。
実施の形態1において、第2の半導体層107の作製方法について、図9を用いて示す。
実施の形態1とは異なる薄膜トランジスタの作製方法について、図10及び図11を用いて示す。
本実施の形態では、チャネル長が10μm以下と短い薄膜トランジスタにおいて、ソース領域及びドレイン領域の抵抗を低減することが可能な形態について、以下に示す。ここでは、実施の形態1を用いて説明するが、適宜他の実施の形態に適用可能である。
本実施の形態では、実施の形態1乃至実施の形態7で示す薄膜トランジスタを用いることが可能な、素子基板、及び当該素子基板を有する表示装置について、以下に示す。表示装置としては、液晶表示装置、発光表示装置、電子ペーパー等があるが、上記実施の形態の薄膜トランジスタは他の表示装置の素子基板にも用いることができる。ここでは、上記実施の形態1で示す薄膜トランジスタを有する液晶表示装置、代表的には、VA(Vertical Alignment)型の液晶表示装置について、図12及び図13を用いて説明する。
実施の形態8で示す素子基板313において、配向膜311を形成せず、発光素子を設けることにより、当該素子基板を発光表示装置や、発光装置に用いることができる。発光表示装置や発光装置は、発光素子として代表的には、エレクトロルミネッセンスを利用する発光素子がある。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって大別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
上記実施の形態に係る薄膜トランジスタを有する表示装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、電子ペーパー、デジタルカメラやデジタルビデオカメラ等のカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。特に、実施の形態8及び実施の形態9で示したように、上記実施の形態に係る薄膜トランジスタを液晶表示装置、発光装置、電気泳動方式表示装置などに適用することにより、電子機器の表示部に用いることができる。以下に具体的に例示する。
Claims (3)
- 基板上のゲート電極と、
前記ゲート電極上のゲート絶縁層と、
前記ゲート絶縁層上の半導体層と、
前記半導体層上の不純物元素を含む半導体層と、
前記不純物元素を含む半導体層上のソース電極とドレイン電極とを有する薄膜トランジスタの作製方法であって、
前記半導体層は、前記ゲート絶縁層側から、第1の層と、前記第1の層上の第2の層と、前記第2の層上の第3の層とを有し、
前記第1の層は、微結晶半導体層であり、
前記第2の層は、微結晶半導体領域と、非晶質半導体領域とを有し、
前記第3の層は、非晶質半導体層であり、
前記第1の層は、前記ゲート絶縁層側の第1の領域と、前記第1の部分上の第2の領域とを有し、
シリコンまたはゲルマニウムを含む堆積性気体と、水素と、希ガスとを混合し、シリコンまたはゲルマニウムを含む堆積性気体の流量に対して、水素の流量を10〜2000倍にし、高周波電力を印加することで、前記第1の領域を形成し、
前記第1の領域を形成後、シリコンまたはゲルマニウムを含む堆積性気体と、水素と、窒素を含む気体を混合し、シリコンまたはゲルマニウムを含む堆積性気体の流量に対して、水素の流量を10〜2000倍にし、高周波電力を印加することで、前記第2の領域と前記第2の層と前記第3の層とを形成することを特徴とする薄膜トランジスタの作製方法。 - 請求項1において、
前記第2の領域は、前記第1の領域を種結晶として結晶成長することで形成されることを特徴とする薄膜トランジスタの作製方法。 - 請求項1または請求項2において、
前記第2の層の前記微結晶半導体領域は、前記第1の層から前記第3の層に向かって、先端が狭まる凸状の領域であり、
前記第2の層の前記微結晶半導体領域以外は、前記非晶質半導体領域であることを特徴とする薄膜トランジスタの作製方法。
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