JP5542364B2 - 薄膜トランジスタの作製方法 - Google Patents
薄膜トランジスタの作製方法 Download PDFInfo
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- JP5542364B2 JP5542364B2 JP2009099587A JP2009099587A JP5542364B2 JP 5542364 B2 JP5542364 B2 JP 5542364B2 JP 2009099587 A JP2009099587 A JP 2009099587A JP 2009099587 A JP2009099587 A JP 2009099587A JP 5542364 B2 JP5542364 B2 JP 5542364B2
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- Prior art keywords
- semiconductor layer
- layer
- thin film
- film transistor
- semiconductor
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Description
本実施の形態では、本発明の一態様に係る薄膜トランジスタについて、図面を参照して説明する。
本実施の形態では、実施の形態1と異なる薄膜トランジスタの作製方法について、図6乃至図7を用いて説明する。実施の形態1の薄膜トランジスタの構造上の相違点は、第1の半導体層108の有無である。本実施の形態で説明する薄膜トランジスタは、第2の半導体層109(非晶質構造を有する半導体層)が、本発明の一態様に係る薄膜トランジスタのチャネル形成領域として機能する。以下、本実施の形態に係る薄膜トランジスタの作製方法について説明する。本実施の形態では、nチャネル型の薄膜トランジスタの作製方法について説明する。なお、図1に示す薄膜トランジスタの作製方法と重複する部分に関しては、省略或いは簡略化して説明する。
本実施の形態では、上記実施の形態と異なる薄膜トランジスタの作製工程について説明する。
本実施の形態では、表示装置の一形態として、実施の形態3で示す薄膜トランジスタを有する液晶表示装置について、以下に示す。ここでは、VA(Vertical Alignment)型の液晶表示装置について、図11乃至図13を用いて説明する。VA型の液晶表示装置とは、液晶パネルの液晶分子の配列を制御する方式の一種である。VA型の液晶表示装置は、電圧が印加されていないときにパネル面に対して液晶分子が垂直方向を向く方式である。本実施の形態では、特に画素(ピクセル)をいくつかの領域(サブピクセル)に分け、それぞれ別の方向に分子を倒すよう工夫されている。これをマルチドメイン化あるいはマルチドメイン設計という。以下の説明では、マルチドメイン設計が考慮された液晶表示装置について説明する。
本実施の形態では、表示装置の一形態として、実施の形態3で示す薄膜トランジスタを有する発光表示装置について、以下に示す。ここでは、発光表示装置が有する画素の構成について説明する。図14(A)に、画素の上面図の一形態を示し、図14(B)に図14(A)中の切断線A−Bに対応する断面構造の一形態を示す。
次に、本発明の一態様の表示装置の一形態である表示パネルの構成について、以下に示す。
本発明の一態様に係る薄膜トランジスタで構成される素子基板、及びそれを用いた表示装置等によって、アクティブマトリクス型表示装置パネルを作製することができる。即ち、それらを表示部に組み込んだ電子機器全てに本発明の一態様を実施できる。
102 ゲート電極層
103 ゲート絶縁膜
104 半導体膜
105 半導体膜
106 不純物半導体膜
107 レジストマスク
108 半導体層
109 半導体層
110 不純物半導体層
111 導電膜
112 レジストマスク
113 配線層
114 半導体層
115 不純物半導体層
116 絶縁層
117 絶縁層
118 画素電極層
119 レジストマスク
120 導電層
121 レジストマスク
122 配線層
130 被処理物
180 グレートーンマスク
181 基板
182 遮光部
183 回折格子部
185 ハーフトーンマスク
186 基板
187 半透光部
188 遮光部
201 真空容器
202 プラズマ発生室
203 放電管
204 ガス導入管
205 放電コイル
206 RF電源
207 ダウンフロー室
208 ヒータ
209 排気口
211 マスフローコントローラ
212 ベーパライザー
213 シリンダ
214 ガス供給手段
215 ステージ
281a 薄膜トランジスタ
281b 薄膜トランジスタ
282 発光素子
283a 走査線
283b ゲート電極
284a 信号線
284b 配線
285a 電源線
285b 配線
286 絶縁膜
287 平坦化膜
288 陰極
289 発光層
290 陽極
291 隔壁
292 保護絶縁膜
500 基板
501 対向基板
502 ゲート配線
503 ゲート配線
516 配線
518 配線
519 配線
520 パッシベーション膜
522 平坦化膜
523 コンタクトホール
524 画素電極
525 スリット
526 画素電極
527 コンタクトホール
528 薄膜トランジスタ
529 薄膜トランジスタ
532 遮光膜
536 着色膜
537 平坦化膜
540 対向電極
541 スリット
546 配向膜
548 配向膜
550 液晶層
921 画素部
922 信号線駆動回路
923 走査線駆動回路
924 チューナ
925 映像信号増幅回路
926 映像信号処理回路
927 コントロール回路
928 信号分割回路
929 音声信号増幅回路
930 音声信号処理回路
931 制御回路
932 入力部
933 スピーカ
1001 基板
1002 ゲート電極
1003 ゲート絶縁膜
1004 微結晶シリコン膜
1005 非晶質シリコン膜
1006 不純物半導体膜
1008 微結晶シリコン層
1009 非晶質シリコン層
1010 不純物半導体層
1012 レジストマスク
1013 配線
1014 非晶質シリコン層
1015 不純物半導体層
1017 保護絶縁膜
1101 表示部
1102 スピーカ
1103 マイクロフォン
1104 操作キー
1105 ポインティングディバイス
1106 表面カメラ用レンズ
1107 外部接続端子ジャック
1108 イヤホン端子
1109 筐体
1111 筐体
1201 キーボード
1202 外部メモリスロット
1203 裏面カメラ
1204 ライト
2001 筐体
2002 表示用パネル
2003 主画面
2004 モデム
2005 受信機
2006 リモコン操作機
2007 表示部
2008 サブ画面
2009 スピーカ部
2301 携帯電話機
2302 表示部
2303 操作部
2401 本体
2402 表示部
2501 照明部
2502 傘
2503 可変アーム
2504 支柱
2505 台
2506 電源
6011 基板
6012 画素部
6013 信号線駆動回路
6014 走査線駆動回路
6015 FPC
6016 保護回路
6021 基板
6022 画素部
6023 信号線駆動回路
6024 走査線駆動回路
6025 FPC
6026 保護回路
6031 基板
6032 画素部
6033a アナログスイッチ
6033b シフトレジスタ
6034 走査線駆動回路
6035 FPC
6036 保護回路
Claims (4)
- ゲート電極が設けられた絶縁表面を有する基板上にゲート絶縁層を形成し、
前記ゲート絶縁層上に、微結晶半導体層を形成し、
前記微結晶半導体層上に非晶質半導体層を形成し、
前記非晶質半導体層上に、ソース領域及びドレイン領域を形成する一導電型を付与する不純物元素を含む半導体層を形成し、
前記一導電型を付与する不純物元素を含む半導体層上に、レジストマスクを用いてソース電極及びドレイン電極を形成し、
前記ソース電極及びドレイン電極から露出する前記一導電型を付与する不純物元素を含む半導体層及びその下に接して形成されている層にある前記非晶質半導体層の一部を第1のドライエッチングにより除去し、
前記第1のドライエッチングにより露出した前記非晶質半導体層の一部を第2のドライエッチングにより除去し、
前記第2のドライエッチングにより露出した前記非晶質半導体層の表面にOH遊離基を含むプラズマ処理を行うことにより変質層を形成し、且つ前記プラズマ処理により前記レジストマスクを除去することを特徴とする薄膜トランジスタの作製方法。 - ゲート電極が設けられた絶縁表面を有する基板上にゲート絶縁層を形成し、
前記ゲート絶縁層上に、非晶質半導体層を形成し、
前記非晶質半導体層上に、ソース領域及びドレイン領域を形成する、一導電型を付与する不純物元素を含む半導体層を形成し、
前記一導電型を付与する不純物元素を含む半導体層上に、レジストマスクを用いてソース電極及びドレイン電極を形成し、
前記ソース電極及びドレイン電極から露出する前記一導電型を付与する不純物元素を含む半導体層及びその下に接して形成されている層にある前記非晶質半導体層の一部を第1のドライエッチングにより除去し、
前記第1のドライエッチングにより露出した前記非晶質半導体層の一部を第2のドライエッチングにより除去し、
前記第2のドライエッチングにより露出した前記非晶質半導体層の表面にOH遊離基を含むプラズマ処理を行うことにより変質層を形成し、且つ前記プラズマ処理により前記レジストマスクを除去することを特徴する薄膜トランジスタの作製方法。 - 請求項1又は請求項2において、
前記第2のドライエッチングは、前記絶縁表面を有する基板側には電力を投入せずに前記非晶質半導体層のエッチングを行うことを特徴とする薄膜トランジスタの作製方法。 - 請求項1乃至請求項3のいずれか一において、
前記プラズマ処理は、前記絶縁表面を有する基板を加熱することを特徴とする薄膜トランジスタの作製方法。
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2009
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- 2009-04-16 JP JP2009099587A patent/JP5542364B2/ja not_active Expired - Fee Related
- 2009-04-22 KR KR1020090034961A patent/KR101624484B1/ko active IP Right Grant
- 2009-04-22 TW TW098113349A patent/TWI478243B/zh not_active IP Right Cessation
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KR101624484B1 (ko) | 2016-05-26 |
US20100099226A1 (en) | 2010-04-22 |
JP2009283919A (ja) | 2009-12-03 |
TW201001562A (en) | 2010-01-01 |
US7998801B2 (en) | 2011-08-16 |
TWI478243B (zh) | 2015-03-21 |
KR20090113196A (ko) | 2009-10-29 |
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