JP2009164478A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
【解決手段】半導体装置1は、インタポーザ2の主面に半導体チップ4〜12がそれぞれ積層されたチップオンチップ構造からなる。半導体チップ4〜12は、貫通ビア4b〜12b,4c〜12cを介して電源電圧が供給されている。半導体チップ5〜12には、貫通ビア5b〜12b,5c〜12cにそれぞれ接続された貫通ビア5e〜12e,5f〜12fがそれぞれ設けられている。貫通ビア5e,6e、貫通ビア7e,8e、貫通ビア9e,10e、貫通ビア11e,12eはバンプ14を介して、貫通ビア5f,6f、貫通ビア7f,8f、貫通ビア9f,10f、貫通ビア11f,12fはバンプ15を介してそれぞれ接続されている。
【選択図】図1
Description
ことを特徴とする半導体装置。
図1は、本発明の実施の形態1による半導体装置の断面図、図2は、図1の半導体装置に用いられる半導体チップの上面図、図3は、図1の半導体装置に設けられたコントローラによる半導体チップの選択例を示す説明図、図4は、図1の半導体装置に設けられた半導体チップの等価回路の一例を示す説明図、図5は、図4の半導体チップにおける論理回路が動作していない場合の等価回路例を示す説明図、図6は、図4の半導体チップにおける論理回路が動作している場合の等価回路例を示す説明図、図7は、図1の半導体装置に設けられた半導体チップの等価回路の他の例を示す説明図である。
図8は、本発明の実施の形態2による半導体装置の断面図、図9は、図8の半導体装置における半導体チップの積層例を示す説明図、図10は、図9のA−A’断面図、図11は、図8の半導体チップにおける貫通ビア、および電極の配置の一例を示す説明図、図12は、図8の半導体チップにおける貫通ビア、および電極の配置の他の例を示す説明図である。
2 インタポーザ
2a 配線
3 接続用電極
3a〜3d 接続用電極
4 半導体チップ
4a〜4d 貫通ビア
5 半導体チップ
5a〜5f 貫通ビア
6 半導体チップ
6a〜6f 貫通ビア
7 半導体チップ
7a〜7f 貫通ビア
8 半導体チップ
8a〜8f 貫通ビア
9 半導体チップ
9a〜9f 貫通ビア
10 半導体チップ
10a〜10f 貫通ビア
11 半導体チップ
11a〜11f 貫通ビア
12 半導体チップ
12a〜12f 貫通ビア
13 バンプ
13a バンプ
13b バンプ
13c バンプ
14 バンプ
15 バンプ
16 パッケージ
17〜22 等価モデル
23,24,27,28 電極
25、26,29,30 配線
31,32 バンプ
ca1〜ca9 回路形成領域
CS チップ選択部
Claims (12)
- 第1の半導体チップと、前記第1の半導体チップの上方に2個が1組となるようにペアリングされた偶数個の複数の第2の半導体チップとが積層された構造の半導体装置であって、
前記第1の半導体チップは、
外部から供給される電源を前記第1の半導体チップの論理回路に供給する第1の電源供給用電極を備え、
前記第1の電源供給用電極は、
外部の電源電圧が接続される第1の電源電圧用電極と、
外部の基準電位が接続される第1の基準電位用電極とよりなり、
前記第2の半導体チップは、
前記第1の電源供給用電極を介して前記第2の半導体チップの論理回路に電源を供給する第2の電源供給用電極と、
前記第2の電源供給用電極に接続される第3の電源供給用電極とを備え、
前記第2の電源供給用電極は、
前記第1の電源電圧用電極を介して電源電圧が接続される第2の電源電圧用電極と、
前記第1の基準電位用電極を介して基準電位が接続される第2の基準電位用電極とよりなり、
前記第3の電源供給用電極は、
前記第2の電源電圧用電極を介して電源電圧が接続される第3の電源電圧用電極と、
前記第2の基準電位用電極を介して基準電位が接続される第3の基準電位用電極と、
ペアリングされた2つの前記第2の半導体チップにおける前記第3の電源電圧用電極を相互に接続する第1の電極接続部と、
ペアリングされた2つの前記第2の半導体チップにおける前記第3の基準電位用電極を相互に接続する第2の電極接続部とよりなり、
ペアリングされた前記第2の半導体チップは、
一方の前記第2の半導体チップが動作した際には、他方の前記第2の半導体チップが非動作となることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2の半導体チップは、半導体メモリであり、
前記第1の半導体チップは、前記第2の半導体チップを制御するコントローラであることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記コントローラは、
ペアリングされた2つの前記半導体メモリのうち、一方の前記半導体メモリが動作する際、他方の前記半導体メモリを非動作とする制御を行うことを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記第1の電源電圧用電極、および前記第1の基準電位用電極は、
前記第1の半導体チップの厚さ方向に貫通した電極よりなり、
前記第2の電源電圧用電極、前記第2の基準電位用電極、前記第3の電源電圧用電極、前記第3の基準電位用電極は、
前記第2の半導体チップの厚さ方向に貫通した電極よりなることを特徴とする半導体装置。 - 請求項1〜4のいずれか1項に記載の半導体装置において、
ペアリングされた前記2つの第2の半導体チップは、
前記第2の半導体チップの回路形成面が対向するようにそれぞれ実装されることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記第2の半導体チップに形成された前記第2の電源電圧用電極、前記第3の電源電圧用電極と、前記第2の基準電位用電極、前記第3の基準電位用電極とは、
前記第2の半導体チップの任意の一辺と平行となる基準線に対して対称となるように形成されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
ペアリングされる一方の前記第2の半導体チップにおける前記第2の電源電圧用電極、前記第3の電源電圧用電極、前記第2の基準電位用電極、および前記第3の基準電位用電極は、
ペアリングされる他方の前記第2の半導体チップに形成された前記第2の電源電圧用電極、前記第3の電源電圧用電極、前記第2の基準電位用電極、前記第3の基準電位用電極とミラー反転するようにそれぞれ形成されていることを特徴とする半導体装置。 - 2個が1組となるようにペアリングされた偶数個の第3の半導体チップが積層された構造の半導体装置であって、
前記第3の半導体チップは、
外部から供給される電源を前記第3の半導体チップの論理回路に供給する第4の電源供給用電極と、
前記第4の電源供給用電極に接続される第5の電源供給用電極とを備え、
前記第4の電源供給用電極は、
外部の電源電圧が接続される第4の電源電圧用電極と、
外部の基準電位が接続される第4の基準電位用電極とよりなり、
前記第5の電源供給用電極は、
前記第4の電源電圧用電極を介して電源電圧が接続される第5の電源電圧用電極と、
前記第4の基準電位用電極を介して基準電位が接続される第5の基準電位用電極と、
ペアリングされた2つの前記第3の半導体チップにおける前記第5の電源電圧用電極を相互に接続する第3の電極接続部と、
ペアリングされた2つの前記第3の半導体チップにおける前記第5の基準電位用電極を相互に接続する第4の電極接続部とよりなり、
ペアリングされた前記第3の半導体チップは、
一方の前記第3の半導体チップが動作した際には、他方の前記第3の半導体チップが非動作となることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記第4の電源電圧用電極、前記第5の電源電圧用電極、前記第4の基準電位用電極、および前記第5の基準電位用電極は、
前記第3の半導体チップの厚さ方向に貫通した電極よりなることを特徴とする半導体装置。 - 請求項8または9記載の半導体装置において、
ペアリングされた前記第3の半導体チップは、
前記第3の半導体チップの回路形成面が対向するようにそれぞれ実装されることを特徴とする半導体装置。 - 請求項10記載の半導体装置において、
前記第3の半導体チップに形成された前記第4の電源電圧用電極、前記第5の電源電圧用電極と、前記第4の基準電位用電極、前記第5の基準電位用電極とは、
前記第3の半導体チップの任意の一辺と平行となる基準線に対して対称となるように形成されていることを特徴とする半導体装置。 - 請求項10記載の半導体装置において、
ペアリングされる一方の前記第3の半導体チップにおける前記第4の電源電圧用電極、前記第5の電源電圧用電極、前記第4の基準電位用電極、および前記第5の基準電位用電極は、
ペアリングされる他方の前記第3の半導体チップに形成された前記第4の電源電圧用電極、前記第5の電源電圧用電極、前記第4の基準電位用電極、および前記第5の基準電位用電極とミラー反転するようにそれぞれ形成されていることを特徴とする半導体装置。
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