CN102598262A - 半导体装置和噪声抑制方法 - Google Patents

半导体装置和噪声抑制方法 Download PDF

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Publication number
CN102598262A
CN102598262A CN2010800509774A CN201080050977A CN102598262A CN 102598262 A CN102598262 A CN 102598262A CN 2010800509774 A CN2010800509774 A CN 2010800509774A CN 201080050977 A CN201080050977 A CN 201080050977A CN 102598262 A CN102598262 A CN 102598262A
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Prior art keywords
conductor
semiconductor chip
semiconductor device
conductive pattern
mounting object
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CN2010800509774A
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竹村浩一
石田尚志
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NEC Corp
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NEC Corp
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Publication of CN102598262A publication Critical patent/CN102598262A/zh
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Abstract

本发明涉及半导体装置和噪声抑制方法。第一半导体芯片（200）被安装在第二半导体芯片（100）上。第一半导体芯片（200）具有第一导体图案（222）。第二半导体芯片（100）具有第二导体图案（122）。第二导体图案（122）在平面图中在叠盖第一导体图案（222）的区域处形成。选自由第一导体图案（222）和第二导体图案（122）组成的组的至少一个元件具有重复结构。

Description

半导体装置和噪声抑制方法
技术领域
本发明涉及将半导体芯片安装到安装对象的半导体装置以及噪声抑制方法。
背景技术
半导体芯片的安装方法的示例包括在中介层（interposer）基板上安装半导体芯片的倒装芯片安装技术。在该方法中，半导体芯片被布置为使得其提供有互连层的面面向中介层侧，且因而中介层基板和半导体芯片通过凸块彼此连接。
此外，近年来，还提出了三维安装结构。在该结构中，多个半导体芯片在与彼此相同的方向上堆叠，且半导体芯片通过穿透半导体芯片的基板的通孔彼此连接。
日本特开专利公报No.2008-270363公开了以倒装芯片方式在电介质基板上安装高频半导体的高频封装中为电介质基板提供EBG结构。根据该技术，构成EBG结构的通过孔减弱电磁波，且这改善了高频半导体的输入和输出之间的高频的隔离特性。
相关文档
专利文档
[专利文档1]日本特开专利公报No.2008-270363。
发明内容
在上述倒装芯片安装或三维安装结构中，诸如下侧半导体芯片和中介层基板的半导体芯片和安装对象通过诸如凸块的连接构件彼此连接。该连接构件位于半导体芯片和安装对象之间的空隙中。因此，从连接构件辐射的电磁波可以通过半导体芯片和安装对象之间的空隙泄露到外部且变成噪声。
本发明的目的是提供一种半导体装置和一种噪声抑制方法，其能够防止电磁波通过半导体芯片和安装对象之间的空隙泄露到外部。
根据本发明的一个实施例，提供一种半导体装置，包括：
安装对象；
安装在安装对象上方的第一半导体芯片；
多个第一导体，它们被重复地提供给选自由该第一半导体芯片和该安装对象组成的组的一个元件；
第二导体，其被提供给选自由该第一半导体芯片和该安装对象组成的组的另一元件，该第二导体与该多个第一导体相对；以及
多个连接构件，它们提供在该安装对象和该第一半导体芯片之间的空隙处，该多个连接构件将该多个第一导体电连接到该第二导体，
其中该多个第一导体通过该多个连接构件和该第二导体彼此电连接。
根据本发明的另一实施例，提供一种半导体装置，包括：
安装对象；
安装在安装对象上方的第一半导体芯片；
多个第一导体，它们被重复地提供给选自由该安装对象和该第一半导体芯片组成的组的一个元件；
第二导体，其被提供给一个元件，该第二导体与该多个第一导体相对；
多个通孔，它们将该多个第一导体连接到该第二导体，
其中该多个第一导体通过该多个通孔和该第二导体彼此电连接。
根据本发明的又一实施例，提供一种噪声抑制方法，包括：
向在其上方安装半导体芯片的安装对象提供第一导体；以及
向该半导体芯片提供第二导体，该第二导体位于与第一导体相对的区域，
其中选自由该第一导体和该第二导体组成的组的至少一个元件被形成为具有重复结构，且通过使用该第一导体和该第二导体形成电磁带隙（EBG）结构，
该方法防止噪声从安装对象和第一半导体芯片之间的空隙泄露。
本发明使得有可能防止电磁波通过半导体芯片和安装对象之间的空隙泄露到外部。
附图说明
从下面的优选实施例和附图，本发明的上述和其他目的、特征和优点将更加显而易见。
图1示出图示根据第一实施例的半导体装置的配置的剖面图。
图2示出图示上侧半导体芯片和下侧半导体芯片之间的连接部分的配置的放大剖面图。
图3示出图示第一区域和EBG结构之间的位置关系的平面示意图。
图4示出图示根据第二实施例的半导体装置的配置的剖面图。
图5示出图示根据第三实施例的半导体装置的配置的剖面图。
图6示出图示根据第四实施例的半导体装置的配置的剖面图。
图7示出图示根据第五实施例的半导体装置的配置的剖面图。
图8示出图示根据第六实施例的半导体装置的配置的剖面图。
图9示出图示根据第七实施例的半导体装置的配置的剖面图。
图10示出图示根据第八实施例的半导体装置的配置的剖面图。
图11示出图示根据第九实施例的半导体装置的配置的剖面图。
图12示出图示根据第十实施例的半导体装置的配置的剖面图。
图13示出图示根据第十一实施例的半导体装置的配置的剖面图。
具体实施方式
此后，将参考附图描述本发明的实施例。在所有附图中，相似的参考数字将给予具有基本相同功能的相似部件，且将不再重复其描述。
图1示出图示根据第一实施例的半导体装置的配置的剖面图。该半导体装置包括中介层基板400、多个半导体芯片600、半导体芯片620以及用作外部连接端子的焊球630。多个半导体芯片600是存储器芯片且堆叠在中介层基板400的一面上。半导体芯片620是系统LSI，且安装在中介层基板400的另一面上。多个半导体芯片600和半导体芯片620在平面图中彼此叠盖。
半导体芯片600以使得其有源面（即，在其上形成诸如晶体管的元件、多层布线以及重新分布层的面）面向相对于中介层基板400的相对方向的方式堆叠。半导体芯片600中的每一个具有通孔（如图2所示），且通过通孔连接到位于下侧的另一半导体芯片600或中介层基板400。最下面的半导体芯片600的通孔通过通孔和提供给中介层基板400的互连连接到半导体芯片620。
焊球630中的每一个是用于将半导体装置连接到主板等的外部连接端子且在其上安装半导体芯片620的中介层基板400的面上提供。焊球630和半导体芯片620通过通孔和提供给中介层基板400的互连连接到焊球630。
多个半导体芯片600通过中介层基板400的一面上的封装树脂640密封，且半导体芯片620通过中介层基板400的另一面上的封装树脂642密封。
图2示出图示第一半导体芯片200和第二半导体芯片100之间的连接部分的配置的放大剖面图。第一半导体芯片200是上侧半导体芯片600。第二半导体芯片100是下侧半导体芯片600。在该图示出的示例中，第一半导体芯片200安装在第二半导体芯片100上。第一半导体芯片200具有切割成导体片的第一导体图案222，且第二半导体芯片100具有连接到切割成导体片的第一导体图案222的导体图案122。导体图案122中的每一个在平面图中在叠盖切割成导体片的第一导体图案222中的每一个的区域处形成。在切割成导体片的第一导体图案222和导体图案122中，至少切割成导体片的第一导体图案222具有重复结构，例如周期结构。第一导体图案222和第二导体图案122构成电磁带隙（EBG）结构20的至少一部分。即，在该实施例中，导体图案122和切割成导体片的第一导体图案222在它们彼此面对的区域具有重复结构，且该重复结构形成为在厚度方向上从第二半导体芯片100跨越到第一半导体芯片200。重复结构连接到选自由导体图案122和切割成导体片的包括重复结构的第一导体图案222组成的组的一个元件。
在图中示出的示例中，切割成导体片的第一导体图案222在第一半导体芯片200的相对于第二半导体芯片100的面上形成。导体图案122在第二半导体芯片100的相对于第一半导体芯片200的面上形成。
第二半导体芯片100包括在与第一半导体芯片200相对的面上用于堆叠结构的多层布线110和重新分布层，从而以重复方式堆叠导体层和绝缘层。重新分布层包括用作导体图案122的多个岛状导体图案。多层布线110包括片状第一导体平面112和多个通孔114。用作导体图案122的多个岛状导体图案周期性地布置。第一导体平面112相对于导体图案122位于下层，且在平面图中在叠盖导体图案122的区域中延伸。多个通孔114将用作导体图案122的多个岛状导体图案中的每一个连接到第一导体平面112。第一导体平面112连接到电源线或接地线，例如连接到电源线。
切割成导体片的第一导体图案222是在平面图中在叠盖用作导体图案122的多个岛状导体图案的每个位置处以岛的形状形成的岛状导体图案。另外，“岛状”的意思在于切割成导体片的第一导体图案222在层中彼此隔离，且切割成导体片的第一导体图案222的形状不仅限于四边形、圆形等，且可以是诸如线、通过盘绕线形成的平面线圈等的形状。第一半导体芯片200包括绝缘层210。绝缘层210位于切割成导体片的第一导体图案222和基板之间。在该图中示出的示例中，绝缘层210被提供在第一半导体芯片200的基板的背面上。切割成导体片的第一导体图案222在绝缘层210上形成。绝缘层210例如由氧化硅膜、氮化硅膜或氧氮化硅膜形成。
图2中示出的半导体装置包括用作连接构件的多个凸块302。凸块302中的每一个将用作导体图案122的多个岛状导体图案中的每一个连接到用作切割成导体片的第一导体图案222的多个岛状导体图案中的任意一个。在第一半导体芯片200中，第一导体图案222与包括在第一半导体芯片200中的其他导体是电无关的。在该实施例中，第一导体图案222不直接连接到包括在第一半导体芯片200中的其他导体。多个第一导体图案222通过多个凸块302、多个导体图案122、多个通孔114和导体图案112彼此电连接。
第一半导体芯片200具有通孔230，且第二半导体芯片100具有通孔130。通孔230的一端连接到用作第一外部连接端子的电极垫220，且通孔130的一端连接到用作第二外部连接端子的电极垫120。电极垫220在第一半导体芯片200的相对于第二半导体芯片100的面上（即在重新分布层中）形成。电极垫220布置在与切割成导体片的第一导体图案222相同的层中。电极垫120在第二半导体芯片100的相对于第一半导体芯片200的面上形成。电极垫120布置在与导体图案122相同的层中。电极垫220和120通过作为连接构件的凸块300彼此连接。通孔230和130、电极垫220和120以及凸块300布置在对应于不形成EBG结构20的区域的第一区域10中。
在该配置中，EBG结构20的单位单元50由切割成导体片的第一导体图案222的一个岛状导体图案、凸块302中的一个、导体图案122的一个岛状导体图案以及其中在平面图中第一导体平面112和第一半导体芯片200的基板叠盖切割成导体片的第一导体图案222中的一个的区域形成。单位单元50在平面图中是二维重复的，且例如，是周期性布置的。
在布置“重复”单位单元50的情况中，在彼此靠近定位的单位单元50中，优选地，相同通孔之间的距离（中心之间的距离）设置为处于用作假想噪声的电磁波的波长λ的一半内。“重复”的意思还包括任意单位单元50中的配置的一部分不完善的情况。在其中单位单元50具有二维布置的情况中，“重复”的意思还包括其中单位单元50是部分不完善的情况。“周期”的意思包括其中构成元件的部分在单位单元50的部分中偏离的情况或其中单位单元50的部分的布置本身偏离的情况。即，在“周期性”中允许一定程度的缺陷，因为尽管严格意义上周期性的缺失，只要单位单元50重复布置，则可以获得元材料属性。出现缺陷的假想原因包括其中互连或通孔被做成在单位单元之间穿透的情况、其中在向现有互连布局添加元材料结构的情况中由于现有通孔或图案、制造错误而不能放置单位单元的情况、其中现有通孔或图案用作单位单元的一部分的情况等。
EBG结构20是所谓的蘑菇型EBG结构，且第一导体平面112对应于连接到蘑菇的导体平面。通孔114、导体图案122和凸块302对应于蘑菇的电感部分，且切割成导体片的第一导体图案222对应于蘑菇的头部。第一半导体芯片200的基板（第三导体）对应于与蘑菇相对的第二导体平面且变成接地线。在这种配置中，EBG结构20的每个电容的幅度通过第一半导体芯片200和第二半导体芯片100之间的空隙以及切割成导体片的第一导体图案222的大小和布置控制。EBG结构20的电感组件通过通孔114的长度和直径控制。EBG结构20的带隙可以通过调节这些物理因素调节。
封装树脂640被注入在第一半导体芯片200和第二半导体芯片100之间。因此，EBG结构20的电容的幅度可以通过调节封装树脂640的材料调节。
图3示出图示第一区域和EBG结构20之间的位置关系的平面示意图。如图2所示，在第一区域10中提供通孔230和130、电极垫220和120以及凸块300。与EBG结构20相比，第一区域10布置在第一半导体芯片200的中心侧。EBG结构20形成为环绕第一区域10。图2对应于沿着图3的A-A’截取的剖面图。
接下来，将描述该实施例的操作和效果。在该实施例中，EBG结构20使用切割成导体片的第一半导体图案222和导体图案122形成。切割成导体片的第一导体图案222在第一半导体芯片200中形成。导体图案122在第二半导体芯片100中形成。因而，EBG结构20在第一半导体芯片200和第二半导体芯片100之间的空隙中形成。因此，防止噪声在空隙中传播且辐射到外部。
用于噪声的源的示例包括凸块300。如果若干半导体芯片600像该实施例一样垂直且相邻堆叠，则多个半导体芯片600可以同时切换，且因而从凸块300辐射的噪声增加。如果EBG结构20以从凸块300辐射的噪声的频率被包括在EBG结构20的带隙中的这种方式设计，则防止从凸块300辐射的噪声从第一半导体芯片200和第二半导体芯片100之间的空隙泄露。
在该实施例中，切割成导体片的第一导体图案222与将要成为第二导体平面的第一半导体芯片200的基板相对。绝缘层210插入在第一导体图案222和第一半导体芯片200的基板之间。因此，在EBG结构20中，主要决定带隙的电容组件可以被计算为由切割成导体片的第一导体图案222和第一半导体芯片200的基板形成的简单平行板电容。因而，EBG结构20中的电容的设计变得简单。尤其在该实施例中，存在调节绝缘层210的厚度和材料的灵活度，且因此上述效果增加。
图4示出图示根据第二实施例的半导体装置的配置的剖面图。该图对应于第一实施例中的图2。根据该实施例的半导体装置与根据第一实施例的半导体装置具有相同的配置，除了第一半导体芯片200的基板在与第二半导体芯片100相对的面中提供有杂质区域202（第三导体）。杂质区域202在平面图中在叠盖构成切割成导体片的第一导体图案222的多个岛状导体图案的区域中延伸。在EBG结构20中，杂质区域202对应于蘑菇型EBG结构中的第二导体平面。
根据该实施例，可以获得与第一实施例相同的效果。另外，可以通过调节杂质区域202的杂质浓度调节有效电容，且因而可以控制EBG结构20的带隙。尤其在低电阻中，可以提高每单位面积的电容。因而，既使使用相同的面积，EBG结构20的带隙可以向低频侧偏移。 
图5示出图示根据第三实施例的半导体装置的配置的剖面图。该图对应于第一实施例中的图2。除了以下方面，根据该实施例的半导体装置与根据第一实施例的半导体装置具有相同的配置。
首先，第二半导体芯片100不提供有通孔114。第一半导体芯片200具有多个通孔212。多个通孔212提供在绝缘层210中，且将切割成导体片且以多个岛状导体图案形成的第一导体图案222连接到第一半导体芯片200的基板。第二导体图案122不直接连接到包括在第二半导体芯片100中的其他导体。
在该实施例中，EBG结构20也是所谓的蘑菇型EBG结构，且具有从第一实施例中的EBG结构20的结构垂直反转的结构。即，EBG结构20具有其中第一导体平面112（第三导体）与蘑菇的头部相对的结构。第一半导体芯片200的基板对应于连接到蘑菇的导体平面。通孔212、第一导体图案222和凸块302对应于蘑菇的电感部分。切割成导体片的第二导体图案112对应于蘑菇的头部。多个第二导体图案122通过多个凸块302、多个第一导体图案222、多个通孔212和第一半导体芯片200的基板彼此电连接。
根据该实施例，可以获得与第一实施例相同的效果。
图6示出图示根据第四实施例的半导体装置的配置的剖面图。该图对应于第三实施例中的图5。根据该实施例的半导体装置与根据第三实施例的半导体装置具有相同的配置，除了第一半导体芯片200的基板在与第二半导体芯片100相对的面中提供有杂质区域202。杂质区域202在平面图中在叠盖构成第一导体图案222的多个岛状导体图案的区域中延伸。在EBG结构20中，杂质区域202对应于蘑菇型EBG结构中的下侧导体平面。多个第二导体图案122通过多个凸块302、多个第一导体图案222、多个通孔212以及杂质区域202彼此电连接。
根据该实施例，可以获得与第三实施例相同的效果。另外，蘑菇型EBG结构中的下侧导体平面的电阻可以做得很低。因此，EBG结构20的带隙的上升和下降可以变陡。
图7示出图示根据第五实施例的半导体装置的配置的剖面图。该图对应于第一实施例中的图2。除了以下方面，根据该实施例的半导体装置与根据第一实施例的半导体装置具有相同的配置。
首先，第一半导体芯片200提供有导体图案250（第三导体）和绝缘层240。导体图案250具有片形状且在绝缘层210上形成。绝缘层240在导体图案250上形成。构成切割成导体片的第一导体图案222的多个岛状导体图案在绝缘层240上形成。
在该实施例中，通孔230是电源线或接地线，且通过导体图案250和在绝缘层240中提供的导体图案242连接到电极垫220。即，导体图案250连接到通孔230。
在该实施例中，像第一实施例一样，EBG结构20是所谓的蘑菇型EBG结构。然而，取代第一半导体芯片200的基板，导体图案250对应于上侧导体平面。
根据该实施例，也可以获得与第一实施例相同的效果。另外，由第一导体图案222和导体图案250形成的电容可以通过绝缘层240的材料和厚度控制。因而，带隙的控制可以更加容易。
图8示出图示根据第六实施例的半导体装置的配置的剖面图。该图对应于第七实施例中的图7。除了以下方面，根据该实施例的半导体装置与根据第七实施例的半导体装置具有相同的配置。
首先，第二半导体芯片100不提供有通孔114。第一半导体芯片200具有多个通孔244。多个通孔244被提供在绝缘层240中，且切割成导体片的第二导体图案122通过凸块302和导体图案222连接到片状导体图案250。
类似于第三实施例， EBG结构20是所谓的蘑菇型EBG结构且具有从第一实施例中的EBG结构20的结构垂直反转的结构。即，第一导体平面112对应于与蘑菇的头部相对的导体平面。第一半导体芯片200的导体图案250对应于下侧导体平面。通孔244、导体图案222和凸块302对应于蘑菇的电感部分。切割成导体片的第二导体图案122对应于蘑菇的头部。多个第二导体图案122通过多个凸块302、多个第一导体图案222、多个通孔244以及导体图案250彼此电连接。
根据该实施例，可以获得与第一实施例相同的效果。另外，不必改变第二半导体芯片100的多层布线。EBG结构还可以在不针对堆叠设计的半导体芯片上形成。
图9示出图示根据第七实施例的半导体装置的配置的剖面图。该半导体装置与第一至第六实施例中的任意一个相同，除了EBG结构22提供在半导体芯片600中的最低半导体芯片602和中介层基板400之间。
在该实施例中，半导体芯片602与第一半导体芯片200具有相同的配置，且提供有绝缘层210、电极垫220、切割成导体片的第一导体图案222以及通孔230。
中介层基板400提供有第二导体图案422、通孔414、平面导体图案412以及电极垫420。电极垫420通过凸块300连接到电极垫220。第二导体图案422、通孔414和导体图案412在平面图中具有与第一实施例中的导体图案122、通孔114以及第一导体图案112相同的布局。导体图案412连接到电源线或接地线，例如连接到电源线。
在该实施例中，EBG结构22的单位单元52具有类似于第一实施例的单位单元50的蘑菇结构。具体而言，导体图案412对应于连接到蘑菇结构的导体平面。通孔414、第二导体图案422以及凸块302对应于蘑菇的电感部分。切割成导体片的第一导体图案222对应于蘑菇的头部。第一半导体芯片200的基板对应于与蘑菇的头部相对的导体平面。EBG结构22形成为环绕第一区域10。多个第一导体图案222通过多个凸块302、多个导体图案412、多个通孔414和导体图案412彼此电连接。
根据该实施例，可以获得与第一实施例相同的效果。另外，EBG结构22使用切割成导体片的第一导体图案222和第二导体图案422形成。切割成导体片的第一导体图案222在半导体芯片602中形成。第二导体图案422在中介层基板400中形成。因而，EBG结构22在半导体芯片602和中介层基板400之间的空隙中形成。因此，防止噪声在空隙中传播且辐射到外部。
图10示出图示根据第八实施例的半导体装置的配置的剖面图。除了以下方面，该半导体装置与根据图5中示出的第三实施例具有相同的配置。
首先，第一半导体芯片200和第二半导体芯片100通过执行在第一半导体芯片200中形成的电感器（未示出）和在第二半导体芯片100中形成的电感器124之间的通信来发射和接收彼此之间的信号。因此，不形成在图5中示出的通孔130和230以及凸块300。这导致不形成凸块302。即，在第一半导体芯片200和第二导体芯片100之间的空隙中不提供用于将第一导体图案222连接到第一导体平面112的导体。
EBG结构20不具有第二导体图案122和通孔114。该实施例中的EBG结构20是蘑菇型EBG结构，但是第一导体平面112对应于与蘑菇的头部相对的导体平面。第一半导体芯片200的基板对应于连接到蘑菇的导体平面。通孔212对应于蘑菇的电感部分。切割成导体片的第一导体图案222对应于蘑菇的头部。多个第一导体图案222通过多个通孔212和第一导体芯片200的基板彼此电连接。
根据该实施例，可以获得与第三实施例相同的效果。另外，无需凸块连接，且因此，制作工艺可以简单。
图11示出图示根据第九实施例的半导体装置的配置的剖面图。除了EBG结构20的配置，该半导体装置与根据图10中示出的第八实施例的半导体装置具有相同的配置。
该实施例中的EBG结构20不包括通孔212和第一导体图案222。而是，EBG结构20包括杂质区域202、切割成导体片的第二导体图案122以及通孔114。杂质区域202、切割成导体片的第二导体图案122以及通孔114的配置类似于第二实施例中的图4中示出的配置。
该EBG结构20是蘑菇型EBG结构，但是杂质区域202对应于与蘑菇的头部相对的导体平面。第一导体平面112对应于连接到蘑菇的导体平面。通孔114对应于蘑菇的电感部分。切割成导体片的第二导体图案122对应于蘑菇的头部。多个第二导体图案122通过多个通孔114和导体图案112彼此电连接。
根据该实施例，可以获得与第八实施例相同的效果。另外，可以通过杂质区域202调节有效电容，且因而可以控制EBG结构20的带隙。尤其在低电阻，可以提高每单位面积的电容。因而，既使使用相同的面积，EBG结构20的带隙可以向低频侧偏移。在该实施例中，不必提供杂质区域202。在这种情况中，第一半导体芯片200的基板对应于蘑菇型EBG结构中的上侧导体平面。
图12示出图示根据第十实施例的半导体装置的配置的剖面图。除了EBG结构20的配置，该半导体装置与根据第一实施例的半导体装置具有相同的配置。
首先，第一导体图案222（第三导体）不具有岛形状且是片状导体图案。不提供凸块302。
该EBG结构20是蘑菇型EBG结构，但是平面第一导体图案222对应于与蘑菇的头部相对的导体平面。第一导体平面112对应于下侧导体平面。通孔114对应于蘑菇的电感部分。切割成导体片的第二导体图案122对应于蘑菇的头部。
根据该实施例，可以获得与第一实施例相同的效果。另外，因为凸块连接部分的数目小，所以可以提高半导体装置的产出率。
图15示出图示根据第十一实施例的半导体装置的配置的剖面图。在该半导体装置中，半导体芯片610以倒装芯片方式安装在中介层基板400上。半导体芯片610以使得其中形成多层布线650和重新分布层的面面朝下的方式安装在中介层基板400上。重新分布层的电极垫628通过凸块300连接到中介层基板400的电极垫420。电极垫628、凸块300和电极垫420布置在第一区域14中。
在重新分布层中提供用作导体片626的多个岛状导体图案。这些多个岛状导体图案通过凸块302连接到中介层基板400的岛状第二导体图案422。中介层基板400的配置类似于第七实施例示出的配置。
多层布线650包括片状导体平面616。导体平面616在导体片626下方的互连层中形成且在平面图中位于叠盖导体平面616的区域中。
EBG结构24的单位单元56具有与第一实施例的单位单元50相同的蘑菇结构。具体而言，导体图案412对应于连接到蘑菇的导体平面。通孔414、第二导体图案422和凸块302对应于蘑菇的电感部分。导体片626对应于蘑菇的头部。导体平面616对应于与蘑菇的头部相对的导体平面。另外，EGB结构24形成为环绕第一区域14。
在该实施例中，EBG结构24使用导体片626和第二导体图案422形成。导体片626在半导体芯片610上形成。第二导体图案422在中介层基板400上形成。因而，EBG结构24在半导体芯片610和中介层基板400之间的空隙中形成。因此，防止噪声在空隙中传播且辐射到外部。
此前，已经参考附图描述了本发明的实施例，但是这些描述仅是说明性的且可以采用不同于上述配置的各种配置。例如，EBG结构20至24的配置不限于上述实施例，且呈现EBG属性的任意结构可以作为EBG结构20至24应用。
本专利申请要求于2009年11月10日提交的日本专利申请No.2009-257070的优先权，此处通过引用并入该申请的公开内容。

Claims (14)

1.一种半导体装置，包括：
安装对象；
安装在该安装对象上方的第一半导体芯片；
多个第一导体，它们被重复地提供给选自由该第一半导体芯片和该安装对象组成的组的一个元件；
第二导体，其被提供给选自由该第一半导体芯片和该安装对象组成的组的另一元件，该第二导体与该多个第一导体相对；以及
多个连接构件，其被提供在安装对象和第一半导体芯片之间的空隙处，该多个连接构件将该多个第一导体电连接到该第二导体，
其中该多个第一导体通过该多个连接构件和第二导体彼此电连接。
2.根据权利要求1所述的半导体装置，还包括：
提供给该一个元件的第三导体，该第三导体位于该一个元件的内层处且位于第一导体下方，该第三导体与该多个第一导体相对，该第三导体不电连接到该一个元件中的第一导体。
3.根据权利要求1或2所述的半导体装置，
其中该第二导体在该另一元件的内层处形成，
该半导体装置还包括：
通孔，其被提供给该另一元件且将第二导体电连接到该连接构件。
4.根据权利要求1至3中的任一项所述的半导体装置，
其中该另一元件是第一半导体芯片，以及
该第二导体是第一半导体芯片的基板。
5.根据权利要求1至4中的任一项所述的半导体装置，
其中选自由该第一导体和该第二导体组成的组的一个元件被连接到电源，且另一元件被连接到地。
6.一种半导体装置，包括：
安装对象；
安装在安装对象上方的第一半导体芯片；
多个第一导体，它们被重复地提供给选自由安装对象和第一半导体芯片组成的组的一个元件；
被提供给该一个元件的第二导体，该第二导体与该多个第一导体相对；
多个通孔，它们将该多个第一导体连接到第二导体，
其中该多个第一导体通过该多个通孔和第二导体彼此电连接。
7.根据权利要求6所述的半导体装置，
其中该一个元件是第一半导体芯片，以及
该第二导体是第一半导体芯片的基板。
8.根据权利要求6或7所述的半导体装置，还包括：
第三导体，其被提供给选自由安装对象和第一半导体芯片组成的组的该另一元件，该第三导体与该多个第一导体相对。
9.根据权利要求1至8中的任一项所述的半导体装置，还包括：
第一外部连接端子，其被形成在第一半导体芯片的与安装对象相对的面上方；
第二外部连接端子，其被形成在安装对象的与第一半导体芯片相对的面上方；以及
连接构件，其将第一外部连接端子连接到第二外部连接端子，
其中第一导体和第二导体形成为在平面图中环绕第一外部连接端子、第二外部连接端子和连接构件。
10.根据权利要求1至9中的任一项所述的半导体装置，
其中该第一导体被形成在第一半导体芯片的与安装对象相对的面上方。
11.根据权利要求1至9中的任一项所述的半导体装置，
其中该第一导体被形成在安装对象的与第一半导体芯片相对的面上方。
12.根据权利要求1至11中的任一项所述的半导体装置，
其中该安装对象是中介层基板。
13.根据权利要求1至11中的任一项所述的半导体装置，
其中该安装对象是第二半导体芯片。
14.一种噪声抑制方法，包括：
向在其上方安装半导体芯片的安装对象提供第一导体；以及
向该半导体芯片提供第二导体，该第二导体位于与第一导体相对的区域，
其中选自由第一导体和第二导体组成的组的至少一个元件形成为具有重复结构，且通过使用第一导体和第二导体来形成电磁带隙（EBG）结构，
该方法防止噪声从安装对象和第一半导体芯片之间的空隙泄露。
CN2010800509774A 2009-11-10 2010-09-01 半导体装置和噪声抑制方法 Pending CN102598262A (zh)

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