JP2009147134A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009147134A JP2009147134A JP2007323293A JP2007323293A JP2009147134A JP 2009147134 A JP2009147134 A JP 2009147134A JP 2007323293 A JP2007323293 A JP 2007323293A JP 2007323293 A JP2007323293 A JP 2007323293A JP 2009147134 A JP2009147134 A JP 2009147134A
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- memory chip
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Abstract
【解決手段】積層された第1メモリチップと第2メモリチップ2において、上段の第2メモリチップ2の下に隠れた下段の前記第1メモリチップの第1パッドを再配線によって引き出すことで、上段の第2メモリチップ2から迫り出して露出した前記第1パッドと上段の第2メモリチップ2の第2パッド2dとをワイヤ接続することができる。さらに最上段の第2メモリチップ2上でマイコンチップ3と再配線2f上に形成した第3パッド2eとをワイヤ4で接続することにより、積層された複数のメモリチップのワイヤ接続をスペーサを介在させずに実現できる。
【選択図】図8
Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す平面図、図2は図1のA−A線に沿って切断した構造の一例を示す断面図、図3は図1のB−B線に沿って切断した構造の一例を示す断面図、図4は図2に示すA部の構造の一例を拡大して示す拡大断面図、図5は図1に示す半導体装置のメモリチップにおける再配線部の構造の一例を拡大して示す拡大断面図である。また、図6は図1に示す半導体装置のチップ固有信号のパッドにおける引き出し配線による上段と下段のメモリチップの接続状態の一例を示す斜視図、図7は図1に示す半導体装置のチップ共通信号のパッドにおける引き出し配線による上段と下段のメモリチップの接続状態の一例を示す斜視図である。さらに、図8は図1に示す半導体装置に搭載されるメモリチップの引き出し配線の引き回しの一例及びマイコンチップとのワイヤリングの一例を示す配線図で、図9は図1に示す半導体装置に搭載されるマイコンチップとメモリチップのパッド配列の位置関係の一例を示す平面図と拡大平面図である。
とワイヤ4を介して接続される再配置パッド2eから、下段側のメモリチップ(第1メモリチップ1)の下辺(長辺)に沿って配置されたパッド(上段の第2メモリチップ2で覆われている元パッド)1gまでの距離は、マイコンチップ3の電極(内部インタフェース用電極)3g(3c)とワイヤ4を介して接続される再配置パッド2eから、上段側のメモリチップ(第2メモリチップ2)の下辺(長辺)に沿って配置されたパッド2gまでの距離よりも遠い。これは、第2メモリチップ2のパッドと第1メモリチップ1のパッドとをワイヤ4を介して繋いでいることが1つの原因である。そのため、上段側のメモリチップ(第2メモリチップ2)と下段側のメモリチップ(第1メモリチップ1)の夫々の元パッド2g,1gまでの配線長(配線経路の長さ)を等長化することが困難となり、マイコンチップ3の内部インタフェース用電極3g(3c)を介して入出力される信号(データ)にばらつきが生じる。2つのメモリチップ1,2に対して信号(データ)を同時に入出力する場合、システムが動作しない恐れがある。そこで、図38(a)に示すように、上段側のメモリチップ(第2メモリチップ2)の主面上に形成する配線パターン(再配線2fのレイアウト)を下段側のメモリチップ(第1メモリチップ1)の配線パターンと異なるように、形成することが好ましい。詳細に説明すると、上段側のメモリチップ(第2メモリチップ2)の主面上に形成する配線パターンが、下段側のメモリチップ(第1メモリチップ1)の配線パターンよりも長くなるように、蛇行させることが好ましい。
1a 主面
1b 裏面
1c 第1パッド
1d 第2パッド
1e 第3パッド
1f 再配線(引き出し配線)
1g 元パッド
1h 再配置パッド
1i 固有信号用パッド
2 第2メモリチップ
2a 主面
2b 裏面
2c 第1パッド
2d 第2パッド
2e 第3パッド
2f 再配線(引き出し配線)
2g 元パッド
2h 再配置パッド
2i 元パッド
2j 再配置パッド
2k マイコンチップ用パッド
2m(2i) 固有信号用パッド
2n(2f) 電源用再配線(電源用引き出し配線)
2p(2f) 信号用再配線(信号用引き出し配線)
2q クロック用パッド
2r クロック用再配線(クロック用引き出し配線)
2s(2n) マイコンチップ用電源配線
2t(2n) メモリチップ用電源配線
2u(2h,2j) マイコンチップ用端部パッド
2v GND線
3 マイコンチップ
3a 主面
3b 裏面
3c 端子
3d クロック用端子
3e 第1辺
3f 第2辺
3g メモリチップ用端子
3h 外部接続用端子
3i GND用端子
4 ワイヤ
5 接着材
6 封止体
6a 側部
7 リードフレーム
7a インナリード
7b アウタリード(外部端子)
7c タブ(チップ搭載部)
7d 吊りリード
8 SSOP(半導体装置)
9 シリコン基板
9a 絶縁膜
9b 元パッド
9c 第1保護膜
9d 第2保護膜
9e 第1絶縁膜
9f 第2絶縁膜
9g バリア層
9h 再配置パッド
10 配線基板
10a 主面
10b 裏面
10c 外部リード(外部端子)
10d ボンディングリード
10e ビア配線
10f Cu配線
10g コア材
10h ソルダレジスト
11 ケース
12 メモリカード(半導体装置)
13 同パターンメモリチップ
13a パッド(チップセレクトピン)
13b ワイドパッド(チップセレクトピン)
21 配線基板
22 メモリチップ
23 マイコンチップ
24 スペーサ
25 SOP(半導体装置)
Claims (18)
- 主面の対向する2辺それぞれに沿って複数のパッドが各々に形成され、かつ積層された複数のメモリチップと、
前記複数のメモリチップの最上段のメモリチップ上に搭載されたマイコンチップと、
前記マイコンチップと電気的に接続する複数の外部端子とを有し、
前記複数のメモリチップそれぞれは、前記主面の対向する2辺のうちの一方の辺に沿って前記主面上に形成された第1パッドと、前記第1パッドと電気的に接続する引き出し配線と、前記主面の対向する2辺のうちの他方の辺に沿って前記主面上に形成され、かつ前記引き出し配線と電気的に接続する第2パッドと、前記引き出し配線上において前記マイコンチップの端子とワイヤを介して電気的に接続される第3パッドを備えており、
前記積層された複数のメモリチップのうち、上段の前記メモリチップの第2パッドと前記上段のメモリチップから迫り出して露出した下段の前記メモリチップの第2パッドとがワイヤによって電気的に接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記マイコンチップは、前記最上段のメモリチップの主面の中央部に搭載されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記メモリチップは、前記マイコンチップと外部機器とを電気的に接続する複数のマイコンチップ用パッドを有しており、前記複数のマイコンチップ用パッドは、前記メモリチップの主面の前記第1及び第2パッドが配置された辺とは異なった辺に沿って配置されていることを特徴とする半導体装置。
- 請求項3記載の半導体装置において、前記マイコンチップ用パッドは、前記引き出し配線によって前記メモリチップの端部近傍まで引き出されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数のメモリチップそれぞれの固有信号用パッドは、平面的に同じ位置に配置され、下段の前記メモリチップの固有信号用パッドから前記引き出し配線によって引き出された前記第2パッドは、上段の前記メモリチップの固有信号用パッドから前記引き出し配線によって引き出された前記第2パッドとずれた位置のパッドに電気的に接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記引き出し配線のうち、電源用及びGND用引き出し配線は、信号用引き出し配線より太く形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記メモリチップは、前記マイコンチップにクロック信号を供給するための第1クロック用パッドと、一端部が前記第1クロック用パッドと繋がるクロック用引き出し配線と、前記クロック用引き出し配線の前記一端部とは反対側の他端部と繋がる第2クロック用パッドと、前記第1クロック用パッドと隣接する第1GND用パッドと、前記第2クロック用パッドと隣接する第2GND用パッドと、前記第1GND用パッドと前記第2GND用パッドとを繋ぎ、前記第1クロック用パッド、前記第2クロック用パッド及び前記クロック用引き出し配線を囲むように形成されたGND用引き出し配線とを有することを特徴とする半導体装置。
- 請求項7記載の半導体装置において、前記メモリチップの前記第1及び第2クロック用パッドと電気的に接続する前記マイコンチップのクロック用端子は、前記マイコンチップの主面の一辺の中央部に配置されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記メモリチップの主面上の前記引き出し配線は、マイコンチップ用電源配線とメモリチップ用電源配線とで別々に形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記マイコンチップは、平面形状が四角形から成り、互いに対向する一対の第1辺には、外部機器と信号のやり取りを行うための外部接続用端子が前記第1辺に沿って設けられ、前記第1辺と交差する第2辺には、前記メモリチップと信号のやり取りを行うメモリチップ用端子が前記第2辺に沿って設けられていることを特徴とする半導体装置。
- 請求項10記載の半導体装置において、前記メモリチップ用端子のうち、下段の前記メモリチップと電気的に接続する端子は、1つの辺における端部側に配置され、上段の前記メモリチップと電気的に接続する端子は、1つの辺における中央部に配置されていることを特徴とする半導体装置。
- 請求項10記載の半導体装置において、前記メモリチップ用端子は、相互に対向する2つの前記第2辺それぞれに沿って設けられ、この2つの前記第2辺に分散して配置した前記メモリチップ用端子がそれぞれ前記引き出し配線上の前記第3パッドとワイヤを介して電気的に接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数のメモリチップと前記マイコンチップが積層されて搭載されたチップ搭載部と、前記チップ搭載部の周囲に配置された複数のインナリードと、最上段の前記メモリチップのパッドと前記インナリードとを電気的に接続する複数のワイヤと、前記複数のメモリチップ、前記マイコンチップ及び前記複数のワイヤを樹脂封止する封止体と、前記インナリードと一体で繋がり、かつ前記封止体の対向する2つの側部から露出する複数のアウタリードとを有することを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数のメモリチップと前記マイコンチップが積層されて搭載され、かつ裏面に前記複数の外部端子が形成された配線基板と、最上段の前記メモリチップのパッドと前記配線基板のボンディングリードとを電気的に接続する複数のワイヤと、前記複数のメモリチップ、前記マイコンチップ、前記配線基板及び前記複数のワイヤを収容するケースとを有し、前記ケースがカード型に形成されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記マイコンチップは、平面形状が四角形から成り、外部機器とのやり取りを行うための外部接続用端子及び前記メモリチップとのやり取りを行うメモリチップ用端子は1つの辺に沿って配置され、下段の前記メモリチップと電気的に接続する端子と上段の前記メモリチップと電気的に接続する端子は、並んで設けられていることを特徴とする半導体装置。
- チップ搭載部、及び前記チップ搭載部の周囲に設けられた複数の端子を有する基板と、
平面形状が四角形から成り、複数のパッドが形成された主面を有し、前記基板の前記チップ搭載部上に搭載されたメモリチップと、
平面形状が四角形から成り、複数の電極が形成された主面を有し、前記メモリチップの主面上に搭載されたマイコンチップと、
前記マイコンチップの前記複数の電極と前記メモリチップの前記複数のパッドとをそれぞれ電気的に接続する複数の第1ワイヤと、
前記メモリチップの前記複数のパッドと前記基板の前記複数の端子とをそれぞれ電気的に接続する複数の第2ワイヤと、
を含み、
前記マイコンチップは、前記マイコンチップの一辺が前記メモリチップの一辺と並ぶように、前記メモリチップ上に搭載され、
前記メモリチップの前記複数のパッドは、前記メモリチップの前記一辺に沿って配置された複数の第1パッドと、前記複数の第1パッドよりも前記マイコンチップに近い位置に配置された複数の第2パッドと、前記複数の第1パッドと前記複数の第2パッドとをそれぞれ繋ぐ複数の配線とを有し、
前記マイコンチップの前記複数の電極は、前記メモリチップと前記マイコンチップにより構成されるシステムの内部に対してデータの入出力を行うための複数の内部インタフェース用電極を有し、
前記複数の第1ワイヤは、前記マイコンチップと前記メモリチップを電気的に接続するための複数の内部インタフェース用ワイヤを有し、
前記マイコンチップの前記複数の内部インタフェース用電極と前記複数の第2パッドは、前記複数の内部インタフェース用ワイヤを介してそれぞれ電気的に接続されていることを特徴とする半導体装置。 - 請求項16記載の半導体装置において、前記メモリチップの前記複数のパッドは、前記メモリチップの前記一辺と交差する辺に沿って配置された複数の第3パッドと、前記複数の第3パッドよりも前記マイコンチップに近い位置に配置された複数の第4パッドと、前記複数の第3パッドと前記複数の第4パッドとをそれぞれ繋ぐ複数の配線とを有し、
前記マイコンチップの前記複数の電極は、前記システムの外部に対してデータの入出力を行うために、前記マイコンチップの前記一辺と交差する辺に沿って配置された複数の外部インタフェース用電極を有し、
前記複数の第1ワイヤは、前記マイコンチップと前記システムの外部を電気的に接続するための複数の外部インタフェース用ワイヤを有し、
前記マイコンチップの前記複数の外部インタフェース用電極と前記複数の第4パッドは、前記複数の外部インタフェース用ワイヤを介してそれぞれ電気的に接続され、
前記メモリチップの前記複数の第3パッドと前記基板の前記複数の端子は、前記複数の第2ワイヤを介してそれぞれ電気的に接続されていることを特徴とする半導体装置。 - 請求項16記載の半導体装置において、前記マイコンチップの前記内部インタフェース用電極とこの内部インタフェース用電極に対応する前記第2パッドとを電気的に接続する内部インタフェース用ワイヤの長さは、この第2パッドとこの第2パッドに対応する前記第1パッドとを繋ぐ引き出し配線の長さよりも短いことを特徴とする半導体装置。
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JP5183186B2 (ja) * | 2007-12-14 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JP5581627B2 (ja) * | 2009-08-05 | 2014-09-03 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
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JP5618873B2 (ja) | 2011-03-15 | 2014-11-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6122290B2 (ja) | 2011-12-22 | 2017-04-26 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 再配線層を有する半導体パッケージ |
JP2014220439A (ja) * | 2013-05-10 | 2014-11-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
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