JP2009033151A - Ｓｏｉ基板の製造方法及び半導体装置の作製方法 - Google Patents

Ｓｏｉ基板の製造方法及び半導体装置の作製方法 Download PDF

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Publication number
JP2009033151A
JP2009033151A JP2008174221A JP2008174221A JP2009033151A JP 2009033151 A JP2009033151 A JP 2009033151A JP 2008174221 A JP2008174221 A JP 2008174221A JP 2008174221 A JP2008174221 A JP 2008174221A JP 2009033151 A JP2009033151 A JP 2009033151A
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layer
substrate
light
single crystal
semiconductor
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JP2009033151A5 (enExample
Inventor
Akihisa Shimomura
明久 下村
Hideto Onuma
英人 大沼
Tetsuya Kakehata
哲弥 掛端
Kenichiro Makino
賢一郎 牧野
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008174221A priority Critical patent/JP2009033151A/ja
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Publication of JP2009033151A5 publication Critical patent/JP2009033151A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
JP2008174221A 2007-07-04 2008-07-03 Ｓｏｉ基板の製造方法及び半導体装置の作製方法 Withdrawn JP2009033151A (ja)

Priority Applications (1)

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JP2008174221A JP2009033151A (ja) 2007-07-04 2008-07-03 Ｓｏｉ基板の製造方法及び半導体装置の作製方法

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JP2007175757 2007-07-04
JP2008174221A JP2009033151A (ja) 2007-07-04 2008-07-03 Ｓｏｉ基板の製造方法及び半導体装置の作製方法

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JP2009033151A true JP2009033151A (ja) 2009-02-12
JP2009033151A5 JP2009033151A5 (enExample) 2011-08-04

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US (1) US7678668B2 (enExample)
JP (1) JP2009033151A (enExample)
KR (1) KR101481974B1 (enExample)
CN (1) CN101339899B (enExample)
TW (1) TWI438864B (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015129830A (ja) * 2014-01-07 2015-07-16 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
US11071224B2 (en) 2014-10-28 2021-07-20 Semiconductor Energy Laboratory Co., Ltd. Functional panel, method for manufacturing the same, module, data processing device
CN117066978A (zh) * 2023-10-16 2023-11-17 天通控股股份有限公司 一种钽酸锂键合晶片的减薄方法

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8163628B2 (en) * 2007-11-01 2012-04-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US20100270658A1 (en) * 2007-12-27 2010-10-28 Kazuo Nakagawa Semiconductor device and method for producing same
US7951656B2 (en) * 2008-06-06 2011-05-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8815657B2 (en) * 2008-09-05 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US20100081251A1 (en) * 2008-09-29 2010-04-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP5420968B2 (ja) 2009-05-07 2014-02-19 信越化学工業株式会社 貼り合わせウェーハの製造方法
JP2011119233A (ja) * 2009-11-04 2011-06-16 Canon Inc 有機ｅｌ素子とそれを用いた表示装置
WO2011062042A1 (en) 2009-11-20 2011-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101055473B1 (ko) * 2009-12-15 2011-08-08 삼성전기주식회사 기판 제조용 캐리어 부재 및 이를 이용한 기판의 제조방법
KR101366000B1 (ko) * 2010-03-08 2014-02-21 가부시키가이샤 히다치 고쿠사이 덴키 반도체 장치의 제조 방법 및 기판 처리 장치
CN102822978B (zh) * 2010-03-12 2015-07-22 株式会社半导体能源研究所 半导体装置及其制造方法
CN102760697B (zh) 2011-04-27 2016-08-03 株式会社半导体能源研究所 半导体装置的制造方法
JP6005401B2 (ja) * 2011-06-10 2016-10-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5878330B2 (ja) * 2011-10-18 2016-03-08 株式会社ディスコ レーザー光線の出力設定方法およびレーザー加工装置
KR20140091203A (ko) * 2013-01-10 2014-07-21 삼성전자주식회사 반도체의 잔류 응력 제거장치 및 잔류 응력 제거방법
KR101583007B1 (ko) * 2013-12-18 2016-01-07 주식회사 디에이케이코리아 합성수지의 금속 패턴 형성 방법
JP6454606B2 (ja) * 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396854B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396852B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
CN105261586B (zh) * 2015-08-25 2018-05-25 上海新傲科技股份有限公司 带有电荷陷阱和绝缘埋层衬底的制备方法
CN107132616A (zh) * 2017-05-22 2017-09-05 浙江大学 一种基于复合波导的横向电场通过的偏振器
US11232976B2 (en) 2017-07-20 2022-01-25 National Research Council Of Canada Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device
CN110166913A (zh) * 2018-02-14 2019-08-23 复旦大学附属眼耳鼻喉科医院 生物相容性传声器及其制备方法
KR102049806B1 (ko) * 2018-04-25 2020-01-22 한국과학기술연구원 특정 파장의 광원 및 반응성 가스를 이용하여 대상물의 표면을 평탄화하는 방법 및 장치
CN109001179B (zh) * 2018-08-07 2020-10-27 东南大学 尖端间距可调节的金属V型光栅Fano共振结构
US11167375B2 (en) 2018-08-10 2021-11-09 The Research Foundation For The State University Of New York Additive manufacturing processes and additively manufactured products
WO2020180940A1 (en) * 2019-03-04 2020-09-10 Board Of Regents, The University Of Texas System Silicon-on-oxide-on-silicon
CN118738077A (zh) * 2019-05-23 2024-10-01 维耶尔公司 集成功能调谐材料与微型装置的方法及其结构
CN110854117A (zh) * 2019-11-26 2020-02-28 中国科学院微电子研究所 一种三维静态随机存取存储器及其制备方法
CN111181518A (zh) * 2019-12-28 2020-05-19 珠海市东恒电子有限公司 一种平衡非平衡射频转换元器件制程方法
CN113540339B (zh) * 2020-04-21 2024-07-12 济南晶正电子科技有限公司 一种制备压电复合薄膜的方法及压电复合薄膜
CN111508891B (zh) * 2020-04-28 2024-03-12 上海华力集成电路制造有限公司 Soi晶圆片的制作方法
CN113745391B (zh) * 2021-08-26 2022-10-14 厦门天马微电子有限公司 一种显示面板和显示装置
KR20250083279A (ko) 2023-11-30 2025-06-10 삼성디스플레이 주식회사 표시 장치의 제조 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH11233449A (ja) * 1998-02-13 1999-08-27 Denso Corp 半導体基板の製造方法
JP2004273698A (ja) * 2003-03-07 2004-09-30 Casio Comput Co Ltd 半導体薄膜の製造方法
JP2005203596A (ja) * 2004-01-16 2005-07-28 Seiko Epson Corp 電気光学装置の製造方法、電気光学装置および電子機器
JP2006332634A (ja) * 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567967A (en) * 1993-06-28 1996-10-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a crystallized island semiconductor layer
US5767799A (en) * 1995-12-05 1998-06-16 Mitsubishi Semiconductor America, Inc. Low power high speed MPEG video variable length decoder
JPH1197379A (ja) 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
US6534380B1 (en) 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4323724B2 (ja) * 1999-03-05 2009-09-02 セイコーエプソン株式会社 半導体装置の製造方法
JP4379943B2 (ja) 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
FR2817395B1 (fr) 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6767799B2 (en) 2001-12-28 2004-07-27 Semiconductor Energy Laboratory Co., Ltd. Laser beam irradiation method
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
CN101281912B (zh) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
EP2009687B1 (en) 2007-06-29 2016-08-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an SOI substrate and method of manufacturing a semiconductor device
US20090004764A1 (en) 2007-06-29 2009-01-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH11233449A (ja) * 1998-02-13 1999-08-27 Denso Corp 半導体基板の製造方法
JP2004273698A (ja) * 2003-03-07 2004-09-30 Casio Comput Co Ltd 半導体薄膜の製造方法
JP2005203596A (ja) * 2004-01-16 2005-07-28 Seiko Epson Corp 電気光学装置の製造方法、電気光学装置および電子機器
JP2006332634A (ja) * 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015129830A (ja) * 2014-01-07 2015-07-16 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
US11071224B2 (en) 2014-10-28 2021-07-20 Semiconductor Energy Laboratory Co., Ltd. Functional panel, method for manufacturing the same, module, data processing device
JP2021106157A (ja) * 2014-10-28 2021-07-26 株式会社半導体エネルギー研究所 表示装置の作製方法
JP2021108283A (ja) * 2014-10-28 2021-07-29 株式会社半導体エネルギー研究所 表示装置
JP2022024036A (ja) * 2014-10-28 2022-02-08 株式会社半導体エネルギー研究所 表示装置
JP7052161B1 (ja) 2014-10-28 2022-04-11 株式会社半導体エネルギー研究所 表示装置
JP2022060285A (ja) * 2014-10-28 2022-04-14 株式会社半導体エネルギー研究所 機能パネル
JP2022062027A (ja) * 2014-10-28 2022-04-19 株式会社半導体エネルギー研究所 表示装置
JP7178519B2 (ja) 2014-10-28 2022-11-25 株式会社半導体エネルギー研究所 機能パネル
US11818856B2 (en) 2014-10-28 2023-11-14 Semiconductor Energy Laboratory Co., Ltd. Functional panel, method for manufacturing the same, module, data processing device
CN117066978A (zh) * 2023-10-16 2023-11-17 天通控股股份有限公司 一种钽酸锂键合晶片的减薄方法
CN117066978B (zh) * 2023-10-16 2024-01-05 天通控股股份有限公司 一种钽酸锂键合晶片的减薄方法

Also Published As

Publication number Publication date
TWI438864B (zh) 2014-05-21
TW200908214A (en) 2009-02-16
US20090011575A1 (en) 2009-01-08
KR20090004704A (ko) 2009-01-12
CN101339899A (zh) 2009-01-07
CN101339899B (zh) 2012-02-08
KR101481974B1 (ko) 2015-01-14
US7678668B2 (en) 2010-03-16

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