JP2009031784A - 表示装置およびその作製方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Abstract
【解決手段】半導体基板を正六角形またはこれに準じる形に形成し、大面積基板に半導体基板を接合、分離する。さらに、接合された半導体の境界が、フォトリソグラフィ等によるパターニングの際に、エッチングによって除去される領域に位置するようなレイアウトとする。
【選択図】図1
Description
まず、円形のシリコンウエハを多角形に切り出してSOI層(半導体層)形成に使用する具体的方法について説明する。切り出す多角形としては、代表的には正六角形を用いることができる。正六角形またはこれに準じた形とすることで、SOI層を平面的に敷き詰めることが可能となる。特に、切り出す多角形を正六角形とした場合は、除去される部分を小さくすることが可能となるため、好ましい(図1(A)および(B)参照)。
本実施の形態においては、実施の形態1で示した例のように、当該半導体装置が有する半導体領域が、SOI層を貼り合わせて敷き詰めたものによって形成されたものにおける、半導体領域の効果的な配置について説明する。
本発明に係るSOI基板を図6(A)(B)に示す。図6(A)においてベース基板9200は絶縁表面を有する基板若しくは絶縁基板であり、アルミノシリケートガラス、アルミノホウケイ酸ガラス、バリウムホウケイ酸ガラスのような電子工業用に使われる各種ガラス基板が適用される。その他に石英ガラス、シリコンウエハーのような半導体基板も適用可能である。SOI層9202は単結晶半導体であり、代表的には単結晶シリコンが適用される。その他に、水素イオン注入剥離法のようにして単結晶半導体基板若しくは多結晶半導体基板から剥離可能であるシリコン、ゲルマニウム、その他、ガリウムヒ素、インジウムリンなどの化合物半導体による結晶性半導体層を適用することもできる。
本実施の形態はSOI基板の製造方法について図13と図14を参照して説明する。図13(A)は、自然酸化膜が除去された単結晶シリコン基板9401にSiH4ガスとN2Oガスを用い、プラズマCVD法で100nmの厚さで酸化窒化シリコン膜9405を形成する。さらにSiH4ガス、N2Oガス及びNH3ガスを用い、50nmの厚さで窒化酸化シリコン膜9406を成膜する。
本実施の形態においては、表示装置の構成について説明する。
本実施の形態においては、液晶表示装置に適用できる画素の構成及び画素の動作について説明する。
本実施の形態においては、表示装置の画素の構成及び画素の動作について説明する。
本実施の形態においては、電子機器の例について説明する。
11 領域
12 ガラス基板
13 SOI層
14 表示部
15 回路
16 回路
17 回路
5600 画素
5601 トランジスタ
5602 液晶素子
5603 容量素子
5604 配線
5605 配線
5606 配線
5607 対向電極
5610 画素
5611 トランジスタ
5612 液晶素子
5613 容量素子
5614 配線
5615 配線
5616 配線
5620 画素
5621 トランジスタ
5622 液晶素子
5623 容量素子
5624 配線
5625 配線
5627 対向電極
5630 画素
5631 トランジスタ
5632 液晶素子
5633 容量素子
5635 配線
5637 対向電極
5640 サブ画素
5641 トランジスタ
5642 液晶素子
5643 容量素子
5644 配線
5645 配線
5646 配線
5647 対向電極
5650 サブ画素
5651 トランジスタ
5652 液晶素子
5653 容量素子
5655 配線
5657 対向電極
5659 画素
6400 画素
6401 スイッチング用トランジスタ
6402 駆動用トランジスタ
6403 容量素子
6404 発光素子
6405 信号線
6406 走査線
6407 電源線
6408 共通電極
6410 駆動用トランジスタ
6411 スイッチ
6412 スイッチ
6413 スイッチ
6414 容量素子
6415 容量素子
6416 発光素子
6417 共通電極
6421 信号線
6422 電源線
6423 走査線
6424 走査線
6425 走査線
6430 駆動用トランジスタ
6431 スイッチ
6432 スイッチ
6433 スイッチ
6434 容量素子
6435 発光素子
6436 共通電極
6441 信号線
6442 電源線
6443 走査線
6444 走査線
6445 走査線
8200 基板
8201 画素部
8202 画素
8203 走査線側入力端子
8204 信号線側入力端子
8205 走査線駆動回路
8206 信号線駆動回路
8210 FPC
8211 ICチップ
9031 本体
9032 表示部
9033 イヤホン
9034 支持部
9035 接続端子
9036 センサ
9037 マイクロフォン
9038 スピーカ
9601 表示パネル
9602 画素部
9603 走査線駆動回路
9604 信号線駆動回路
9605 回路基板
9606 コントロール回路
9607 信号分割回路
9608 接続配線
9611 チューナ
9612 映像信号増幅回路
9613 映像信号処理回路
9614 信号線駆動回路
9615 音声信号増幅回路
9616 音声信号処理回路
9617 スピーカ
9618 制御回路
9619 入力部
9621 表示パネル
9622 コントロール回路
9623 信号分割回路
9624 走査線駆動回路
9631 筐体
9632 表示画面
9633 スピーカ
9634 操作キー
9635 接続端子
9636 センサ
9637 マイクロフォン
9640 充電器
9642 筐体
9643 表示部
9646 操作キー
9647 スピーカ部
9648 接続端子
9649 センサ
9641 マクロフォン
9662 表示パネル
9663 FPC
9650 ハウジング
9651 プリント基板
9652 スピーカ
9653 マイクロフォン
9654 送受信回路
9655 信号処理回路
9656 接続端子
9657 バッテリー9659 筐体
9660 アンテナ
9661 センサ
9671 筐体
9672 支持台
9673 表示部
9674 接続端子
9675 センサ
9676 マイクロフォン
9677 スピーカ
9678 操作キー
9679 LEDランプ
9691 本体
9692 表示部
9693 受像部
9694 操作キー
9695 外部接続ポート
9696 シャッターボタン
9697 接続端子
9698 センサ
9699 マイクロフォン
9700 スピーカ
9701 LEDランプ
9721 本体
9722 筐体
9723 表示部
9724 キーボード
9725 外部接続ポート
9726 ポインティングデバイス
9727 接続端子
9728 センサ
9729 マイクロフォン
9730 スピーカ
9731 LEDランプ
9732 リーダ/ライタ
9730 筐体
9731 表示部
9732 リモコン装置
9733 スピーカ部
9741 表示パネル
9742 ユニットバス
9751 柱状体
9752 表示パネル
9761 車体
9762 表示パネル
9771 ドア
9772 表示パネル
9773 ガラス窓
9774 天井
9781 天井
9782 表示パネル
9783 ヒンジ部
9791 本体
9792 表示部
9793 スイッチ
9794 操作キー
9795 赤外線ポート
9796 接続端子
9797 センサ
9798 マイクロフォン
9799 スピーカ
9800 LEDランプ
9811 本体
9812 筐体
9813 表示部A
9814 表示部B
9815 部
9816 操作キー
9817 スピーカ部
9818 接続端子
9819 センサ
9820 マイクロフォン
9821 LEDランプ
9851 筐体
9852 表示部
9853 スピーカ部
9854 操作キー
9855 記憶媒体挿入部
9856 接続端子
9857 センサ
9858 マイクロフォン
9859 LEDランプ
9861 本体
9862 表示部
9863 操作キー
9864 スピーカ
9865 シャッターボタン
9866 受像部
9867 アンテナ
9868 接続端子
9869 センサ
9870 マイクロフォン
9871 LEDランプ
9881 筐体
9882 表示部
9883 表示部
9884 スピーカ部
9885 操作キー
9886 記録媒体挿入部
9887 接続端子
9888 センサ
9889 マイクロフォン
9890 LEDランプ
Claims (12)
- 表示部を有する表示装置であり、
前記表示部は、複数の画素を有し、
前記複数の画素は、同一の信号線を有するm列の画素群(mは正の整数)に分類され、
前記画素群が有する画素は、それぞれの領域内において概同一の位置に半導体領域を有し、
前記画素群は、隣接する画素群と、走査線と平行な方向の画素ピッチXの距離を置いて配置され、
前記画素群が有する画素の領域内における前記半導体領域の位置と、前記画素群と隣接する画素群が有する画素の領域内における前記半導体領域の位置の違いがX/2であり、
前記半導体領域は、それぞれの領域内において単結晶またはそれに準じる結晶性を有する
ことを特徴とする表示装置。 - 請求項1において、前記複数の画素は、その領域の短辺対長辺比がそれぞれ1:√3であることを特徴とする表示装置。
- 請求項1または請求項2において、前記表示部における前記半導体領域は、信号線と平行な方向と概30°の角度を持って並置されていることを特徴とする表示装置。
- 表示部を有する表示装置であり、
前記表示部は、複数の画素を有し、
前記複数の画素は、同一の走査線を有するn行の画素群(nは正の整数)に分類され、
前記画素群が有する画素は、それぞれの領域内において概同一の位置に半導体領域を有し、
前記画素群は、隣接する画素群と、信号線と平行な方向の画素ピッチYの距離を置いて配置され、
前記画素群が有する画素の領域内における前記半導体領域の位置と、前記画素群と隣接する画素群が有する画素の領域内における前記半導体領域の位置の違いがY/2であり、
前記半導体領域は、それぞれの領域内において単結晶またはそれに準じる結晶性を有することを特徴とする表示装置。 - 請求項4において、前記複数の画素は、その領域の短辺対長辺比がそれぞれ√3/2:1であることを特徴とする表示装置。
- 請求項4または請求項5において、前記表示部における前記半導体領域は、信号線と平行な方向と概30°の角度を持って並置されていることを特徴とする表示装置。
- 請求項4または請求項5において、前記表示部における前記半導体領域は、信号線と平行な方向と概60°の角度を持って並置されていることを特徴とする表示装置。
- 複数の半導体領域を有する表示装置であり、
前記複数の半導体領域は、それぞれ、単結晶または単結晶に準じる結晶性を有し、
前記複数の半導体領域は、それぞれ同じ結晶方位を有する半導体領域の複数の集合に区分され、
複数の集合の境界線は、複数の正六角形を並置した態様を呈することを特徴とする表示装置。 - 請求項1乃至8のいずれか一において、さらに
前記表示装置は画素電極と絶縁膜を有し、
前記画素電極は前記絶縁膜に接して設けられ、
前記絶縁膜は、有機物を有する平坦膜であることを特徴とする表示装置。 - ウェハを切り出して六角形の半導体基板を形成し、
矩形の基板に形成する表示部の個数に区分する仮想区分線を設定し、
この設定された仮想区分線に対して、半導体基板の六角形の一辺が平行となり、且つ、該半導体基板の六角形の一辺が最も近い他の六角形の一辺と平行となるように、六角形の半導体基板を矩形の基板に対して複数枚並べて貼り合わせる表示装置の作製方法であり、
前記仮想区分線は、表示部の外形線である表示装置の作製方法。 - ウェハを切り出して六角形の半導体基板を形成し、
矩形の基板上に前記六角形の半導体基板を複数枚並べて貼り合わせ、
複数の半導体領域を形成し、
前記半導体領域と電気的に接続する画素電極を形成して少なくとも一つの半導体領域と1つの画素電極を含む画素を複数配置した表示部を形成する表示装置の作製方法であり、
前記複数の半導体領域の形成は、六角形の半導体基板を矩形の基板に対して複数枚貼り合わせ、隣り合う六角形の基板の境界領域が、ある一つの半導体領域とその隣の半導体領域との間に配置されるように複数の半導体領域を形成する表示装置の作製方法。 - 請求項11において、前記表示部における画素の配置はデルタ配置である表示装置の作製方法。
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