JP2008535245A5 - - Google Patents

Download PDF

Info

Publication number
JP2008535245A5
JP2008535245A5 JP2008504047A JP2008504047A JP2008535245A5 JP 2008535245 A5 JP2008535245 A5 JP 2008535245A5 JP 2008504047 A JP2008504047 A JP 2008504047A JP 2008504047 A JP2008504047 A JP 2008504047A JP 2008535245 A5 JP2008535245 A5 JP 2008535245A5
Authority
JP
Japan
Prior art keywords
region
forming
channel region
insulator
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008504047A
Other languages
English (en)
Japanese (ja)
Other versions
JP5372493B2 (ja
JP2008535245A (ja
Filing date
Publication date
Priority claimed from US11/093,801 external-priority patent/US7282402B2/en
Application filed filed Critical
Publication of JP2008535245A publication Critical patent/JP2008535245A/ja
Publication of JP2008535245A5 publication Critical patent/JP2008535245A5/ja
Application granted granted Critical
Publication of JP5372493B2 publication Critical patent/JP5372493B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2008504047A 2005-03-30 2006-02-16 デュアル歪みチャネル半導体デバイスを製造する方法 Expired - Fee Related JP5372493B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/093,801 2005-03-30
US11/093,801 US7282402B2 (en) 2005-03-30 2005-03-30 Method of making a dual strained channel semiconductor device
PCT/US2006/005471 WO2006107419A2 (en) 2005-03-30 2006-02-16 Method of making a dual strained channel semiconductor device

Publications (3)

Publication Number Publication Date
JP2008535245A JP2008535245A (ja) 2008-08-28
JP2008535245A5 true JP2008535245A5 (https=) 2009-04-09
JP5372493B2 JP5372493B2 (ja) 2013-12-18

Family

ID=37073906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008504047A Expired - Fee Related JP5372493B2 (ja) 2005-03-30 2006-02-16 デュアル歪みチャネル半導体デバイスを製造する方法

Country Status (4)

Country Link
US (1) US7282402B2 (https=)
JP (1) JP5372493B2 (https=)
TW (1) TWI389258B (https=)
WO (1) WO2006107419A2 (https=)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791107B2 (en) * 2004-06-16 2010-09-07 Massachusetts Institute Of Technology Strained tri-channel layer for semiconductor-based electronic devices
US7276417B2 (en) * 2005-12-28 2007-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid STI stressor with selective re-oxidation anneal
US7504696B2 (en) * 2006-01-10 2009-03-17 International Business Machines Corporation CMOS with dual metal gate
US7615418B2 (en) * 2006-04-28 2009-11-10 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7772060B2 (en) * 2006-06-21 2010-08-10 Texas Instruments Deutschland Gmbh Integrated SiGe NMOS and PMOS transistors
KR100809327B1 (ko) * 2006-08-10 2008-03-05 삼성전자주식회사 반도체 소자 및 그 제조방법
KR20090038653A (ko) * 2007-10-16 2009-04-21 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조방법
US20090191468A1 (en) * 2008-01-29 2009-07-30 International Business Machines Corporation Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features
US8211786B2 (en) * 2008-02-28 2012-07-03 International Business Machines Corporation CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication
US20090250760A1 (en) * 2008-04-02 2009-10-08 International Business Machines Corporation Methods of forming high-k/metal gates for nfets and pfets
US7524740B1 (en) * 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
US7975246B2 (en) * 2008-08-14 2011-07-05 International Business Machines Corporation MEEF reduction by elongation of square shapes
JP4875038B2 (ja) * 2008-09-24 2012-02-15 株式会社東芝 半導体装置およびその製造方法
DE102009010883B4 (de) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses
DE102009021480B4 (de) * 2009-05-15 2013-10-24 Globalfoundries Dresden Module One Llc & Co. Kg Reduzierte Siliziumdicke in n-Kanaltransistoren in SOI-CMOS Bauelementen
DE102009023237B4 (de) * 2009-05-29 2013-11-28 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zum Herstellen von Transistorelementen mit unterschiedlicher Verformung und Halbleiterbauelement
DE102009035418B4 (de) * 2009-07-31 2012-08-16 Globalfoundries Dresden Module One Llc & Co. Kg Herstellung einer Kanalhalbleiterlegierung durch Abscheiden einer Hartmaske für das selektive epitaktische Aufwachsen
US8278165B2 (en) * 2009-10-12 2012-10-02 GlobalFoundries, Inc. Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices
US8716752B2 (en) * 2009-12-14 2014-05-06 Stmicroelectronics, Inc. Structure and method for making a strained silicon transistor
CN101819996B (zh) * 2010-04-16 2011-10-26 清华大学 半导体结构
DE102010028459B4 (de) * 2010-04-30 2018-01-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Reduzierte STI-Topographie in Metallgatetransistoren mit großem ε durch Verwendung einer Maske nach Abscheidung einer Kanalhalbleiterlegierung
US8486776B2 (en) * 2010-09-21 2013-07-16 International Business Machines Corporation Strained devices, methods of manufacture and design structures
DE102010063296B4 (de) * 2010-12-16 2012-08-16 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Herstellungsverfahren mit reduzierter STI-Topograpie für Halbleiterbauelemente mit einer Kanalhalbleiterlegierung
DE102010064281B4 (de) * 2010-12-28 2017-03-23 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Herstellung einer Kanalhalbleiterlegierung durch Erzeugen eines Hartmaskenschichtstapels und Anwenden eines plasmaunterstützten Maskenstrukturierungsprozesses
US8730628B2 (en) * 2011-10-26 2014-05-20 United Microelectronics Corp. Electrostatic protection circuit capable of preventing latch-up effect
US8828851B2 (en) * 2012-02-01 2014-09-09 Stmicroeletronics, Inc. Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
US8883598B2 (en) * 2012-03-05 2014-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Thin capped channel layers of semiconductor devices and methods of forming the same
US20130285117A1 (en) * 2012-04-27 2013-10-31 International Business Machines Corporation CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
FR3002078B1 (fr) * 2013-02-11 2015-03-27 Commissariat Energie Atomique Procede de realisation d'une couche semi-conductrice presentant au moins deux epaisseurs differentes
JP6251604B2 (ja) * 2013-03-11 2017-12-20 ルネサスエレクトロニクス株式会社 フィンｆｅｔ構造を有する半導体装置及びその製造方法
US9059041B2 (en) 2013-07-02 2015-06-16 International Business Machines Corporation Dual channel hybrid semiconductor-on-insulator semiconductor devices
EP3087602A4 (en) * 2013-12-27 2017-08-09 Intel Corporation Bi-axial tensile strained ge channel for cmos
US9105662B1 (en) 2014-01-23 2015-08-11 International Business Machines Corporation Method and structure to enhance gate induced strain effect in multigate device
US9570360B2 (en) 2014-08-27 2017-02-14 International Business Machines Corporation Dual channel material for finFET for high performance CMOS
KR102277398B1 (ko) * 2014-09-17 2021-07-16 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9165945B1 (en) 2014-09-18 2015-10-20 Soitec Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures
US9219150B1 (en) 2014-09-18 2015-12-22 Soitec Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures
US9209301B1 (en) 2014-09-18 2015-12-08 Soitec Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers
US9406799B2 (en) * 2014-10-21 2016-08-02 Globalfoundries Inc. High mobility PMOS and NMOS devices having Si—Ge quantum wells
US9508588B2 (en) * 2014-10-29 2016-11-29 GlobalFoundries, Inc. Methods for fabricating integrated circuits with isolation regions having uniform step heights
KR102316160B1 (ko) * 2014-12-22 2021-10-26 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
US9418841B2 (en) * 2014-12-30 2016-08-16 International Business Machines Corporation Type III-V and type IV semiconductor device formation
US9543323B2 (en) 2015-01-13 2017-01-10 International Business Machines Corporation Strain release in PFET regions
US20160254145A1 (en) * 2015-02-27 2016-09-01 Globalfoundries Inc. Methods for fabricating semiconductor structure with condensed silicon germanium layer
US9553030B2 (en) * 2015-04-24 2017-01-24 Globalfoundries Inc. Method of manufacturing P-channel FET device with SiGe channel
KR20170036966A (ko) * 2015-09-24 2017-04-04 삼성전자주식회사 반도체 소자의 제조하는 방법
US10249529B2 (en) * 2015-12-15 2019-04-02 International Business Machines Corporation Channel silicon germanium formation method
US9601385B1 (en) 2016-01-27 2017-03-21 International Business Machines Corporation Method of making a dual strained channel semiconductor device
US9905649B2 (en) * 2016-02-08 2018-02-27 International Business Machines Corporation Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer
US10141229B2 (en) * 2016-09-29 2018-11-27 Globalfoundries Inc. Process for forming semiconductor layers of different thickness in FDSOI technologies
FR3067516B1 (fr) 2017-06-12 2020-07-10 Stmicroelectronics (Rousset) Sas Realisation de regions semiconductrices dans une puce electronique
FR3068507B1 (fr) * 2017-06-30 2020-07-10 Stmicroelectronics (Rousset) Sas Realisation de regions semiconductrices dans une puce electronique
US10680065B2 (en) 2018-08-01 2020-06-09 Globalfoundries Inc. Field-effect transistors with a grown silicon-germanium channel
CN118610268B (zh) * 2024-08-09 2024-11-22 杭州积海半导体有限公司 一种半导体结构及其制备方法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
EP0838858B1 (de) 1996-09-27 2002-05-15 Infineon Technologies AG Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
JPH10270685A (ja) * 1997-03-27 1998-10-09 Sony Corp 電界効果トランジスタとその製造方法、半導体装置とその製造方法、その半導体装置を含む論理回路および半導体基板
US5906951A (en) 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5943565A (en) 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US5846857A (en) 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US6124627A (en) 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
JP3884203B2 (ja) 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
US6369438B1 (en) 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
JP2001160594A (ja) * 1999-09-20 2001-06-12 Toshiba Corp 半導体装置
KR100392166B1 (ko) 2000-03-17 2003-07-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법 및 반도체 장치
US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
KR100784603B1 (ko) * 2000-11-22 2007-12-11 가부시키가이샤 히타치세이사쿠쇼 반도체 장치 및 그 제조 방법
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
JP2003086708A (ja) * 2000-12-08 2003-03-20 Hitachi Ltd 半導体装置及びその製造方法
JP2002280568A (ja) * 2000-12-28 2002-09-27 Toshiba Corp 半導体装置及びその製造方法
JP2003031495A (ja) 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
US6475870B1 (en) 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US6600170B1 (en) * 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6638802B1 (en) 2002-06-20 2003-10-28 Intel Corporation Forming strained source drain junction field effect transistors
US6900502B2 (en) * 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
US6936506B1 (en) * 2003-05-22 2005-08-30 Advanced Micro Devices, Inc. Strained-silicon devices with different silicon thicknesses
US6982433B2 (en) * 2003-06-12 2006-01-03 Intel Corporation Gate-induced strain for MOS performance improvement
JP2005019851A (ja) * 2003-06-27 2005-01-20 Sharp Corp 半導体装置及びその製造方法
JP4322255B2 (ja) * 2003-08-05 2009-08-26 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US7545001B2 (en) * 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
WO2005112129A1 (ja) * 2004-05-13 2005-11-24 Fujitsu Limited 半導体装置およびその製造方法、半導体基板の製造方法

Similar Documents

Publication Publication Date Title
JP2008535245A5 (https=)
US7488659B2 (en) Structure and methods for stress concentrating spacer
JP5039902B2 (ja) デュアル・ストレス（二重応力）ｓｏｉ基板の製造方法および半導体デバイス
US7608489B2 (en) High performance stress-enhance MOSFET and method of manufacture
US7494902B2 (en) Method of fabricating a strained multi-gate transistor
US7560328B2 (en) Strained Si on multiple materials for bulk or SOI substrates
JP2008504677A5 (https=)
CN101256949B (zh) 应变soi衬底的制造方法和在其上制造cmos器件的方法
JP2007535802A5 (https=)
JP2005531144A5 (https=)
TW200601420A (en) Method of forming strained Si/SiGe on insulator with silicon germanium buffer
CN103077969B (zh) 一种mos器件及其制造方法
TW200735345A (en) Direct channel stress
WO2008150557A1 (en) Channel strain engineering in field-effect-transistor
CN101064285A (zh) 高性能应力增强mosfet及制造方法
US8686506B2 (en) High performance devices and high density devices on single chip
US7741168B2 (en) Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks
TW200539425A (en) Integrated circuit with strained and non-strained transistors, and method of forming thereof
CN101326631B (zh) 互补金属氧化物半导体
CN105870061B (zh) 用于绝缘体上应变硅晶片上双重隔离的方法和装置
US7951662B2 (en) Method of fabricating strained silicon transistor
JP2008510320A5 (https=)
CN101969047B (zh) 用于制备应变沟道cmos的等效应变记忆方法
JP2005216985A (ja) 半導体装置
JP2009164222A (ja) 半導体装置の製造方法