JP2008533700A - ネストされた集積回路パッケージオンパッケージシステム - Google Patents

ネストされた集積回路パッケージオンパッケージシステム Download PDF

Info

Publication number
JP2008533700A
JP2008533700A JP2007554259A JP2007554259A JP2008533700A JP 2008533700 A JP2008533700 A JP 2008533700A JP 2007554259 A JP2007554259 A JP 2007554259A JP 2007554259 A JP2007554259 A JP 2007554259A JP 2008533700 A JP2008533700 A JP 2008533700A
Authority
JP
Japan
Prior art keywords
substrate
package
integrated circuit
layer
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007554259A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008533700A5 (enExample
Inventor
キム，ヒョン・ウク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Stats Chippac Inc
Original Assignee
Stats Chippac Pte Ltd
Stats Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd, Stats Chippac Inc filed Critical Stats Chippac Pte Ltd
Publication of JP2008533700A publication Critical patent/JP2008533700A/ja
Publication of JP2008533700A5 publication Critical patent/JP2008533700A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1088—Arrangements to limit the height of the assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
JP2007554259A 2005-02-04 2006-02-04 ネストされた集積回路パッケージオンパッケージシステム Pending JP2008533700A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US65027905P 2005-02-04 2005-02-04
US11/257,894 US7279786B2 (en) 2005-02-04 2005-10-24 Nested integrated circuit package on package system
PCT/US2006/003927 WO2006084177A2 (en) 2005-02-04 2006-02-04 Nested integrated circuit package on package system

Publications (2)

Publication Number Publication Date
JP2008533700A true JP2008533700A (ja) 2008-08-21
JP2008533700A5 JP2008533700A5 (enExample) 2009-03-26

Family

ID=36777986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007554259A Pending JP2008533700A (ja) 2005-02-04 2006-02-04 ネストされた集積回路パッケージオンパッケージシステム

Country Status (4)

Country Link
US (2) US7279786B2 (enExample)
JP (1) JP2008533700A (enExample)
KR (1) KR101099773B1 (enExample)
WO (1) WO2006084177A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710642B2 (en) 2011-03-25 2014-04-29 Fujitsu Semiconductor Limited Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7445962B2 (en) * 2005-02-10 2008-11-04 Stats Chippac Ltd. Stacked integrated circuits package system with dense routability and high thermal conductivity
US7265442B2 (en) * 2005-03-21 2007-09-04 Nokia Corporation Stacked package integrated circuit
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
US7897503B2 (en) * 2005-05-12 2011-03-01 The Board Of Trustees Of The University Of Arkansas Infinitely stackable interconnect device and method
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7429799B1 (en) 2005-07-27 2008-09-30 Amkor Technology, Inc. Land patterns for a semiconductor stacking structure and method therefor
JP4512545B2 (ja) * 2005-10-27 2010-07-28 パナソニック株式会社 積層型半導体モジュール
DE102006003377B3 (de) * 2006-01-24 2007-05-10 Infineon Technologies Ag Halbleiterbaustein mit einem integrierten Halbleiterchip und einem Chipgehäuse und elektronisches Bauteil
KR100836663B1 (ko) * 2006-02-16 2008-06-10 삼성전기주식회사 캐비티가 형성된 패키지 온 패키지 및 그 제조 방법
US7652361B1 (en) 2006-03-03 2010-01-26 Amkor Technology, Inc. Land patterns for a semiconductor stacking structure and method therefor
US7569918B2 (en) * 2006-05-01 2009-08-04 Texas Instruments Incorporated Semiconductor package-on-package system including integrated passive components
US20070262249A1 (en) * 2006-05-11 2007-11-15 Lee Chuen C Encoder having angled die placement
US7514774B2 (en) * 2006-09-15 2009-04-07 Hong Kong Applied Science Technology Research Institute Company Limited Stacked multi-chip package with EMI shielding
JP2008166527A (ja) * 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US7701046B2 (en) * 2006-12-29 2010-04-20 Advanced Semiconductor Engineering Inc. Stacked type chip package structure
KR100817091B1 (ko) * 2007-03-02 2008-03-26 삼성전자주식회사 적층형 반도체 패키지 및 그 제조방법
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
US20080315406A1 (en) * 2007-06-25 2008-12-25 Jae Han Chung Integrated circuit package system with cavity substrate
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
JP4498403B2 (ja) * 2007-09-28 2010-07-07 株式会社東芝 半導体装置と半導体記憶装置
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8258614B2 (en) * 2007-11-12 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with package integration
US8247893B2 (en) * 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
US7800212B2 (en) * 2007-12-27 2010-09-21 Stats Chippac Ltd. Mountable integrated circuit package system with stacking interposer
JP2009188325A (ja) * 2008-02-08 2009-08-20 Nec Electronics Corp 半導体パッケージおよび半導体パッケージの製造方法
US8049320B2 (en) 2008-02-19 2011-11-01 Texas Instruments Incorporated Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
US8247894B2 (en) * 2008-03-24 2012-08-21 Stats Chippac Ltd. Integrated circuit package system with step mold recess
US7956449B2 (en) * 2008-06-25 2011-06-07 Stats Chippac Ltd. Stacked integrated circuit package system
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
US8270176B2 (en) * 2008-08-08 2012-09-18 Stats Chippac Ltd. Exposed interconnect for a package on package system
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8102666B2 (en) * 2008-08-19 2012-01-24 Stats Chippac Ltd. Integrated circuit package system
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
US8531043B2 (en) * 2008-09-23 2013-09-10 Stats Chippac Ltd. Planar encapsulation and mold cavity package in package system
US8803330B2 (en) * 2008-09-27 2014-08-12 Stats Chippac Ltd. Integrated circuit package system with mounting structure
JP5193898B2 (ja) * 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US20100276793A1 (en) * 2009-04-29 2010-11-04 Manolito Galera High pin density semiconductor system-in-a-package
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
KR101583719B1 (ko) * 2009-07-21 2016-01-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20110147908A1 (en) * 2009-12-17 2011-06-23 Peng Sun Module for Use in a Multi Package Assembly and a Method of Making the Module and the Multi Package Assembly
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
KR20110130017A (ko) * 2010-05-27 2011-12-05 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
KR101172678B1 (ko) * 2010-08-23 2012-08-09 삼성전자주식회사 낮은 열팽창 계수를 갖는 인터포저의 연결구조 및 이를 채용한 패키지 부품
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US20130027894A1 (en) * 2011-07-27 2013-01-31 Harris Corporation Stiffness enhancement of electronic substrates using circuit components
US8963310B2 (en) * 2011-08-24 2015-02-24 Tessera, Inc. Low cost hybrid high density package
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9263412B2 (en) 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US9153542B2 (en) * 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
CN103811362A (zh) * 2012-11-08 2014-05-21 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
JP2014112606A (ja) * 2012-12-05 2014-06-19 Shinko Electric Ind Co Ltd 半導体パッケージ
KR20140141281A (ko) * 2013-05-31 2014-12-10 삼성전자주식회사 반도체 패키지
KR102245770B1 (ko) * 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
US20150221570A1 (en) * 2014-02-04 2015-08-06 Amkor Technology, Inc. Thin sandwich embedded package
US9768090B2 (en) * 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
KR102228461B1 (ko) * 2014-04-30 2021-03-17 삼성전자주식회사 반도체 패키지 장치
KR102243285B1 (ko) 2014-07-01 2021-04-23 삼성전자주식회사 반도체 패키지
EP3198644A4 (en) * 2014-09-26 2018-05-23 Intel Corporation Integrated circuit package having wire-bonded multi-die stack
US9305852B1 (en) * 2014-11-11 2016-04-05 Texas Instruments Incorporated Silicon package for embedded electronic system having stacked semiconductor chips
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10546847B2 (en) * 2015-03-27 2020-01-28 Fairchild Semiconductor Corporation Substrate interposer on a leadframe
KR20170001238A (ko) * 2015-06-26 2017-01-04 에스케이하이닉스 주식회사 계단형 기판을 포함하는 반도체 패키지
WO2017049587A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Packaged integrated circuit device with recess structure
US11562955B2 (en) 2016-04-27 2023-01-24 Intel Corporation High density multiple die structure
EP3465751B1 (en) * 2016-06-03 2021-08-18 Intel Corporation Wireless module with antenna package and cap package
US20180053753A1 (en) * 2016-08-16 2018-02-22 Freescale Semiconductor, Inc. Stackable molded packages and methods of manufacture thereof
US10797039B2 (en) 2016-12-07 2020-10-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
US10388637B2 (en) * 2016-12-07 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
KR102327548B1 (ko) 2017-10-17 2021-11-16 삼성전자주식회사 반도체 패키지
KR102504293B1 (ko) 2017-11-29 2023-02-27 삼성전자 주식회사 패키지 온 패키지 형태의 반도체 패키지
KR102397905B1 (ko) * 2017-12-27 2022-05-13 삼성전자주식회사 인터포저 기판 및 반도체 패키지
CN110299328B (zh) * 2018-03-21 2021-08-13 华为技术有限公司 一种堆叠封装器件及其封装方法
US11381999B2 (en) 2019-05-10 2022-07-05 Qualcomm Incorporated Multi-link aggregation link management
US11855124B2 (en) 2019-11-15 2023-12-26 Qualcomm Incorporated Vertically integrated device stack including system on chip and power management integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213543A (ja) * 1994-10-20 1996-08-20 Hughes Aircraft Co マルチダイパッケージ装置
JPH1070233A (ja) * 1996-07-23 1998-03-10 Internatl Business Mach Corp <Ibm> マルチ電子デバイス・パッケージ
JP2001267490A (ja) * 2000-03-14 2001-09-28 Ibiden Co Ltd 半導体モジュール

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2694840B1 (fr) * 1992-08-13 1994-09-09 Commissariat Energie Atomique Module multi-puces à trois dimensions.
US5939782A (en) * 1998-03-03 1999-08-17 Sun Microsystems, Inc. Package construction for integrated circuit chip with bypass capacitor
US6313522B1 (en) * 1998-08-28 2001-11-06 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
TW415056B (en) * 1999-08-05 2000-12-11 Siliconware Precision Industries Co Ltd Multi-chip packaging structure
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
TW455964B (en) * 2000-07-18 2001-09-21 Siliconware Precision Industries Co Ltd Multi-chip module package structure with stacked chips
JP2002158326A (ja) 2000-11-08 2002-05-31 Apack Technologies Inc 半導体装置、及び製造方法
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6867500B2 (en) * 2002-04-08 2005-03-15 Micron Technology, Inc. Multi-chip module and methods
US6818978B1 (en) * 2002-11-19 2004-11-16 Asat Ltd. Ball grid array package with shielding
US7071545B1 (en) * 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
TW556961U (en) * 2002-12-31 2003-10-01 Advanced Semiconductor Eng Multi-chip stack flip-chip package
US6861288B2 (en) * 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
US7217994B2 (en) * 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213543A (ja) * 1994-10-20 1996-08-20 Hughes Aircraft Co マルチダイパッケージ装置
JPH1070233A (ja) * 1996-07-23 1998-03-10 Internatl Business Mach Corp <Ibm> マルチ電子デバイス・パッケージ
JP2001267490A (ja) * 2000-03-14 2001-09-28 Ibiden Co Ltd 半導体モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710642B2 (en) 2011-03-25 2014-04-29 Fujitsu Semiconductor Limited Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus

Also Published As

Publication number Publication date
US20070290319A1 (en) 2007-12-20
US7279786B2 (en) 2007-10-09
KR20070115877A (ko) 2007-12-06
KR101099773B1 (ko) 2011-12-28
WO2006084177A2 (en) 2006-08-10
US8169064B2 (en) 2012-05-01
US20060175696A1 (en) 2006-08-10
WO2006084177A3 (en) 2009-04-09

Similar Documents

Publication Publication Date Title
US7279786B2 (en) Nested integrated circuit package on package system
KR101874057B1 (ko) 패키지 적층체를 구비한 집적회로 패키지 시스템 및 그 제조 방법
US9236319B2 (en) Stacked integrated circuit package system
US7977579B2 (en) Multiple flip-chip integrated circuit package system
US7750454B2 (en) Stacked integrated circuit package system
TWI384612B (zh) 具有雙側連接之積體電路封裝件系統
US7445962B2 (en) Stacked integrated circuits package system with dense routability and high thermal conductivity
US12205906B2 (en) Electronic package and fabrication method thereof
KR101424777B1 (ko) 집적 회로 패키지 시스템
US7071569B2 (en) Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection
TWI506707B (zh) 具有導線架插入件的積體電路封裝系統及其製造方法
KR20050064144A (ko) 수직 실장된 반도체 칩 패키지를 갖는 반도체 모듈
US7786571B2 (en) Heat-conductive package structure
US7833840B2 (en) Integrated circuit package system with down-set die pad and method of manufacture thereof
US20120168936A1 (en) Multi-chip stack package structure and fabrication method thereof
US8269329B2 (en) Multi-chip package
TW202234530A (zh) 半導體裝置及其製造方法
TWI391084B (zh) 具有散熱件之電路板結構
US12159792B2 (en) Flip chip package unit comprising thermal protection film and associated packaging method
JP4919689B2 (ja) モジュール基板
US7327025B2 (en) Heat spreader for thermally enhanced semiconductor package
JP3850712B2 (ja) 積層型半導体装置
TW202326952A (zh) 垂直式多晶片裝置
KR20000001313A (ko) 적층형 반도체 패키지
KR19990079132A (ko) 반도체 패키지

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090203

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090203

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20090203

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20090302

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090310

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090604

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090707

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100216

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100316

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100715

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100913

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20101029