WO2006084177A2 - Nested integrated circuit package on package system - Google Patents

Nested integrated circuit package on package system Download PDF

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Publication number
WO2006084177A2
WO2006084177A2 PCT/US2006/003927 US2006003927W WO2006084177A2 WO 2006084177 A2 WO2006084177 A2 WO 2006084177A2 US 2006003927 W US2006003927 W US 2006003927W WO 2006084177 A2 WO2006084177 A2 WO 2006084177A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
package
integrated circuit
layer
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/003927
Other languages
English (en)
French (fr)
Other versions
WO2006084177A3 (en
Inventor
Hyun Uk Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Stats Chippac Inc
Original Assignee
Stats Chippac Pte Ltd
Stats Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd, Stats Chippac Inc filed Critical Stats Chippac Pte Ltd
Priority to KR1020077018095A priority Critical patent/KR101099773B1/ko
Priority to JP2007554259A priority patent/JP2008533700A/ja
Publication of WO2006084177A2 publication Critical patent/WO2006084177A2/en
Anticipated expiration legal-status Critical
Publication of WO2006084177A3 publication Critical patent/WO2006084177A3/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Definitions

  • the present invention relates generally to integrated circuit package systems, and more particularly to a system for Package in Packages (PIP) or Package on Package (POP).
  • PIP Package in Packages
  • POP Package on Package
  • MCM multi-chip module
  • the system of increasing semiconductor density on a circuit board by stacking semiconductor packaged devices one on top of another is commonly referred to a "package to package” or a "package on package” assembly.
  • One problem with the current package to package system assembly is difficulties caused by irregularities in the flatness/coplanarity of the lower package.
  • Another problem results from the increased stiffness of the overall assembly, which can lead to reduced board level reliability.
  • Still another problem can arise from poor heat dissipation from the upper package.
  • the typical package on package stacked semiconductor assembly uses an interposer structure between the first package and the second package.
  • a second package fits mounts onto a interposer substrate using a ball grid array (BGA) interface.
  • the interposer substrate provides electrical contact points at the peripheral boundary.
  • the second package electrically couples to the first substrate through the ball grid array (BGA) interface through the interposer substrate then connected to the first substrate.
  • BGA ball grid array
  • the present invention provides a package on package system including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein.
  • the first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
  • FIG. 1 is a cross-section of an integrated circuit package on package system in accordance with an embodiment of the present invention
  • FIG. 2 is a more detailed cross-section of the second substrate shown in FIG. 1 ;
  • FIG. 3 is a more detailed cross-section of the first package shown in FIG. 1;
  • FIG. 4 is a more detailed cross-section of the second package shown in FIG. 1;
  • FIG. 5 is a more detailed cross-section of the first package of FIG. 3 nested in the second package of FIG. 4;
  • FIG. 6 is a cross-section of a package on package system after assembly and a second backend process;
  • FIG. 7 is a more detailed cross-section of the second substrate of FIG. 2 prior to assembly;
  • FIG. 8 is a more detailed cross-section of the second substrate of FIG. 2 in accordance with another embodiment of the present invention.
  • FIG. 9 is a flow chart of a package on package system for manufacturing an integrated circuit package on package system in accordance with a further embodiment of the present invention.
  • horizontal as used herein is defined as a plane parallel to the conventional plane or surface of the die or package or substrate, regardless of its orientation.
  • vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
  • processing as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
  • the integrated circuit package on package system 100 comprises a first package 102 stacked below a second package 104.
  • the first package 102 comprises a first substrate 106, wherein the first substrate 106 comprises a top surface 122 and a bottom surface 124, and a first set of integrated circuits 126 mounted on the top surface 122.
  • the second package 104 comprises a second substrate 110, wherein the second substrate 110 comprises a top surface 118 and a bottom surface 120, and a second set of integrated circuits 402 of FIG. 4 mounted on the top surface 118.
  • a second ball grid array
  • BGA interface 108 is on the bottom surface 120 of the second substrate 110, wherein the second ball grid array (BGA) interface 108 provides electrical, mechanical, and thermal connectivity between the first substrate 106 and the second substrate 110.
  • the bottom surface 120 of the second substrate 110 comprises a predefined recess 112 to nest the first set of integrated circuits 126 mounted on the top surface 122 on the first substrate 106.
  • a first ball grid array (BGA) interface 116 is on the bottom surface 124 of the first substrate 106, wherein the first ball grid array (BGA) interface 116 provides electrical, mechanical, and thermal connectivity between the first substrate 106 and an external printed circuit board (not shown).
  • the electrical and mechanical interface between the first package 102 and the second package 104 is a ball grid array (BGA) interface 116 in this embodiment, although it is understood that other coupling mechanisms may be used in accordance with the principles of the present invention.
  • FIG. 2 therein is shown a more detailed cross-section of the second substrate 110 shown in FIG. 1.
  • the second substrate 110 has the predefined recess 112 to provide a clearance for the first set of integrated circuits 126 mounted on the top surface 122 on the first substrate 106 of FIG. 1.
  • the predefined recess 112 comprises a hollowed out area along with a recess height
  • the recess height 210 along with the second ball grid array (BGA) interface
  • the second substrate 110 is shown as a four-layer substrate having a first layer 202, a second layer 204, a third layer 206, and a fourth layer 208. Although the second substrate 110 is shown as four layers, it is understood the number of layers may differ in accordance with the principles of the present invention.
  • FIG. 3 therein is shown a more detailed cross-section of the first package 102 shown in FIG. 1.
  • the first package 102 is shown without the first ball grid array (BGA) interface 116 attached to the bottom surface 124 of the first substrate 106.
  • the first package 102 comprising the first set of integrated circuits 126, such as, two stacked semiconductor dice comprising a top semiconductor die 304 above a bottom semiconductor die 306, mounted on the first substrate 106.
  • the top semiconductor die 304 and the bottom semiconductor die 306 are electrically attached to the top surface 122 of the first substrate 106 by a plurality of wire bond wires 302.
  • top semiconductor die 304 and the bottom semiconductor die 306 may be electrically couple the top semiconductor die 304 and the bottom semiconductor die 306 to the top surface 122 of the first substrate 106.
  • the top surface 122 of the first substrate 106 further comprises a first set of contact points 308.
  • the second ball grid array (BGA) interface 108 of FIG. 1 is electrically and mechanically coupled to the first set contact points 308.
  • the bottom surface 124 of the first substrate 106 further comprises a plurality of contact sites 310 for providing electrical, mechanical, and thermal connection to the first ball grid array (BGA) interface 116.
  • the first set of integrated circuits 126 is shown to comprise the top semiconductor die 304 and the bottom semiconductor die 306 in a stacked orientation, although it is understood the relative orientation of the one or more semiconductor need not be stacked or any combination thereof.
  • top semiconductor die 304 and the bottom semiconductor die 306 may be other elements, such as passive elements and circuits.
  • the one or more semiconductor dice size may differ or be similar relative to each other.
  • the one or more semiconductor dice functionality may differ or be similar.
  • the second package 104 comprises the second set of integrated circuits 402 mounted on the top surface 118 of the second substrate 110, wherein the second set of integrated circuits 402 comprise two stacked semiconductor dice comprising a top semiconductor die 404 above a bottom semiconductor die 406.
  • the top semiconductor die 404 and the bottom semiconductor die 406 are shown to be electrically coupled to the second substrate 110 by a plurality of wire bond wires 408. It is understood the techniques, such as direct attach, TAB, or flip chip, may be used to electrically couple the top semiconductor die 404 and the bottom semiconductor die 406 to the second substrate 110.
  • the second set of integrated circuits 402 is shown to comprise the top semiconductor die 404 and the bottom semiconductor die 406 in a stacked orientation, although it is understood the relative orientation of the one or more semiconductor need not be stacked or any combination thereof.
  • the top semiconductor die 404 and the bottom semiconductor die 406 may be other elements, such as passive elements and circuits.
  • the one or more semiconductor dice size may differ or be similar relative to each other.
  • the one or more semiconductor dice functionality may differ or be similar.
  • the predefined recess 112 provides reduced spacing between the first substrate 106 and the second substrate 110.
  • the integrated circuit package on package system 100 with the predefined recess 112 also avoids molding problems, and can accommodate various thicknesses of the top semiconductor die 304 and the bottom semiconductor die 306 as well as other multi-stack possibilities.
  • the predefined recess 112 may comprise a ring-like structure, although it is understood the predefined recess 112 may comprise different shape and dimension to accommodate the physical dimensions of the first package 102.
  • FIG. 5 therein is shown a more detailed cross-section of the first package 102 nested in the second package 104.
  • An epoxy layer 502 on the encapsulant 503 of the first package 102 further connects the first package and the second package.
  • the second ball grid array (BGA) interface 108 electrically, mechanically, and thermally couples the bottom surface 120 of the second substrate 110 to the top surface 122 of the first substrate 106.
  • FIG. 6 therein is shown a cross-section of the integrated circuit package on package system 100 after assembly and a second backend process.
  • the second backend process includes such processes as solder ball mount (SBM), singulation (SGN), and external visual inspection (EVI) with the first package 102 further comprising the first ball grid array (BGA) interface 116 electrically coupling to an external printed circuit board (not shown).
  • SBM solder ball mount
  • SGN singulation
  • EVI external visual inspection
  • FIG. 7 therein is shown a more detailed cross-section of the second substrate 110 of FIG. 2 prior to assembly.
  • the second substrate 110 is shown in an orientation vertically flipped from previous figures, before assembly.
  • the top surface 118 comprises a flat, two layer substrate comprising the first layer 202 and the second layer 204 coupled with an adhesive layer 704.
  • the first layer 202 comprises one or more metallic regions 706 used to electrically and mechanically connect the top semiconductor die 404 and the bottom semiconductor die 406 to the second substrate 110 by the plurality of wire bond wires 408.
  • the metallic regions 706 also provide signal conduction paths, voltage supply, ground, and other electrical functions.
  • the first layer 202 of the second substrate 110 also comprises one or more non- metallic insulating regions 708 that insulate the metallic regions 706.
  • the second layer 204 of the second substrate 110 comprises one or more metallic regions 710.
  • the metallic regions 710 also provide signal conduction paths, voltage supply, ground, and other electrical functions.
  • the second layer 204 of the second substrate 110 comprises one or more non-metallic insulating regions 712 that insulate the metallic regions 710.
  • an electrical via 714 electrically couples the metallic region 706 of the first layer 202 to the metallic region 710 of the second layer 204 of the second substrate 110.
  • a dielectric layer 716 insulates and separates the first layer 202 from the second layer 204 of the second substrate 110.
  • the second substrate 110 with the bottom surface 120 being a two layer substrate, comprised of the third layer 206 and the fourth layer 208, bonded to the top surface 118 of the second substrate 110 with the first layer 202 and the second layer 204 to form the second substrate 110.
  • the second substrate 110 has the predefined recess 112 in the bottom surface 120 of the second substrate 110.
  • the third layer 206 of the second substrate 110 comprises one or more metallic regions 806 used for the electrical coupling to the metallic region 710 of the second layer 204 of the second substrate 110.
  • the metallic regions 806 also provide signal conduction paths, voltage supply, ground, and other electrical functions.
  • the third layer 206 of the second substrate 110 comprises one or more non-metallic insulating regions 808 that insulate the metallic regions 806.
  • the fourth layer 208 of the second substrate 110 comprises one or more metallic regions 810.
  • the metallic regions 810 also provide signal conduction paths, voltage supply, ground, and other electrical functions.
  • the fourth layer 208 of the second substrate 110 comprises one or more non-metallic insulating regions 812 that insulate the metallic regions 810.
  • an electrical via 814 electrically connects the metallic region 806 of the third layer 206 to the metallic regions 810 of the fourth layer 208 of the second substrate 110.
  • a dielectric layer 816 separates the third layer 206 and the fourth layer 208 of the second substrate 110.
  • the electrical connection between substrate layers is describe as electrical vias, although it is understood that other electrical coupling structures may be used.
  • the package on package system 900 includes providing a first substrate having a first integrated circuit thereon in a block 902; providing a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein in a block 904; and mounting the first and second substrate having the first integrated circuit at least partially nested in the recess in a block 906.
  • a system to provide the integrated circuit package on package system
  • the package on package stacking is created utilizing only the attributes of the first substrate 106 of the first package 102 and the second substrate 110 of the second package 104. (FIG. 1)
  • the predefined recess 112 on the bottom surface 120 of the second substrate 110 provides a hollowed out area to nest the first set of integrated circuits 126 mounted on the top surface 122 on the first substrate 106.
  • the first package 102 comprising the first substrate 106 having the first set of contact points 308 for the second ball grid array (BGA) interface 108 of the second package 104.
  • BGA ball grid array
  • An advantage is that the present invention provides more degrees of freedom for the dice thickness or the number of dice in the stack comprised in the first package 102 resulting in relaxed manufacturing flow and materials requirements.
  • the selection of EMC could be broadened to use either the normal or the fine filler size EMC. It has been discovered that the disclosed structure results in the increased density of the solder balls comprised in the second ball grid array (BGA) interface 108.
  • BGA ball grid array
  • yet another discovery of the present invention is the increased density of the solder balls of the second ball grid array (BGA) interface 108 coupled to more of the first set of contact points 308 of the first substrate 106 results in providing mechanical rigidity for the integrated circuit package on package system 100.
  • BGA ball grid array
  • BGA ball grid array
  • the overall system dimension may be reduced by accommodation of the mold end height 114 of the first package 102 with the bottom surface 120 of the second substrate 110 having the predefined recess 112 providing the hollowed out area for.
  • Yet another important advantage of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
PCT/US2006/003927 2005-02-04 2006-02-04 Nested integrated circuit package on package system Ceased WO2006084177A2 (en)

Priority Applications (2)

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KR1020077018095A KR101099773B1 (ko) 2005-02-04 2006-02-04 내포된 집적 회로 패키지 온 패키지 시스템
JP2007554259A JP2008533700A (ja) 2005-02-04 2006-02-04 ネストされた集積回路パッケージオンパッケージシステム

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US65027905P 2005-02-04 2005-02-04
US60/650,279 2005-02-04
US11/257,894 2005-10-24
US11/257,894 US7279786B2 (en) 2005-02-04 2005-10-24 Nested integrated circuit package on package system

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US20070290319A1 (en) 2007-12-20
US7279786B2 (en) 2007-10-09
KR20070115877A (ko) 2007-12-06
KR101099773B1 (ko) 2011-12-28
JP2008533700A (ja) 2008-08-21
US8169064B2 (en) 2012-05-01
US20060175696A1 (en) 2006-08-10
WO2006084177A3 (en) 2009-04-09

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