JP2008533700A - ネストされた集積回路パッケージオンパッケージシステム - Google Patents
ネストされた集積回路パッケージオンパッケージシステム Download PDFInfo
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Abstract
Description
本願は、2005年2月4日に出願した米国特許仮出願番号第60/650,279号の利益を主張し、その内容を参照によって本書に援用する。
本発明は一般的に集積回路パッケージシステムに関し、さらに詳しくは、パッケージインパッケージ(Package in Packages)(PIP)またはパッケージオンパッケージ(Package on Package)(POP)のためのシステムに関する。
回路基板のようなキャリア基板上で集積回路によって使用される表面積つまり「リアルエステート」の量を節約するために、様々な種類の高密度パッケージが開発されてきた。これらの高密度パッケージの種類の中に、いわゆる「マルチチップモジュール」(MCM)がある。数種類のマルチチップモジュールには、相互に上下に積層した集積回路の組立体が含まれる。集積回路を積層することによって節約することのできるキャリア基板の表面積の量は容易に理解できる。
本発明は、第1集積回路を有する第1基板および第2集積回路を有する第2基板を含み、第2基板に凹所が設けられて成る、パッケージオンパッケージシステムを提供する。第1および第2基板は、第1集積回路を凹所に少なくとも部分的にネストさせた状態で、実装される。
以下の説明では、本発明の完全な理解をもたらすために、多数の具体的な詳細を提示する。しかし、本発明がこれらの具体的な詳細無しに実施できることは明らかであろう。本発明を曖昧にすることを避けるために、一部の周知のシステム構成およびプロセスステップは詳細には開示しない。同様に、本発明の実施形態を示す図面は概略図であって、原寸に比例するものではなく、特に、寸法の一部は明瞭に提示するために、図では非常に誇張して示されている。一般的に、デバイスはどのような向きでも動作することができる。全ての図で、同じ要素に関連して同じ番号が使用されている。
は、第1基板106と外部プリント回路基板(図示せず)との間の電気的、機械的、および熱的接続性を提供する。例示を目的として、第1パッケージ102と第2パッケージ104との間の電気的および機械的インタフェースは、この実施形態ではボールグリッドアレイ(BGA)インタフェース116であるが、本発明の原理に従って他の結合機構を使用することができることは理解される。
に結合されるように図示されている。直接取付け、TAB、またはフリップチップのような技術を使用して、頂部半導体ダイ404および底部半導体ダイ406を第2基板110に電気的に結合することができることは理解される。
2は、金属領域706を絶縁する1つまたはそれ以上の非金属絶縁領域708をも含む。
2.第2基板110の底面120の予め定められた凹所112は、第1基板106の頂面122に実装された第1組の集積回路126をネストするためのくり抜き領域を提供する。(図2)
3.第1パッケージ102は、第2パッケージ104の第2ボールグリッドアレイ(B
GA)インタフェース108のための第1組の接触点308を有する第1基板106を含む。(図3)
利点は、本発明が第1パッケージ102に含まれるスタックにおけるダイの厚さまたはダイの数についてより高い自由度をもたらし、その結果、製造の流れおよび材料要件が緩和されることである。例えば、通常または微小いずれかの充填材粒径のEMCを使用するように、EMCの選択の幅を広げることができる。
Claims (10)
- 第1集積回路(126)を有する第1基板(106)を提供するステップと、
第2集積回路(402)を有する第2基板(110)であって、凹所(112)が設けられた第2基板(110)を提供するステップと、
前記第1集積回路(126)を前記凹所(112)に少なくとも部分的にネストさせた状態で、前記第1および第2基板(106)(110)を実装するステップとを含むパッケージオンパッケージシステム(100)。 - 前記第1集積回路(126)の周囲に封止体(503)を成形するステップと、
前記封止体(503)を前記凹所(112)内に配置するステップとをさらに含む、請求項1に記載のシステム(100)。 - 前記第1および第2基板(106)(110)の間に電気的接続(108)を形成するステップをさらに含む、請求項1に記載のシステム(100)。
- 前記第1基板(106)の前記第1集積回路(126)の下に電気的接続(116)を形成するステップをさらに含む、請求項1に記載のシステム(100)。
- 前記第2基板(110)を提供するステップがさらに、
前記第1集積回路(126)をその上に設けるための第1層(202)を形成するステップと、
前記第1層(202)と協働して前記凹所(112)を形成するために、貫通穴が設けられた第2層(204)を形成するステップとを含む、請求項1に記載のシステム(100)。 - 第1集積回路(126)を有する第1基板(106)と、
第2集積回路(402)を有する第2基板(110)とを備え、
前記第2基板(110)に凹所(112)が設けられ、前記第1および第2基板(106)(110)は、前記凹所(112)に少なくとも部分的にネストされた前記第1集積回路(126)を有する、パッケージオンパッケージシステム(100)。 - 前記第1集積回路(126)の周囲および前記凹所(112)内に封止体(503)をさらに備える、請求項6に記載のシステム(100)。
- 前記第1および第2基板(106)(110)の間に電気的接続(108)をさらに備える、請求項6に記載のシステム(100)。
- 前記第1基板(106)の前記第1集積回路(126)の下に電気接続(116)をさらに備える、請求項6に記載のシステム(100)。
- 前記第2基板(110)が、
前記第1集積回路(126)を有するための第1層(202)と、
前記第1層(202)と協働して前記凹所(112)を形成するために、貫通穴が設けられた第2層(204)とをさらに備える、請求項6に記載のシステム(100)。
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US65027905P | 2005-02-04 | 2005-02-04 | |
US11/257,894 US7279786B2 (en) | 2005-02-04 | 2005-10-24 | Nested integrated circuit package on package system |
PCT/US2006/003927 WO2006084177A2 (en) | 2005-02-04 | 2006-02-04 | Nested integrated circuit package on package system |
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Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20100913 |
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A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20101029 |