JP2008510320A - 勾配半導体層 - Google Patents

勾配半導体層 Download PDF

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Publication number
JP2008510320A
JP2008510320A JP2007527945A JP2007527945A JP2008510320A JP 2008510320 A JP2008510320 A JP 2008510320A JP 2007527945 A JP2007527945 A JP 2007527945A JP 2007527945 A JP2007527945 A JP 2007527945A JP 2008510320 A JP2008510320 A JP 2008510320A
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JP
Japan
Prior art keywords
semiconductor layer
germanium
layer
concentration
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007527945A
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English (en)
Japanese (ja)
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JP2008510320A5 (enExample
Inventor
ジー． サダカ、マリアム
ジー． トーマス、ショーン
アール． ホワイト、テッド
リュウ、チュン−リ
エル． バール、アレクサンダー
ニューエン、ビック−イェン
シーン、ブーン−ユウ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2008510320A publication Critical patent/JP2008510320A/ja
Publication of JP2008510320A5 publication Critical patent/JP2008510320A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2007527945A 2004-08-17 2005-08-08 勾配半導体層 Pending JP2008510320A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/919,952 US7241647B2 (en) 2004-08-17 2004-08-17 Graded semiconductor layer
PCT/US2005/029113 WO2006023492A1 (en) 2004-08-17 2005-08-08 Graded semiconductor layer

Publications (2)

Publication Number Publication Date
JP2008510320A true JP2008510320A (ja) 2008-04-03
JP2008510320A5 JP2008510320A5 (enExample) 2008-09-25

Family

ID=35910124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007527945A Pending JP2008510320A (ja) 2004-08-17 2005-08-08 勾配半導体層

Country Status (6)

Country Link
US (1) US7241647B2 (enExample)
JP (1) JP2008510320A (enExample)
KR (1) KR20070047307A (enExample)
CN (1) CN100472761C (enExample)
TW (1) TWI371087B (enExample)
WO (1) WO2006023492A1 (enExample)

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DE102009010883B4 (de) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
CN102903635B (zh) * 2011-07-25 2015-05-06 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制造方法
CN102903636B (zh) * 2011-07-25 2015-05-06 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制造方法
US20140057399A1 (en) * 2012-08-24 2014-02-27 International Business Machines Corporation Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
CN105679645A (zh) * 2014-11-17 2016-06-15 上海华力微电子有限公司 嵌入式锗硅外延位错缺陷的改善方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
JP2003197544A (ja) * 2001-12-27 2003-07-11 Sumitomo Mitsubishi Silicon Corp 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
JP2005072054A (ja) * 2003-08-27 2005-03-17 Toshiba Corp 歪み緩和ＳｉＧｅ基板の製造方法

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US3912559A (en) * 1971-11-25 1975-10-14 Suwa Seikosha Kk Complementary MIS-type semiconductor devices and methods for manufacturing same
US4851257A (en) * 1987-03-13 1989-07-25 Harris Corporation Process for the fabrication of a vertical contact
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5756898A (en) * 1994-06-27 1998-05-26 Texaco Inc. Passive acoustic method of measuring the effective internal diameter of a pipe containing flowing fluids
DE59707274D1 (de) * 1996-09-27 2002-06-20 Infineon Technologies Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5943565A (en) * 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US5846857A (en) * 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6124627A (en) * 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6259138B1 (en) * 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
JP3884203B2 (ja) 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
US6369438B1 (en) * 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2001036054A (ja) * 1999-07-19 2001-02-09 Mitsubishi Electric Corp Ｓｏｉ基板の製造方法
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
KR100392166B1 (ko) * 2000-03-17 2003-07-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법 및 반도체 장치
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
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US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020168802A1 (en) * 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
US6475870B1 (en) * 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture
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US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
JP2003197544A (ja) * 2001-12-27 2003-07-11 Sumitomo Mitsubishi Silicon Corp 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
JP2005072054A (ja) * 2003-08-27 2005-03-17 Toshiba Corp 歪み緩和ＳｉＧｅ基板の製造方法

Also Published As

Publication number Publication date
WO2006023492A1 (en) 2006-03-02
CN101006580A (zh) 2007-07-25
TWI371087B (en) 2012-08-21
CN100472761C (zh) 2009-03-25
US20060040433A1 (en) 2006-02-23
TW200620572A (en) 2006-06-16
KR20070047307A (ko) 2007-05-04
US7241647B2 (en) 2007-07-10

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