CN101160664B - 压缩SiGe<110>生长的MOSFET器件及其制造方法 - Google Patents

压缩SiGe<110>生长的MOSFET器件及其制造方法 Download PDF

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CN101160664B
CN101160664B CN2005800153966A CN200580015396A CN101160664B CN 101160664 B CN101160664 B CN 101160664B CN 2005800153966 A CN2005800153966 A CN 2005800153966A CN 200580015396 A CN200580015396 A CN 200580015396A CN 101160664 B CN101160664 B CN 101160664B
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K·K·陈
K·W·瓜里尼
M·耶奥
K·里姆
杨敏
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Abstract

本发明公开了一种用于传导载流子的结构及其形成方法，结合具有<110>的上表面的Si或SiGe单晶衬底和SiGe伪晶或外延层，其具有不同于衬底的Ge浓度从而伪晶层处于应变。公开了一种形成半导体外延层的方法，结合在快速热化学气相沉积(RTCVD)工具中通过将工具中的温度升高到约600℃并且引入含Si气体和含Ge气体形成伪晶或外延层的步骤。公开了一种用于外延沉积化学处理衬底的方法，包括如下步骤：将衬底浸入一系列分别含有臭氧，稀HF，去离子水，HCl酸和去离子水的浴中，随后在惰性气氛中干燥衬底以获得无杂质并且具有小于0.1nm的RMS粗糙度的衬底表面。

Description

压缩SiGe<110>生长的MOSFET器件及其制造方法
技术领域
本发明涉及先进的互补金属氧化物半导体(CMOS)晶体管器件的设计和材料工艺，更具体地说涉及压缩应变SiGe材料。
背景技术
随着CMOS晶体管器件尺寸的下降，提高电路的性能的方法变得更重要。做此事的一种方法是增强沟道区域中载流子的迁移率；即增强电子或空穴迁移率。这可以通过几种方法实现：
1.在硅衬底上使用不同的Si晶格尺寸以获得应变。一般地，驰豫SiGe过渡层上应变硅或SOI上应变硅(SSDOI)在高Ge浓度SiGe合金下表现出N-FET上约2x的电子迁移率的增强和p-FET上50％的空穴迁移率的增强。其很大程度上是因为硅处在双轴拉伸应变下。然而，大多数这样的拉伸应变Si包括高密度的缺陷。
2.在如Si<110>衬底的不同表面取向硅上制造MOSFET在P-FET中表现出～1.5x的空穴迁移率增强但是N-FET的电子迁移率却有相当大的下降。Min Yang在IEDM 2003上描述了一种混合取向衬底，其将Si<110>衬底和Si<100>衬底结合在一起，以便在Si<110>衬底上制造P-FET用于增强空穴迁移率并且在Si<100>上制造N-FET以保持N-FET的性能。
发明内容
需要一种在CMOS中获得空穴和电子载流子的增强的解决方法。
本发明提供一种具有增强的载流子迁移率的半导体材料，其包括在双轴压缩应变下的具有<110>表面晶向的SiGe合金层。双轴压缩应变表示由纵向压缩应力和横向压缩应力引起的净应力，其在半导体材料生长期间在SiGe合金层的平面内引起。
可以通过在如Si或SiGe的具有较小晶格间隔的基层或衬底上形成层在SiGe层中形成双轴压缩应变，其中Ge的浓度小于在其上的压缩应变层中的Ge浓度。
可以通过在如SiGe的具有较大晶格间隔的基层或衬底上外延形成层在SiGe层中形成双轴拉伸应变，其中Ge的浓度大于在其上的拉伸应变层中的Ge浓度。
本发明的半导体材料包括具有双轴压缩应变的<110>表面取向的SiGe合金层，为N-MOS和P-MOS场效应晶体管提供增强的迁移率。
本发明的另一个方面涉及形成本发明的半导体材料的方法，其中本发明的方法包括如下步骤：提供硅锗合金<110>层；在此硅锗合金含<110>层中具有双轴压缩应变。
在一个实施例中，通过包括如下步骤的方法制造具有<110>表面取向和双轴压缩应变的SiGe合金层。
使用如下步骤处理Si或SiGe<110>衬底表面：23℃的DI水中10ppm的臭氧，100∶1的稀氢氟酸1min，DI水冲洗5min，在23℃的DI水中1∶100体积比的盐酸，最后DI水冲洗5min。然后是在30℃以上在如N2的惰性气氛中加热，冲洗并干燥。处理后的衬底表面具有小于或等于约0.1nm的RMS。
下一步，在Si或SiGe<110>衬底上形成外延结晶压缩应变SiGe合金层，其通过上述清洁工艺处理，通过使用硅烷或锗烷气体的快速热化学气相沉积(RTCVD)，在从600℃到650℃的温度范围内，在等于20Torr的气压下生长。在我们的情况下，通过使用100sccm的硅烷，40sccm的锗烷，600℃的温度和7torr的气压下134秒，压缩应变22％SiGe合金的厚度应该低于20nm。此SiGe层在Si或SiGe<110>衬底上是压缩应变或伪晶。通过AFM测量的表面粗糙度低于0.2nm并且缺陷密度在器件的质量范围内(低于5×107缺陷/cm2)。
另外，在Si或SiGe<110>衬底上的外延结晶压缩应变SiGe合金层可以在由Applied Material Corporation，HTF模型的Centura平台建立的快速热化学气相沉积系统(RTCVD)中生长。此系统包括6个室；2个进片室，1个转换室，1个快速热退火(RTP)室，2个高温多晶硅(HTP)室。在600℃到650℃范围内的HTP室中生长压缩应变SiGe合金层。
另外，可以在具有浅沟槽隔离的外延结晶压缩应变SiGe合金区域上形成CMOS器件。
另外，可以在具有浅沟槽隔离的外延结晶压缩应变SiGe合金区域上形成具有如具有高于3.9的介电常数的金属氧化物，金属硅化物的高K栅极介质的CMOS器件。
另外，可以在具有浅沟槽隔离的外延结晶压缩应变SiGe合金区域上的栅极介质或高K介质上形成具有金属栅极和金属硅化物的CMOS器件。
附图说明
通过下面结合附图对本发明的详细描述，本发明的这些和其它特征，目的以及优点将更清楚，其中：
图1示出了在(110)表面取向的硅衬底上的RTCVD生长22％SiGe合金层上的5nm Si覆层的TEM微观图。
图2示出了Si<110>表面在化学处理(清洁)工序后的AFM图像。
图3示出了在(110)表面取向硅衬底上的压缩应变或伪晶的厚度小于20nm的SiGe 22％Ge的RAMAN分析的曲线图。
图4示出了在(110)表面取向硅衬底上的SiGe合金的临界厚度曲线。
图5示出了通过RAMAN分析在(110)表面取向硅衬底上的22％SiGe合金层的热稳定性。
图6示出了在(110)表面取向硅衬底上的压缩应变的22％SiGe合金层上制造的MOSFET。
图7示出了空穴迁移率对反向电荷的曲线图，示出了在22％SiGe层<110>上的空穴迁移率高于Min Yang在IEDM 2003上报道的Si<110>的约10到15％，高于Si层<100>即控制层的约180％。
具体实施方式
参考附图，特别是图1，TEM微观图示出了在单晶硅衬底16的(110)表面14上的SiGe合金层12。在通过快速热化学气相沉积(RTCVD)工艺生长的SiGe合金层12中的Ge浓度为22％。层12的厚度为18nm。在层12上生长厚度为5nm的Si覆层18。
在沉积层12前，化学处理衬底16的上表面14。图2示出了部分表面14在化学处理后的原子力显微(AFM)图像。化学处理包括选择具有表面粗糙度小于0.2nm的Si或SiGe衬底16，将衬底16浸入在23℃下的去离子水中10PPM臭氧的第一浴中，将衬底16浸入稀HF 100∶1的第二浴中至少1分钟，将衬底16浸入去离子水的第三浴中至少5分钟，将衬底16浸入在23℃下的HCl酸和去离子水至少1∶100的第四浴中，将衬底16浸入去离子水的第五浴中至少5分钟，并且从第五浴移出衬底16以在包括如氮气的惰性气氛中并且在至少30℃的温度下干燥衬底16。通过RMS的表面粗糙度等于0.109nm并且Z范围等于1.174nm，其与最初的Si<110>表面相当。
形成SiGe外延层12的步骤包括选择具有<110>的上表面的Si或SiGe单晶衬底16，将单晶衬底16载入快速热化学气相沉积工具中，将工具中的气压降低到0.2Torr以下，升高工具中的温度到约600℃并且引入如硅烷的含硅气体和如锗烷的含锗气体，从而在衬底16上形成SiGe伪晶层，其具有的Ge浓度不同于所述衬底从而伪晶层12是应变层。
图3示出了层12作为厚度的函数的RAMAN分析。在图3中，纵坐标表示驰豫百分比并且横坐标表示nm厚度。曲线30具有曲线部分34，这一部分的层12是伪晶，在曲线30的点35处开始层12的驰豫。曲线部分36示出了随着层12的厚度增加驰豫加速。只要层12低于20nm，层12仍为伪晶。伪晶指外延或晶格匹配和/或与衬底晶格一致。因此SiGe22％的晶格间隔一般大于Si并且通过伪晶处于压缩应变。对110 Si中的晶格间隔在x和y方向上为5.4埃。Ge的晶格间隔在x和y方向上为5.6埃，大于Si的约4％。SiGe合金具有的晶格间隔是Si和Ge的浓度的线性函数。因此当层12是<110>Si上的伪晶时，在SiGe中22％的Ge浓度导致约1％的压缩应变。在<100>Si上压缩相同。曲线32示出了SiGe层<100>作为厚度的函数的驰豫。
图4的曲线40示出了在<110>表面取向的Si衬底上的SiGe合金的临界厚度。在图4中，纵坐标表示nm临界厚度，横坐标表示在SiGe合金中Ge的百分比。在图4中，具有的厚度在曲线40下的SiGe的层12为伪晶。
图5的曲线50-53，通过RAMAN分析示出了在MOSFET制造期间SiGe合金层12的热稳定性。在图5中，纵坐标表示a.b.u.强度，横坐标表示1/cm波数。λ等于325nm。曲线50示出了Si 110的波数520 1/cm。曲线51-53示出了通过快速热退火(RTA)在1000℃下高达400秒的热循环后约514 1/cm的波数。图5中，曲线51-53显示，在1000℃的RTA期间，层12仍为伪晶。在RTA期间或之后没有观察到层12的驰豫。
图6是在Si衬底16的<110>表面14上的压缩应变22％SiGe合金层12上制造的MOSFET器件的扫描显微图像。首先化学处理衬底16的上表面14。然后在衬底16上制造层12。下一步，在衬底16中形成浅沟槽隔离(STI)区域60以提供将制造的MOSFET的电隔离。下一步，在层12上生长栅极介质层62。栅极介质层62为约2.5nm厚的N2O氧化物。栅极介质层62向下接触SiGe合金层12。在栅极介质层62下在SiGe合金层12上剩余小于0.5nm的Si覆盖层18，意味着N2O氧化物接触SiGe合金层12。下一步，在栅极介质层62上形成多晶硅层64。下一步，通过形成掩膜和反应离子蚀刻(RIE)光刻构图层64和栅极介质层62以形成MOSFET66的栅极介质63和栅极电极65。下一步，通过离子注入形成源极68和漏极69，使用栅极用于源极和漏极的自对准。下一步，与多晶硅栅极65相邻形成侧壁隔离物70。
图7是有效空穴迁移率对反向载流子密度的曲线图。在图7中，纵坐标表示cm2/VSec的有效空穴迁移率，横坐标表示1/cm2的反向载流子密度。曲线74是在层12即图6中示出的MOSFET 66的沟道中空穴迁移率的分布。测量并然后绘制以形成曲线74的空穴迁移率高于在曲线75中示出的Si<110>的空穴迁移率的约10％。在曲线75中的空穴迁移率高于曲线76示出的Si<100>的空穴迁移率的约180％。
已经描述和示出的是：
1.MOSFET器件包括在Si<110>衬底上的伪晶SiGe沟道层。
2.通过RTCVD形成伪晶SiGe层的方法和在RTCVD前化学处理硅表面的方法。
3.对本领域的技术人员明显的是在不脱离仅通过附加权利要求的范围限制的本发明的广义范围下，可以进行各种修改和改变。

Claims (24)

1.一种用于传导载流子的结构，包括：
Si或SiGe的单晶衬底，具有<110>的上表面，以及
SiGe伪晶层，在所述衬底上形成，具有的Ge浓度高于所述衬底的Ge浓度，从而所述伪晶层处于压缩应变。
2.根据权利要求1的结构，还包括在所述伪晶层上的栅极介质。
3.根据权利要求2的结构，还包括在所述栅极介质上的栅极电极。
4.根据权利要求3的结构，还包括在所述伪晶层中并分别在所述栅极介质的两侧上形成的源极和漏极区域，以在其之间形成沟道。
5.根据权利要求2的结构，还包括在所述栅极介质上的多晶硅栅极电极以形成MOSFET。
6.根据权利要求2的结构，还包括在所述栅极介质上的多晶硅锗栅极电极。
7.根据权利要求2的结构，还包括在所述栅极介质上的金属和金属硅化物栅极电极中的一个。
8.根据权利要求2的结构，其中所述栅极介质具有大于3.9的介电常数。
9.根据权利要求1的结构，其中所述衬底表面具有0.1nm的RMS。
10.根据权利要求1的结构，其中所述SiGe伪晶层具有小于20nm的厚度。
11.一种用于形成用于传导载流子的结构的方法，包括如下步骤：
选择具有<110>的上表面的Si或SiGe的单晶衬底，以及
在所述衬底上形成SiGe伪晶层，其具有的Ge浓度高于所述衬底的Ge浓度，从而所述伪晶层处于压缩应变。
12.根据权利要求11的方法，还包括在所述伪晶层上形成栅极介质的步骤。
13.根据权利要求12的方法，还包括在所述栅极介质上形成栅极电极的步骤。
14.根据权利要求13的方法，还包括在所述伪晶层中并分别在所述栅极介质的两侧上形成源极和漏极区域以在其之间形成沟道的步骤。
15.根据权利要求12的方法，还包括在所述栅极介质上形成多晶硅栅极电极以形成MOSFET的步骤。
16.根据权利要求12的方法，还包括在所述栅极介质上形成多晶硅锗栅极电极的步骤。
17.根据权利要求12的方法，还包括在所述栅极介质上形成金属和金属硅化物栅极电极中的一个的步骤。
18.根据权利要求12的方法，还包括选择介电常数大于3.9的所述栅极介质的步骤。
19.根据权利要求11的方法，还包括化学处理所述衬底表面到低于0.1nm的RMS的步骤。
20.根据权利要求11的方法，还包括形成厚度小于20nm的所述SiGe伪晶层的步骤。
21.一种用于形成半导体外延层的方法，包括如下步骤：
选择具有<110>的上表面的Si或SiGe的单晶衬底，
将所述单晶衬底载入快速热化学气相沉积工具中，降低所述工具中的气压到低于0.2Torr，
升高所述工具中的温度到600℃，以及
引入含Si气体和含Ge气体，从而在所述衬底上形成SiGe伪晶层，其具有的Ge浓度不同于所述衬底的Ge浓度，从而所述伪晶层处于应变。
22.根据权利要求21的方法，还包括化学处理所述衬底表面到低于0.1nm的RMS粗糙度的步骤。
23.根据权利要求21的方法，还包括在一段时间内降低所述工具中的温度到低于400℃从而停止外延生长的步骤。
24.一种用于外延沉积化学处理衬底的方法，包括如下步骤：
选择具有小于0.2nm的表面粗糙度的Si或SiGe衬底，
将所述衬底浸入在23℃的去离子水中的10PPM臭氧的第一浴中，
将所述衬底浸入HF与水的体积比为100∶1的稀HF的第二浴中至少1分钟，
将所述衬底浸入去离子水的第三浴中至少5分钟，
将所述衬底浸入在23℃的HCl酸和去离子水的体积比至少1∶100的第四浴中，
将所述衬底浸入去离子水的第五浴中至少5分钟，以及
从所述第五浴移出所述衬底，以在包括如氮气的气氛中在至少30℃的温度下干燥所述衬底。
CN2005800153966A 2004-06-24 2005-06-21 压缩SiGe<110>生长的MOSFET器件及其制造方法 Expired - Fee Related CN101160664B (zh)

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