TW200601419A - Compressive SiGe <110> growth and structure of MOSFET devices - Google Patents

Compressive SiGe <110> growth and structure of MOSFET devices

Info

Publication number
TW200601419A
TW200601419A TW094118430A TW94118430A TW200601419A TW 200601419 A TW200601419 A TW 200601419A TW 094118430 A TW094118430 A TW 094118430A TW 94118430 A TW94118430 A TW 94118430A TW 200601419 A TW200601419 A TW 200601419A
Authority
TW
Taiwan
Prior art keywords
substrate
psuedomorphic
sige
forming
epitaxial
Prior art date
Application number
TW094118430A
Other languages
English (en)
Inventor
Kevin K Chan
Kathryn W Guarini
Meikel Leong
Ke-Rn Rim
Min Yang
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200601419A publication Critical patent/TW200601419A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
TW094118430A 2004-06-24 2005-06-03 Compressive SiGe <110> growth and structure of MOSFET devices TW200601419A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/875,727 US7187059B2 (en) 2004-06-24 2004-06-24 Compressive SiGe <110> growth and structure of MOSFET devices

Publications (1)

Publication Number Publication Date
TW200601419A true TW200601419A (en) 2006-01-01

Family

ID=35504690

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118430A TW200601419A (en) 2004-06-24 2005-06-03 Compressive SiGe <110> growth and structure of MOSFET devices

Country Status (6)

Country Link
US (1) US7187059B2 (zh)
EP (1) EP1794786A4 (zh)
JP (1) JP5314891B2 (zh)
CN (1) CN101160664B (zh)
TW (1) TW200601419A (zh)
WO (1) WO2006002410A2 (zh)

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US7473593B2 (en) * 2006-01-11 2009-01-06 International Business Machines Corporation Semiconductor transistors with expanded top portions of gates
FR2896620B1 (fr) * 2006-01-23 2008-05-30 Commissariat Energie Atomique Circuit integre tridimensionnel de type c-mos et procede de fabrication
TW200735344A (en) * 2006-03-03 2007-09-16 Univ Nat Chiao Tung N type metal oxide semiconductor transistor structure having compression strain silicon-germanium channel formed on silicon (110) substrate
US7361574B1 (en) * 2006-11-17 2008-04-22 Sharp Laboratories Of America, Inc Single-crystal silicon-on-glass from film transfer
US20080169535A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Sub-lithographic faceting for mosfet performance enhancement
US20090085169A1 (en) * 2007-09-28 2009-04-02 Willy Rachmady Method of achieving atomically smooth sidewalls in deep trenches, and high aspect ratio silicon structure containing atomically smooth sidewalls
US20090242989A1 (en) * 2008-03-25 2009-10-01 Chan Kevin K Complementary metal-oxide-semiconductor device with embedded stressor
US7972922B2 (en) * 2008-11-21 2011-07-05 Freescale Semiconductor, Inc. Method of forming a semiconductor layer
US8440547B2 (en) * 2009-02-09 2013-05-14 International Business Machines Corporation Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
JP4875115B2 (ja) 2009-03-05 2012-02-15 株式会社東芝 半導体素子及び半導体装置
US8329568B1 (en) * 2010-05-03 2012-12-11 Xilinx, Inc. Semiconductor device and method for making the same
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US9466672B1 (en) 2015-11-25 2016-10-11 International Business Machines Corporation Reduced defect densities in graded buffer layers by tensile strained interlayers
EP3486940A4 (en) * 2016-07-15 2020-02-19 National University Corporation Tokyo University of Agriculture and Technology METHOD FOR MANUFACTURING SEMICONDUCTOR LAMINATE FILM AND SEMICONDUCTOR LAMINATE FILM
JP7215683B2 (ja) * 2019-09-09 2023-01-31 株式会社Sumco 半導体デバイス

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Also Published As

Publication number Publication date
US7187059B2 (en) 2007-03-06
EP1794786A4 (en) 2008-12-24
CN101160664B (zh) 2010-09-08
WO2006002410A2 (en) 2006-01-05
EP1794786A2 (en) 2007-06-13
US20050285159A1 (en) 2005-12-29
WO2006002410A3 (en) 2007-12-06
JP2008504695A (ja) 2008-02-14
CN101160664A (zh) 2008-04-09
JP5314891B2 (ja) 2013-10-16

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