CN1805151A - 具有局部应力结构的金属氧化物半导体场效应晶体管 - Google Patents

具有局部应力结构的金属氧化物半导体场效应晶体管 Download PDF

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CN1805151A
CN1805151A CNA2005100753613A CN200510075361A CN1805151A CN 1805151 A CN1805151 A CN 1805151A CN A2005100753613 A CNA2005100753613 A CN A2005100753613A CN 200510075361 A CN200510075361 A CN 200510075361A CN 1805151 A CN1805151 A CN 1805151A
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layer
stress
stress induced
semiconductor element
semi
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CN100452431C (zh
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陈建豪
蔡邦彦
张志坚
李资良
陈世昌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种具有局部应力结构的金属氧化物半导体场效应晶体管，可于源极/漏极区域形成应力诱导层，该应力诱导层包括第一半导体材料及第二半导体材料。利用一系列作用于第一半导体材料的反应操作形成应力诱导层并迫使第二半导体材料进入应力诱导层下层。该应力诱导层可以位于源极/漏极间的凹陷区域或非凹陷区域。本发明提供一种方法，利用锗硅化物的氮化或氧化工艺使源极/漏极区域产生应力诱导层，此应力诱导层上层可形成氮化或氧化薄膜，并使锗得以进入应力诱导层下层。本发明提供另一方法，产生反应层覆盖于应力诱导层之上，使该反应层与应力诱导层产生交互作用。

Description

具有局部应力结构的金属氧化物半导体场效应晶体管
技术领域
本发明涉及一种半导体相关的元件，特别是涉及一种具有局部应力结构的金属氧化物半导体场效应晶体管及制造此种晶体管的方法。
背景技术
过去十多年来，利用缩减金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistors，MOSFET)尺寸的方式，包括减少栅极的长度以与栅极氧化层的厚度，已经持续改善了集成电路组成元件的操作速度、效能表现、元件密度及单位成本。为了提高晶体管的表现效能，利用位于半导体基材上的部分应变通道区域来制造金属氧化物半导体场效应晶体管元件可增强载子(Carrier)的迁移率(Mobility)，从而提高p型及n型的金属氧化物半导体场效应晶体管使用效率。一般来说，在n型金属氧化物半导体场效应晶体管(NMOSFET)晶体管n型通道上形成的拉伸应变(Tensile Strain)可提高电子由源极往漏极方向的迁移率，而在p型金属氧化物半导体场效应晶体管(PMOSFET)晶体管的p型通道形成的压缩应变(Compressive Strain)则可提高空穴由源极往漏极方向的迁移率。有关于晶体管通道区域中的应变结构已被披露于许多公知技术中。
公知技术中，覆盖的半导体薄层下方是以锗-硅或锗-硅-碳形成的半导体合金层，该半导体合金层具有与覆盖的半导体薄层所不同的晶格结构，不同的晶格结构促使覆盖的半导体形成应变结构以提高载子的迁移率。
然而在此公知例中，除了全面性半导体合金层造成接面漏电效应之外，磊晶成长的半导体合金层中锗元素的计量也难以精确的控制。除此之外，该半导体合金层在源极/漏极间形成不必要的界面也可能导致接合处的漏电效应。
在另一公知例中，在基材上的源极/漏极区域制造凹陷现象可导致通道应变结构的形成，凹陷区域的一层锗硅化物磊晶可造成通道的应变结构。制造工艺中增加锗浓度会增加应变量，但如何提高凹陷区域的锗浓度却是制造工艺中的一大问题，因为在磊晶过程中增加锗的浓度，容易使锗硅化物层形成高密度的位错(Dislocations)及缺陷。另外晶体管栅极氧化层的选择性退化(Degradation)及沉积工艺的窗洞也是值得重视的问题。
因此需要一种有效率且考虑成本效益的方法来诱导产生通道区域的应变结构以增强晶体管的效能。
发明内容
为解决上述和其它的问题，并且达到本发明所主张的技术优点，本发明提供一种具有应变结构的半导体元件及制造此半导体元件的方法，以改善半导体的操作性能。
因此本发明的目的就是提供一种具有局部应力的金属氧化物半导体场效应晶体管，此局部应力包括于源极/漏极区域的凹陷处形成应力诱导层，该应力诱导层包括第一半导体材料及第二半导体材料，借着提高第二半导体材料浓度来达到制造应力诱导层的目的。
本发明的另一目的是提供一种应力诱导层，该应力诱导层位于源极/漏极区域的非凹陷处上。
本发明的又一目的是提供一种于源极/漏极区域制造具有局部应力的金属氧化物半导体场效应晶体管的方法。根据本发明的上述目的，提出一种在源极/漏极区域的凹陷处或非凹陷处形成诱导型应变结构，该诱导型应变结构包含第一半导体材料及第二半导体材料，通过氧化或氮化环境使第一半导体材料与环境中气体反应，并迫使第二半导体材料进入该应力诱导层中。
本发明的又一目的是提供另一种于源极/漏极区域制造具有局部应力的金属氧化物半导体场效应晶体管的方法。根据本发明的上述目的，提出一种在源极/漏极区域的凹陷处或非凹陷处形成诱导型应变结构，该诱导型应变结构包含第一半导体材料及第二半导体材料，利用形成于应力诱导层上的反应层，与第一半导体材料的交互反应，使第二半导体材料进入应力诱导层中。
附图说明
为让本发明的上述和其它目的、特征、优点与实施例能更明显易懂，附图的详细说明如下：
图1到图6为依照本发明的一种于源极/漏极区域上具有局部应力结构的金属氧化物半导体场效应晶体管元件的制造方法。
图7到图8为依照本发明的另一种于源极/漏极区域上具有局部应力结构的金属氧化物半导体场效应晶体管元件的制造方法。主要元件标记说明
100：晶片            110：栅绝缘层
112：栅极            114：基材
210：掩膜            310：凹陷区域
410：应力诱导层      510：空乏层
610：间隙壁          710：反应层
810：已反应层
具体实施方式
本发明的较佳实施例的制造及使用方法如下所述，应注意的是，虽然本发明披露较佳实施例如下，然其并非用以限定本发明的权利要求。
请参照图1到图6，其表示依照本发明所披露的一种具有应变通道结构的半导体元件的制造方法。本发明的实施例可应用于各种电路系统中。参照图1的晶片100，具有栅绝缘层110及栅极112构筑于基材114上，该基材114包含位于硅覆绝缘层(Silicon on insulator，SOI)基材上的硅块材质、掺杂或是未掺杂材质及主动层。一般来说，SOI基材包括位于绝缘层上的半导体材质层例如硅，绝缘层可为氧化埋(Buried Oxide，BOX)层或是氧化硅层。绝缘层可位于硅基材或是玻璃基材上，亦可位于复层基材或是含不同浓度梯度的掺杂物基材上。
在基材114上，以公知的方式形成栅绝缘层110以与栅极112并且进行图案化，其中栅绝缘层110的材质以高介电值材质且介电常数大于4，例如氧化硅、氮氧化硅、氮化硅、氧化物及含氮的氧化物等材质或其所组成的族群为较佳。在一实施例中，栅绝缘层110的材质可为氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪等材质或其所组成的族群。
在一较佳实施例中，栅绝缘层110的材质包括氧化层，可利用任何的氧化环境来形成氧化层，例如在含有氧化物、水份、氮氧化物的环境中进行湿热或干热氧化作用，或是利用四乙基正硅酸盐(Tetra-ethyl-ortho-silicate，TEOS)以及氧作为前驱物进行化学气相沉积(Chemical Vapor Deposition，CVD)工艺。在一实施例中，栅绝缘层110的厚度可介于8至50埃之间，其中以16埃为较佳。
在一实施例中，栅极112的材质包括导电材质，例如钽、钛、钼、钨、铂、铝、铪、钌等金属材质，或钛硅化物、钴硅化物、镍硅化物、钽硅化物等金属硅化物，或钛化氮、钽化氮等金属氮化物，以及掺杂的结晶多晶硅材质或其它导电材质。在一实施例中，沉积非均质硅材质并且进行再结晶化工艺，以形成多晶硅(Poly-crystalline Silicon)。在一较佳实施例中，当栅极112的材质为多晶硅时，主要是以低压化学气相沉积法(Low-pressureChemical Vapor Deposition，LPCVD)沉积掺杂或是未掺杂的多晶硅来形成厚度介于400至2500埃之间的栅极112，其中以1500埃为较佳。
利用公知的光刻工艺对栅绝缘层110与栅极112进行图案化步骤，一般来说，光刻工艺包括沉积光刻胶层、形成掩膜、曝光及显影步骤。在组成光刻胶掩膜图案后即进行蚀刻工艺，以移除多余的栅介电层材质以与栅极材质，形成图1所示的栅绝缘层110与栅极112。在一较佳实施例中，栅极材质可为多晶硅且栅介电层的材质可为氧化物，蚀刻工艺可为湿蚀刻或干蚀刻法、各向异性蚀刻法(Anisotropic Etch)或各向同性蚀刻法(Isotropic Etch)，其中以各向异性干蚀刻法为较佳。
请参照图2，其表示依据本发明的一实施例，在晶片100上形成一层掩膜210以覆盖栅绝缘层110与栅极112。掩膜210主要为防止随后的磊晶工艺中锗硅化物磊晶层沿着栅绝缘层110与栅极112表面生长。一般来说，锗硅化物的磊晶生长包含在特定工艺条件下使硅接触到锗，锗便与暴露的硅共同生长成锗硅化物磊晶层。由于栅绝缘层110与栅极112通常由硅组成，例如二氧化硅及多晶硅，因此利用一个可覆盖栅绝缘层110与栅极112的掩膜，以避免锗硅化物磊晶层于栅绝缘层110与栅极112上生长。
在一实施例中，掩膜210可为通过化学气相沉积法、物理气相沉积法或原子层沉积法或其它沉积方法所形成的整面全区覆盖式氮化硅层。经沉积工艺后，即可以光刻技术进行掩膜210的图案化，掩膜210的厚度以介于0到1000埃之间为较佳。值得注意的是伴随下一步骤所产生的应力结构可形成于邻近区域、间隔处或栅极下方。
请参照图3，其表示依据本发明的一实施例，晶片100进行蚀刻工艺后可在栅极112两侧的任一侧制造凹陷区域310。值得注意的是，通道区域指的是位于该凹陷区域310与栅绝缘层110与栅极112下方之间的基材114部分。
另一个值得注意的是，图1到图6表示依据本发明的较佳实施例中，具有锗硅化物磊晶成长于凹陷区域310的源极/漏极区域。于图1到图6所述的工艺可适用于源极/漏极区域的高锗硅化物区域。另一实施例中，锗硅化物磊晶层可成长于基材114表面但不形成凹陷。并利用本文所述的相同步骤，促使锗向下层扩展从而制造锗浓度较高的区域。
如图3所示，该凹陷区域310可利用氯和溴进行化学性等离子体蚀刻(Plasma Etch)，其凹陷区域的厚度以10至200纳米为较佳。为了后续的磊晶工艺得以顺利完成，可视情况进行退火(Anneal)步骤，通过修复蚀刻过程中造成的损伤部分，使硅化物的表面更为平滑。
请参照图4，其表示依据本发明的一实施例，晶片100经磊晶成长工艺在凹陷区域310产生应力诱导层410(Stress-inducing Layer)，例如锗硅化物。该磊晶工艺可以是化学气相沉积法(CVD)、或超真空化学气相沉积法(UHV-CVD)、分子束磊晶成长。该磊晶层成长材料可能在基材114表面之上或表面之下扩张。较高的源极/漏极区域在此仅为例示而已。本发明的一较佳实施例中，基材114表面上应力诱导层410的厚度为0纳米到200纳米间的范围，该应力诱导层的厚度以10到300纳米为较佳。其它半导体材料如碳化硅、氮锗硅化物及碳氮化硅皆可为之应用。
应力诱导层410包含第一半导体材料及第二半导体材料，该第二半导体材料与第一半导体材料具有不同的晶格结构，以提供通道区域的应变。本发明的一实施例中，以硅作为基材，第一半导体材料可以是硅而第二半导体材料可以为锗，因此该应力诱导层410可以为锗硅化物层。
图5表示在晶片100的应力诱导层410的较低区域中，通过提高第二半导体材料例如锗的操作，于应力诱导层410上形成空乏层510。本发明的一实施例中，应力诱导层410包括锗硅化物，其操作为使该应力诱导层410暴露于充满反应气体或液体的环境中，使环境中气体或液体可与锗硅化物中的硅反应，借着该反应产生空乏层510，且空乏层510包含了SiX，其中X代表其它的材料。如图5的箭头方向所示，其中空乏层510的锗进一步的向下扩展进入应力诱导层410中。在本发明的一较佳实施例中，空乏层510下方的应力诱导层410显示出由应力诱导层410上层至底层持续变化的锗浓度梯度，且其浓度改变至少大于5％。
在本发明的一实施例中，其操作方式包括加热工艺(标准高温炉/快速加热步骤)、等离子体处理、紫外线固化、植入等，或类似的操作如添加氧化型气体如氧气、水、氢气、一氧化二氮、一氧化氮及臭氧等，温度大约介于100℃至1200℃之间，于本实施例中，空乏层可包含氧化硅(SixOy)薄膜。
于另一实施例中，操作方式包括加热工艺(标准高温炉/快速加热步骤)、等离子体处理、紫外线固化、植入等，或类似的操作如添加氮化型气体如氨气、氮气、一氧化氮及一氧化二氮等，温度大约介于100℃至1200℃之间，于本实施例中，空乏层可包含氮化硅(SixNy)或氮氧化硅(SixOyNz)。其它可使硅反应但使锗不反应或仅有轻微反应的环境及/或操作亦可为本发明的应用范畴。
图6表示本发明的一实施例中，利用氢氟酸(Hydrofluoric acid)浸湿或干蚀刻(Dry Etch)工艺移除掩膜210，并产生间隙壁610。间隙壁610作为间隔之用，以便经一次或一次以上的离子植入(Ion Implants)制造出源极/漏极区域，其中材质包括氮化硅(Si3N4)，如氮化硅(SixNy)或氮氧化硅(SiOxNy)、脂类氮氧化硅(SiOxNy:Hz)或其所组成的群组。在本发明的一较佳实施例中，间隙壁610的形成以硅甲烷(Silane)及氨气为气体前驱物并利用化学气相沉积法形成氮化硅层。
间隙壁610可通过各向同性或各向异性蚀刻工艺产生，例如利用磷酸于各向同性蚀刻工艺中。由于氮化硅层的厚度邻近栅极112时最大，各向同性蚀刻工艺除去栅极112之上及覆盖于基材114的区域未靠近栅极112部分的氮化硅层材料，仅留下如图6所示的间隙壁610部分。本发明的一实施例中，间隙壁610的宽度大约介于1至100纳米之间。值得注意的是部分的应力诱导层410可能位于间隙壁610之下，视源极/漏极区域所需的植入及其电性特征而定。
图7和图8表示本发明的第二实施例，利用本发明的磊晶成长工艺形成锗硅化物层。图7和图8中所例举的第二实施例假设有制备方式如图1到图4的晶片，该图标标号说明亦相同。图7显示图4的晶片100，其中反应层710形成于应力诱导层410之上。
于特定的条件下，反应层710可与锗硅化物的硅产生反应但不与锗发生反应，以此方法，反应层710可以与硅反应而迫使锗硅化物层的锗进入下层，从而提高锗的浓度。在本发明的实施例中，反应层710的材质可以为钴、镍或钛或其它任何可应用于化学气相沉积、或物理气相沉积或原子层沉积工艺的材质。
图8表示反应层710与应力诱导层410经操作反应后产生的已反应层(Reacted Layer)810，该操作步骤可以是任何能使反应层710与应力诱导层410上的硅反应的操作，由于此反应的进行使得已反应层810产生并使锗得以进入应力诱导层410下方，其方向如图8的箭头所示。值得注意的是一部分的已反应层810乃是由部分的应力诱导层410所产生的，如此一来当锗原子维持相对恒定的同时，应力诱导层410则会减少，因而提高了锗在应力诱导层410中的浓度。
本发明的一实施例中，包含操作步骤如加热退火(Thermal Annealing)，其环境包括含氧气体、含氮气体或其所组成的群组，其温度范围则介于100℃至1200℃之间。亦可能包含其它操作步骤例如快速加热退火(Rapid-thermal Annealing)，或激光、紫外线固化、电子束固化，植入技术、等离子体技术、紫外线辐射技术等。
经上述步骤后可移去掩膜210并制造出间隙壁，接着进行后续操作，步骤及方法皆已详述于图6中。
在一实施例中，形成介于该应力诱导层410上层至下层的具有浓度梯度的连续型变异的晶格常数结构，其变异程度至少为0.2％，其上层区域显示出具有大于下层区域的晶格常数。此外，由于应力诱导层410影响而产生应力，故基材上的通道区域的晶格常数要比基材较低部分要小。
虽然本发明已用较佳实施例披露如上，然其并非用以限定本发明，任何所属技术领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与改进，因此本发明的保护范围当视权利要求所界定者为准。

Claims (11)

1.一种半导体元件，其特征是该元件至少包含：
形成于基材上的栅极；以及
形成于栅极任一侧的源极/漏极区域；
其中该源极/漏极区域包含应力诱导层，至少包含第一半导体材料及第二半导体材料，其中第二半导体材料的浓度，靠近该应力诱导层表面上层的浓度大于下层。
2.根据权利要求1所述的半导体元件，其特征是该第一半导体材料为硅，该第二半导体材料为锗。
3.根据权利要求1所述的半导体元件，其特征是该应力诱导层的该第二半导体材料的浓度，靠近表面上层的浓度大于下层至少5％。
4.根据权利要求1所述的半导体元件，其特征是该应力诱导层的上表面高于该基材的上表面。
5.根据权利要求1所述的半导体元件，其特征是该应力诱导层的厚度范围为10至300纳米。
6.根据权利要求1所述的半导体元件，其特征是该应力诱导层位于该基材上的凹陷处。
7.根据权利要求1所述的半导体元件，其特征是该应力诱导层为一种高应力层，可于该基材上的非凹陷处形成。
8.根据权利要求1所述的半导体元件，其特征是该应力诱导层的位置为距离栅极0至300纳米之间。
9.根据权利要求1所述的半导体元件，其特征是该应力诱导层包含具有不同晶格常数的梯度层。
10.根据权利要求9所述的半导体元件，其特征是该梯度层上层区域具有大于层区域的晶格常数。
11.根据权利要求9所述的半导体元件，其特征是该应力诱导层上层区域的第一晶格常数大于下层区域的第二晶格常数0.2％。
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